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From: Conor Dooley <conor@kernel.org>
To: claudiu.beznea@tuxon.dev, Conor Dooley <conor@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	pierre-henry.moussay@microchip.com,
	valentina.fernandezalanis@microchip.com,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: (subset) [PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code
Date: Tue, 21 Oct 2025 14:31:29 +0100	[thread overview]
Message-ID: <20251021-ranked-attendee-8caed80461b2@spud> (raw)
In-Reply-To: <20251013-album-bovine-faf9f5ebc5d4@spud>

From: Conor Dooley <conor.dooley@microchip.com>

On Mon, 13 Oct 2025 18:45:32 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> In v5 the only real change is that I removed the attempt at a common
> implementation of regmap-based divider/gate clocks. The series hasn't
> managed to receive feedback on my approach in 2025, despite sending
> several revisions and bumps, and it is blocking support for both new
> drivers (gpio interrupt support, pinctrl and hwmon off the top of my
> head) and a new platform so I have decided to strip out the attempt at
> making something common in exchange for something that can be merged
> through the clk-microchip tree without relying on feedback from the
> clock maintainers.
> 
> [...]

Applied to riscv-soc-drivers-for-next, because the pinctrl series that
I am working on needs them.

[1/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC
      https://git.kernel.org/conor/c/feaa716adc51
[2/9] soc: microchip: add mfd drivers for two syscon regions on PolarFire SoC
      https://git.kernel.org/conor/c/5b59e62532fc

Thanks,
Conor.

      parent reply	other threads:[~2025-10-21 13:32 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 17:45 [PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code Conor Dooley
2025-10-13 17:45 ` [PATCH v5 1/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Conor Dooley
2025-10-13 17:45 ` [PATCH v5 2/9] soc: microchip: add mfd drivers for two syscon regions " Conor Dooley
2025-10-23  4:04   ` Claudiu Beznea
2025-10-23  9:12     ` Conor Dooley
2025-10-23 10:15     ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 3/9] reset: mpfs: add non-auxiliary bus probing Conor Dooley
2025-10-23  4:06   ` Claudiu Beznea
2025-10-24 10:07     ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 4/9] dt-bindings: clk: microchip: mpfs: remove first reg region Conor Dooley
2025-10-13 17:45 ` [PATCH v5 5/9] clk: microchip: mpfs: use regmap for clocks Conor Dooley
2025-10-23  4:06   ` Claudiu Beznea
2025-10-23 14:42     ` Brian Masney
2025-10-24 10:20     ` Conor Dooley
2025-10-24 10:30       ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 6/9] riscv: dts: microchip: fix mailbox description Conor Dooley
2025-10-13 17:45 ` [PATCH v5 7/9] riscv: dts: microchip: convert clock and reset to use syscon Conor Dooley
2025-10-13 17:45 ` [PATCH v5 8/9] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Conor Dooley
2025-10-13 17:45 ` [PATCH v5 9/9] MAINTAINERS: rename " Conor Dooley
2025-10-21 13:31 ` Conor Dooley [this message]

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