* [PATCH v3 1/5] dt-bindings: pinctrl: document pic64gx "gpio2" pinmux
2025-10-22 10:09 [PATCH v3 0/5] Microchip mpfs/pic64gx pinctrl Conor Dooley
@ 2025-10-22 10:09 ` Conor Dooley
2025-10-22 10:09 ` [PATCH v3 2/5] pinctrl: add pic64gx "gpio2" pinmux driver Conor Dooley
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2025-10-22 10:09 UTC (permalink / raw)
To: linus.walleij
Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
linux-kernel, linux-gpio, devicetree, Valentina.FernandezAlanis
From: Conor Dooley <conor.dooley@microchip.com>
The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The
documentation for the SoC provides no name for this device, but it is
used to swap pins between either GPIO controller #2 or select other
functions, hence the "gpio2" name. Currently there is no documentation
about what each bit actually does that is publicly available, nor (I
believe) what pins are affected. That info is as follows:
pin role (1/0)
--- ----------
E14 MAC_0_MDC/GPIO_2_0
E15 MAC_0_MDIO/GPIO_2_1
F16 MAC_1_MDC/GPIO_2_2
F17 MAC_1_MDIO/GPIO_2_3
D19 SPI_0_CLK/GPIO_2_4
B18 SPI_0_SS0/GPIO_2_5
B10 CAN_0_RXBUS/GPIO_2_6
C14 PCIE_PERST_2#/GPIO_2_7
E18 PCIE_WAKE#/GPIO_2_8
D18 PCIE_PERST_1#/GPIO_2_9
E19 SPI_0_DO/GPIO_2_10
C7 SPI_0_DI/GPIO_2_11
D6 QSPI_SS0/GPIO_2_12
D7 QSPI_CLK (B)/GPIO_2_13
C9 QSPI_DATA0/GPIO_2_14
C10 QSPI_DATA1/GPIO_2_15
A5 QSPI_DATA2/GPIO_2_16
A6 QSPI_DATA3/GPIO_2_17
D8 MMUART_3_RXD/GPIO_2_18
D9 MMUART_3_TXD/GPIO_2_19
B8 MMUART_4_RXD/GPIO_2_20
A8 MMUART_4_TXD/GPIO_2_21
C12 CAN_1_TXBUS/GPIO_2_22
B12 CAN_1_RXBUS/GPIO_2_23
A11 CAN_0_TX_EBL_N/GPIO_2_24
A10 CAN_1_TX_EBL_N/GPIO_2_25
D11 MMUART_2_RXD/GPIO_2_26
C11 MMUART_2_TXD/GPIO_2_27
B9 CAN_0_TXBUS/GPIO_2_28
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
| 73 +++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
--git a/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
new file mode 100644
index 000000000000..07d6befb299c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PIC64GX GPIO2 Mux
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description:
+ The "GPIO2 Mux" determines whether GPIO2 or select other functions are
+ available on package pins on PIC64GX. Some of these functions must be
+ mapped to this mux via iomux0 for settings here to have any impact.
+
+properties:
+ compatible:
+ const: microchip,pic64gx-pinctrl-gpio2
+
+ reg:
+ maxItems: 1
+
+ pinctrl-use-default: true
+
+patternProperties:
+ '^mux-':
+ type: object
+ additionalProperties: false
+
+ properties:
+ function:
+ description:
+ A string containing the name of the function to mux to the group.
+ enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2, gpio ]
+
+ groups:
+ description:
+ An array of strings. Each string contains the name of a group.
+ items:
+ enum: [ mdio0, mdio1, spi0, can0, pcie, qspi, uart3, uart4, can1, uart2,
+ gpio_mdio0, gpio_mdio1, gpio_spi0, gpio_can0, gpio_pcie,
+ gpio_qspi, gpio_uart3, gpio_uart4, gpio_can1, gpio_uart2 ]
+
+ required:
+ - function
+ - groups
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ pinctrl@41000000 {
+ compatible = "microchip,pic64gx-pinctrl-gpio2";
+ reg = <0x41000000 0x4>;
+ pinctrl-use-default;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_gpio2>, <&mdio1_gpio2>, <&spi0_gpio2>, <&qspi_gpio2>,
+ <&uart3_gpio2>, <&uart4_gpio2>, <&can1_gpio2>, <&can0_gpio2>,
+ <&uart2_gpio2>;
+
+ mux-gpio2 {
+ function = "gpio";
+ groups = "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie",
+ "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1";
+ };
+ };
+
+...
--
2.51.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 2/5] pinctrl: add pic64gx "gpio2" pinmux driver
2025-10-22 10:09 [PATCH v3 0/5] Microchip mpfs/pic64gx pinctrl Conor Dooley
2025-10-22 10:09 ` [PATCH v3 1/5] dt-bindings: pinctrl: document pic64gx "gpio2" pinmux Conor Dooley
@ 2025-10-22 10:09 ` Conor Dooley
2025-10-22 10:09 ` [PATCH v3 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux Conor Dooley
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2025-10-22 10:09 UTC (permalink / raw)
To: linus.walleij
Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
linux-kernel, linux-gpio, devicetree, Valentina.FernandezAlanis
From: Conor Dooley <conor.dooley@microchip.com>
The pic64gx has a second pinmux "downstream" of the iomux0 pinmux. The
documentation for the SoC provides no name for this device, but it is
used to swap pins between either GPIO controller #2 or select other
functions, hence the "gpio2" name. Add a driver for it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-pic64gx-gpio2.c | 356 ++++++++++++++++++++++++
3 files changed, 365 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-pic64gx-gpio2.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4f8507ebbdac..e83fda9bf308 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -486,6 +486,14 @@ config PINCTRL_PIC32MZDA
def_bool y if PIC32MZDA
select PINCTRL_PIC32
+config PINCTRL_PIC64GX
+ bool "pic64gx gpio2 pinctrl driver"
+ depends on ARCH_MICROCHIP || COMPILE_TEST
+ select GENERIC_PINCONF
+ default y
+ help
+ This selects the pinctrl driver for gpio2 on pic64gx.
+
config PINCTRL_PISTACHIO
bool "IMG Pistachio SoC pinctrl driver"
depends on OF && (MIPS || COMPILE_TEST)
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index e0cfb9b7c99b..f33976a6c91b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_PINCTRL_OCELOT) += pinctrl-ocelot.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
+obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
diff --git a/drivers/pinctrl/pinctrl-pic64gx-gpio2.c b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c
new file mode 100644
index 000000000000..f322bb5e6181
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-pic64gx-gpio2.c
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/seq_file.h>
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "pinctrl-utils.h"
+
+#define PIC64GX_PINMUX_REG 0x0
+
+static const struct regmap_config pic64gx_gpio2_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+ .max_register = 0x0,
+};
+
+struct pic64gx_gpio2_pinctrl {
+ struct pinctrl_dev *pctrl;
+ struct device *dev;
+ struct regmap *regmap;
+ struct pinctrl_desc desc;
+};
+
+struct pic64gx_gpio2_pin_group {
+ const char *name;
+ const unsigned int *pins;
+ const unsigned int num_pins;
+ u32 mask;
+ u32 setting;
+};
+
+struct pic64gx_gpio2_function {
+ const char *name;
+ const char * const *groups;
+ const unsigned int num_groups;
+};
+
+static const struct pinctrl_pin_desc pic64gx_gpio2_pins[] = {
+ PINCTRL_PIN(0, "E14"),
+ PINCTRL_PIN(1, "E15"),
+ PINCTRL_PIN(2, "F16"),
+ PINCTRL_PIN(3, "F17"),
+ PINCTRL_PIN(4, "D19"),
+ PINCTRL_PIN(5, "B18"),
+ PINCTRL_PIN(6, "B10"),
+ PINCTRL_PIN(7, "C14"),
+ PINCTRL_PIN(8, "E18"),
+ PINCTRL_PIN(9, "D18"),
+ PINCTRL_PIN(10, "E19"),
+ PINCTRL_PIN(11, "C7"),
+ PINCTRL_PIN(12, "D6"),
+ PINCTRL_PIN(13, "D7"),
+ PINCTRL_PIN(14, "C9"),
+ PINCTRL_PIN(15, "C10"),
+ PINCTRL_PIN(16, "A5"),
+ PINCTRL_PIN(17, "A6"),
+ PINCTRL_PIN(18, "D8"),
+ PINCTRL_PIN(19, "D9"),
+ PINCTRL_PIN(20, "B8"),
+ PINCTRL_PIN(21, "A8"),
+ PINCTRL_PIN(22, "C12"),
+ PINCTRL_PIN(23, "B12"),
+ PINCTRL_PIN(24, "A11"),
+ PINCTRL_PIN(25, "A10"),
+ PINCTRL_PIN(26, "D11"),
+ PINCTRL_PIN(27, "C11"),
+ PINCTRL_PIN(28, "B9"),
+};
+
+static const unsigned int pic64gx_gpio2_mdio0_pins[] = {
+ 0, 1
+};
+
+static const unsigned int pic64gx_gpio2_mdio1_pins[] = {
+ 2, 3
+};
+
+static const unsigned int pic64gx_gpio2_spi0_pins[] = {
+ 4, 5, 10, 11
+};
+
+static const unsigned int pic64gx_gpio2_can0_pins[] = {
+ 6, 24, 28
+};
+
+static const unsigned int pic64gx_gpio2_pcie_pins[] = {
+ 7, 8, 9
+};
+
+static const unsigned int pic64gx_gpio2_qspi_pins[] = {
+ 12, 13, 14, 15, 16, 17
+};
+
+static const unsigned int pic64gx_gpio2_uart3_pins[] = {
+ 18, 19
+};
+
+static const unsigned int pic64gx_gpio2_uart4_pins[] = {
+ 20, 21
+};
+
+static const unsigned int pic64gx_gpio2_can1_pins[] = {
+ 22, 23, 25
+};
+
+static const unsigned int pic64gx_gpio2_uart2_pins[] = {
+ 26, 27
+};
+
+#define PIC64GX_PINCTRL_GROUP(_name, _mask) { \
+ .name = "gpio_" #_name, \
+ .pins = pic64gx_gpio2_##_name##_pins, \
+ .num_pins = ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \
+ .mask = _mask, \
+ .setting = 0x0, \
+}, { \
+ .name = #_name, \
+ .pins = pic64gx_gpio2_##_name##_pins, \
+ .num_pins = ARRAY_SIZE(pic64gx_gpio2_##_name##_pins), \
+ .mask = _mask, \
+ .setting = _mask, \
+}
+
+static const struct pic64gx_gpio2_pin_group pic64gx_gpio2_pin_groups[] = {
+ PIC64GX_PINCTRL_GROUP(mdio0, BIT(0) | BIT(1)),
+ PIC64GX_PINCTRL_GROUP(mdio1, BIT(2) | BIT(3)),
+ PIC64GX_PINCTRL_GROUP(spi0, BIT(4) | BIT(5) | BIT(10) | BIT(11)),
+ PIC64GX_PINCTRL_GROUP(can0, BIT(6) | BIT(24) | BIT(28)),
+ PIC64GX_PINCTRL_GROUP(pcie, BIT(7) | BIT(8) | BIT(9)),
+ PIC64GX_PINCTRL_GROUP(qspi, GENMASK(17, 12)),
+ PIC64GX_PINCTRL_GROUP(uart3, BIT(18) | BIT(19)),
+ PIC64GX_PINCTRL_GROUP(uart4, BIT(20) | BIT(21)),
+ PIC64GX_PINCTRL_GROUP(can1, BIT(22) | BIT(23) | BIT(25)),
+ PIC64GX_PINCTRL_GROUP(uart2, BIT(26) | BIT(27)),
+};
+
+static const char * const pic64gx_gpio2_gpio_groups[] = {
+ "gpio_mdio0", "gpio_mdio1", "gpio_spi0", "gpio_can0", "gpio_pcie",
+ "gpio_qspi", "gpio_uart3", "gpio_uart4", "gpio_can1", "gpio_uart2"
+};
+
+static const char * const pic64gx_gpio2_mdio0_groups[] = {
+ "mdio0"
+};
+
+static const char * const pic64gx_gpio2_mdio1_groups[] = {
+ "mdio1"
+};
+
+static const char * const pic64gx_gpio2_spi0_groups[] = {
+ "spi0"
+};
+
+static const char * const pic64gx_gpio2_can0_groups[] = {
+ "can0"
+};
+
+static const char * const pic64gx_gpio2_pcie_groups[] = {
+ "pcie"
+};
+
+static const char * const pic64gx_gpio2_qspi_groups[] = {
+ "qspi"
+};
+
+static const char * const pic64gx_gpio2_uart3_groups[] = {
+ "uart3"
+};
+
+static const char * const pic64gx_gpio2_uart4_groups[] = {
+ "uart4"
+};
+
+static const char * const pic64gx_gpio2_can1_groups[] = {
+ "can1"
+};
+
+static const char * const pic64gx_gpio2_uart2_groups[] = {
+ "uart2"
+};
+
+#define PIC64GX_PINCTRL_FUNCTION(_name) { \
+ .name = #_name, \
+ .groups = pic64gx_gpio2_##_name##_groups, \
+ .num_groups = ARRAY_SIZE(pic64gx_gpio2_##_name##_groups), \
+}
+
+static const struct pic64gx_gpio2_function pic64gx_gpio2_functions[] = {
+ PIC64GX_PINCTRL_FUNCTION(gpio),
+ PIC64GX_PINCTRL_FUNCTION(mdio0),
+ PIC64GX_PINCTRL_FUNCTION(mdio1),
+ PIC64GX_PINCTRL_FUNCTION(spi0),
+ PIC64GX_PINCTRL_FUNCTION(can0),
+ PIC64GX_PINCTRL_FUNCTION(pcie),
+ PIC64GX_PINCTRL_FUNCTION(qspi),
+ PIC64GX_PINCTRL_FUNCTION(uart3),
+ PIC64GX_PINCTRL_FUNCTION(uart4),
+ PIC64GX_PINCTRL_FUNCTION(can1),
+ PIC64GX_PINCTRL_FUNCTION(uart2),
+};
+
+static void pic64gx_gpio2_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
+ unsigned int pin)
+{
+ struct pic64gx_gpio2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 val;
+
+ regmap_read(pctrl->regmap, PIC64GX_PINMUX_REG, &val);
+ val = (val & BIT(pin)) >> pin;
+ seq_printf(seq, "pin: %u val: %x\n", pin, val);
+}
+
+static int pic64gx_gpio2_groups_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(pic64gx_gpio2_pin_groups);
+}
+
+static const char *pic64gx_gpio2_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
+{
+ return pic64gx_gpio2_pin_groups[selector].name;
+}
+
+static int pic64gx_gpio2_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
+ const unsigned int **pins, unsigned int *num_pins)
+{
+ *pins = pic64gx_gpio2_pin_groups[selector].pins;
+ *num_pins = pic64gx_gpio2_pin_groups[selector].num_pins;
+
+ return 0;
+}
+
+static const struct pinctrl_ops pic64gx_gpio2_pinctrl_ops = {
+ .get_groups_count = pic64gx_gpio2_groups_count,
+ .get_group_name = pic64gx_gpio2_group_name,
+ .get_group_pins = pic64gx_gpio2_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinctrl_utils_free_map,
+ .pin_dbg_show = pic64gx_gpio2_pin_dbg_show,
+};
+
+static int pic64gx_gpio2_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(pic64gx_gpio2_functions);
+}
+
+static const char *pic64gx_gpio2_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return pic64gx_gpio2_functions[selector].name;
+}
+
+static int pic64gx_gpio2_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ *groups = pic64gx_gpio2_functions[selector].groups;
+ *num_groups = pic64gx_gpio2_functions[selector].num_groups;
+
+ return 0;
+}
+
+static int pic64gx_gpio2_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
+ unsigned int gsel)
+{
+ struct pic64gx_gpio2_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ struct device *dev = pctrl->dev;
+ const struct pic64gx_gpio2_pin_group *group;
+ const struct pic64gx_gpio2_function *function;
+
+ group = &pic64gx_gpio2_pin_groups[gsel];
+ function = &pic64gx_gpio2_functions[fsel];
+
+ dev_dbg(dev, "Setting func %s mask %x setting %x\n",
+ function->name, group->mask, group->setting);
+ regmap_assign_bits(pctrl->regmap, PIC64GX_PINMUX_REG, group->mask, group->setting);
+
+ return 0;
+}
+
+static const struct pinmux_ops pic64gx_gpio2_pinmux_ops = {
+ .get_functions_count = pic64gx_gpio2_pinmux_get_funcs_count,
+ .get_function_name = pic64gx_gpio2_pinmux_get_func_name,
+ .get_function_groups = pic64gx_gpio2_pinmux_get_groups,
+ .set_mux = pic64gx_gpio2_pinmux_set_mux,
+};
+
+static int pic64gx_gpio2_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct pic64gx_gpio2_pinctrl *pctrl;
+ void __iomem *base;
+
+ pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
+ if (!pctrl)
+ return -ENOMEM;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base)) {
+ dev_err(dev, "Failed get resource\n");
+ return PTR_ERR(base);
+ }
+
+ pctrl->regmap = devm_regmap_init_mmio(dev, base, &pic64gx_gpio2_regmap_config);
+ if (IS_ERR(pctrl->regmap)) {
+ dev_err(dev, "Failed to map regmap\n");
+ return PTR_ERR(pctrl->regmap);
+ }
+
+ pctrl->desc.name = dev_name(dev);
+ pctrl->desc.pins = pic64gx_gpio2_pins;
+ pctrl->desc.npins = ARRAY_SIZE(pic64gx_gpio2_pins);
+ pctrl->desc.pctlops = &pic64gx_gpio2_pinctrl_ops;
+ pctrl->desc.pmxops = &pic64gx_gpio2_pinmux_ops;
+ pctrl->desc.owner = THIS_MODULE;
+
+ pctrl->dev = dev;
+
+ platform_set_drvdata(pdev, pctrl);
+
+ pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
+ if (IS_ERR(pctrl->pctrl))
+ return PTR_ERR(pctrl->pctrl);
+
+ return 0;
+}
+
+static const struct of_device_id pic64gx_gpio2_of_match[] = {
+ { .compatible = "microchip,pic64gx-pinctrl-gpio2" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, pic64gx_gpio2_of_match);
+
+static struct platform_driver pic64gx_gpio2_driver = {
+ .driver = {
+ .name = "pic64gx-pinctrl-gpio2",
+ .of_match_table = pic64gx_gpio2_of_match,
+ },
+ .probe = pic64gx_gpio2_probe,
+};
+module_platform_driver(pic64gx_gpio2_driver);
+
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("pic64gx gpio2 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.51.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux
2025-10-22 10:09 [PATCH v3 0/5] Microchip mpfs/pic64gx pinctrl Conor Dooley
2025-10-22 10:09 ` [PATCH v3 1/5] dt-bindings: pinctrl: document pic64gx "gpio2" pinmux Conor Dooley
2025-10-22 10:09 ` [PATCH v3 2/5] pinctrl: add pic64gx "gpio2" pinmux driver Conor Dooley
@ 2025-10-22 10:09 ` Conor Dooley
2025-10-22 17:12 ` Conor Dooley
2025-10-22 10:09 ` [PATCH v3 4/5] pinctrl: add polarfire soc iomux0 pinmux driver Conor Dooley
2025-10-22 10:09 ` [PATCH v3 5/5] MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry Conor Dooley
4 siblings, 1 reply; 7+ messages in thread
From: Conor Dooley @ 2025-10-22 10:09 UTC (permalink / raw)
To: linus.walleij
Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
linux-kernel, linux-gpio, devicetree, Valentina.FernandezAlanis
From: Conor Dooley <conor.dooley@microchip.com>
On Polarfire SoC, iomux0 is responsible for routing functions to either
Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
can either interface with custom RTL or be routed to the FPGA fabric's
IOs. Document it.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip,mpfs-pinctrl-iomux0.yaml | 88 +++++++++++++++++++
.../microchip,mpfs-mss-top-sysreg.yaml | 13 ++-
2 files changed, 100 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
new file mode 100644
index 000000000000..2b718de83a83
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire SoC iomux0
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description:
+ iomux0 is responsible for routing some functions to either the FPGA fabric,
+ or to MSSIOs. It only performs muxing, and has no IO configuration role, as
+ fabric IOs are configured separately and just routing a function to MSSIOs is
+ not sufficient for it to actually get mapped to an MSSIO, just makes it
+ possible.
+
+properties:
+ compatible:
+ oneOf:
+ - const: microchip,mpfs-pinctrl-iomux0
+ - items:
+ - const: microchip,pic64gx-pinctrl-iomux0
+ - const: microchip,mpfs-pinctrl-iomux0
+
+ reg:
+ maxItems: 1
+
+ pinctrl-use-default: true
+
+patternProperties:
+ '^mux-':
+ type: object
+ additionalProperties: false
+
+ properties:
+ function:
+ description:
+ A string containing the name of the function to mux to the group.
+ enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, uart2,
+ uart3, uart4, mdio0, mdio1 ]
+
+ groups:
+ description:
+ An array of strings. Each string contains the name of a group.
+ items:
+ enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_fabric,
+ i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_mssio,
+ can1_fabric, can1_mssio, qspi_fabric, qspi_mssio,
+ uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio,
+ uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio,
+ uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio,
+ mdio1_fabric, mdio1_mssio ]
+
+ required:
+ - function
+ - groups
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #size-cells = <1>;
+ #address-cells = <1>;
+
+ pinctrl@200 {
+ compatible = "microchip,mpfs-pinctrl-iomux0";
+ reg = <0x200 0x4>;
+
+ mux-spi0-fabric {
+ function = "spi0";
+ groups = "spi0_fabric";
+ };
+
+ mux-spi1-mssio {
+ function = "spi1";
+ groups = "spi1_mssio";
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
index 1ab691db8795..39987f722411 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-mss-top-sysreg.yaml
@@ -18,10 +18,17 @@ properties:
items:
- const: microchip,mpfs-mss-top-sysreg
- const: syscon
+ - const: simple-mfd
reg:
maxItems: 1
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
'#reset-cells':
description:
The AHB/AXI peripherals on the PolarFire SoC have reset support, so
@@ -31,6 +38,10 @@ properties:
of PolarFire clock/reset IDs.
const: 1
+ pinctrl@200:
+ type: object
+ $ref: /schemas/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
+
required:
- compatible
- reg
@@ -40,7 +51,7 @@ additionalProperties: false
examples:
- |
syscon@20002000 {
- compatible = "microchip,mpfs-mss-top-sysreg", "syscon";
+ compatible = "microchip,mpfs-mss-top-sysreg", "syscon", "simple-mfd";
reg = <0x20002000 0x1000>;
#reset-cells = <1>;
};
--
2.51.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v3 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux
2025-10-22 10:09 ` [PATCH v3 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux Conor Dooley
@ 2025-10-22 17:12 ` Conor Dooley
0 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2025-10-22 17:12 UTC (permalink / raw)
To: linus.walleij
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, linux-kernel,
linux-gpio, devicetree, Valentina.FernandezAlanis
[-- Attachment #1: Type: text/plain, Size: 1871 bytes --]
On Wed, Oct 22, 2025 at 11:09:11AM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> On Polarfire SoC, iomux0 is responsible for routing functions to either
> Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
> can either interface with custom RTL or be routed to the FPGA fabric's
> IOs. Document it.
>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> +patternProperties:
> + '^mux-':
> + type: object
> + additionalProperties: false
> +
> + properties:
> + function:
> + description:
> + A string containing the name of the function to mux to the group.
> + enum: [ spi0, spi1, i2c0, i2c1, can0, can1, qspi, uart0, uart1, uart2,
> + uart3, uart4, mdio0, mdio1 ]
> +
> + groups:
> + description:
> + An array of strings. Each string contains the name of a group.
> + items:
> + enum: [ spi0_fabric, spi0_mssio, spi1_fabric, spi1_mssio, i2c0_fabric,
> + i2c0_mssio, i2c1_fabric, i2c1_mssio, can0_fabric, can0_mssio,
> + can1_fabric, can1_mssio, qspi_fabric, qspi_mssio,
> + uart0_fabric, uart0_mssio, uart1_fabric, uart1_mssio,
> + uart2_fabric, uart2_mssio, uart3_fabric, uart3_mssio,
> + uart4_fabric, uart4_mssio, mdio0_fabric, mdio0_mssio,
> + mdio1_fabric, mdio1_mssio ]
> +
> + required:
> + - function
> + - groups
I realised a few minutes ago that, despite Rob's review, there's a
mistake here. This, and the gpio2 binding, are both missing a
pinmux-node reference in these child nodes, since that's where the
types for function/groups come from.
I guess I'll send another version tomorrow Linus.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v3 4/5] pinctrl: add polarfire soc iomux0 pinmux driver
2025-10-22 10:09 [PATCH v3 0/5] Microchip mpfs/pic64gx pinctrl Conor Dooley
` (2 preceding siblings ...)
2025-10-22 10:09 ` [PATCH v3 3/5] dt-bindings: pinctrl: document polarfire soc iomux0 pinmux Conor Dooley
@ 2025-10-22 10:09 ` Conor Dooley
2025-10-22 10:09 ` [PATCH v3 5/5] MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry Conor Dooley
4 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2025-10-22 10:09 UTC (permalink / raw)
To: linus.walleij
Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
linux-kernel, linux-gpio, devicetree, Valentina.FernandezAlanis
From: Conor Dooley <conor.dooley@microchip.com>
On Polarfire SoC, iomux0 is responsible for routing functions to either
Multiprocessor Subsystem (MSS) IOs or to the FPGA fabric, where they
can either interface with custom RTL or be routed to the FPGA fabric's
IOs. Add a driver for it.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/pinctrl/Kconfig | 8 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-mpfs-iomux0.c | 278 ++++++++++++++++++++++++++
3 files changed, 287 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-mpfs-iomux0.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e83fda9bf308..4ec2bb7f67cf 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -505,6 +505,14 @@ config PINCTRL_PISTACHIO
help
This support pinctrl and GPIO driver for IMG Pistachio SoC.
+config PINCTRL_POLARFIRE_SOC
+ bool "Polarfire SoC pinctrl driver"
+ depends on ARCH_MICROCHIP || COMPILE_TEST
+ select GENERIC_PINCONF
+ default y
+ help
+ This selects the pinctrl driver for Microchip Polarfire SoC.
+
config PINCTRL_RK805
tristate "Pinctrl and GPIO driver for RK805 PMIC"
depends on MFD_RK8XX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index f33976a6c91b..ea4e890766e1 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_PINCTRL_PEF2256) += pinctrl-pef2256.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PIC64GX) += pinctrl-pic64gx-gpio2.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
+obj-$(CONFIG_PINCTRL_POLARFIRE_SOC) += pinctrl-mpfs-iomux0.o
obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o
diff --git a/drivers/pinctrl/pinctrl-mpfs-iomux0.c b/drivers/pinctrl/pinctrl-mpfs-iomux0.c
new file mode 100644
index 000000000000..49d9fcec0a16
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mpfs-iomux0.c
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/seq_file.h>
+
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-utils.h"
+#include "pinconf.h"
+#include "pinmux.h"
+
+#define MPFS_IOMUX0_REG 0x200
+
+struct mpfs_iomux0_pinctrl {
+ struct pinctrl_dev *pctrl;
+ struct device *dev;
+ struct regmap *regmap;
+ struct pinctrl_desc desc;
+};
+
+struct mpfs_iomux0_pin_group {
+ const char *name;
+ const unsigned int *pins;
+ u32 mask;
+ u32 setting;
+};
+
+struct mpfs_iomux0_function {
+ const char *name;
+ const char * const *groups;
+};
+
+static const struct pinctrl_pin_desc mpfs_iomux0_pins[] = {
+ PINCTRL_PIN(0, "spi0"),
+ PINCTRL_PIN(1, "spi1"),
+ PINCTRL_PIN(2, "i2c0"),
+ PINCTRL_PIN(3, "i2c1"),
+ PINCTRL_PIN(4, "can0"),
+ PINCTRL_PIN(5, "can1"),
+ PINCTRL_PIN(6, "qspi"),
+ PINCTRL_PIN(7, "uart0"),
+ PINCTRL_PIN(8, "uart1"),
+ PINCTRL_PIN(9, "uart2"),
+ PINCTRL_PIN(10, "uart3"),
+ PINCTRL_PIN(11, "uart4"),
+ PINCTRL_PIN(12, "mdio0"),
+ PINCTRL_PIN(13, "mdio1"),
+};
+
+static const unsigned int mpfs_iomux0_spi0_pins[] = { 0 };
+static const unsigned int mpfs_iomux0_spi1_pins[] = { 1 };
+static const unsigned int mpfs_iomux0_i2c0_pins[] = { 2 };
+static const unsigned int mpfs_iomux0_i2c1_pins[] = { 3 };
+static const unsigned int mpfs_iomux0_can0_pins[] = { 4 };
+static const unsigned int mpfs_iomux0_can1_pins[] = { 5 };
+static const unsigned int mpfs_iomux0_qspi_pins[] = { 6 };
+static const unsigned int mpfs_iomux0_uart0_pins[] = { 7 };
+static const unsigned int mpfs_iomux0_uart1_pins[] = { 8 };
+static const unsigned int mpfs_iomux0_uart2_pins[] = { 9 };
+static const unsigned int mpfs_iomux0_uart3_pins[] = { 10 };
+static const unsigned int mpfs_iomux0_uart4_pins[] = { 11 };
+static const unsigned int mpfs_iomux0_mdio0_pins[] = { 12 };
+static const unsigned int mpfs_iomux0_mdio1_pins[] = { 13 };
+
+#define MPFS_IOMUX0_GROUP(_name) { \
+ .name = #_name "_mssio", \
+ .pins = mpfs_iomux0_##_name##_pins, \
+ .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \
+ .setting = 0x0, \
+}, { \
+ .name = #_name "_fabric", \
+ .pins = mpfs_iomux0_##_name##_pins, \
+ .mask = BIT(mpfs_iomux0_##_name##_pins[0]), \
+ .setting = BIT(mpfs_iomux0_##_name##_pins[0]), \
+}
+
+static const struct mpfs_iomux0_pin_group mpfs_iomux0_pin_groups[] = {
+ MPFS_IOMUX0_GROUP(spi0),
+ MPFS_IOMUX0_GROUP(spi1),
+ MPFS_IOMUX0_GROUP(i2c0),
+ MPFS_IOMUX0_GROUP(i2c1),
+ MPFS_IOMUX0_GROUP(can0),
+ MPFS_IOMUX0_GROUP(can1),
+ MPFS_IOMUX0_GROUP(qspi),
+ MPFS_IOMUX0_GROUP(uart0),
+ MPFS_IOMUX0_GROUP(uart1),
+ MPFS_IOMUX0_GROUP(uart2),
+ MPFS_IOMUX0_GROUP(uart3),
+ MPFS_IOMUX0_GROUP(uart4),
+ MPFS_IOMUX0_GROUP(mdio0),
+ MPFS_IOMUX0_GROUP(mdio1),
+};
+
+static const char * const mpfs_iomux0_spi0_groups[] = { "spi0_mssio", "spi0_fabric" };
+static const char * const mpfs_iomux0_spi1_groups[] = { "spi1_mssio", "spi1_fabric" };
+static const char * const mpfs_iomux0_i2c0_groups[] = { "i2c0_mssio", "i2c0_fabric" };
+static const char * const mpfs_iomux0_i2c1_groups[] = { "i2c1_mssio", "i2c1_fabric" };
+static const char * const mpfs_iomux0_can0_groups[] = { "can0_mssio", "can0_fabric" };
+static const char * const mpfs_iomux0_can1_groups[] = { "can1_mssio", "can1_fabric" };
+static const char * const mpfs_iomux0_qspi_groups[] = { "qspi_mssio", "qspi_fabric" };
+static const char * const mpfs_iomux0_uart0_groups[] = { "uart0_mssio", "uart0_fabric" };
+static const char * const mpfs_iomux0_uart1_groups[] = { "uart1_mssio", "uart1_fabric" };
+static const char * const mpfs_iomux0_uart2_groups[] = { "uart2_mssio", "uart2_fabric" };
+static const char * const mpfs_iomux0_uart3_groups[] = { "uart3_mssio", "uart3_fabric" };
+static const char * const mpfs_iomux0_uart4_groups[] = { "uart4_mssio", "uart4_fabric" };
+static const char * const mpfs_iomux0_mdio0_groups[] = { "mdio0_mssio", "mdio0_fabric" };
+static const char * const mpfs_iomux0_mdio1_groups[] = { "mdio1_mssio", "mdio1_fabric" };
+
+#define MPFS_IOMUX0_FUNCTION(_name) { \
+ .name = #_name, \
+ .groups = mpfs_iomux0_##_name##_groups, \
+}
+
+static const struct mpfs_iomux0_function mpfs_iomux0_functions[] = {
+ MPFS_IOMUX0_FUNCTION(spi0),
+ MPFS_IOMUX0_FUNCTION(spi1),
+ MPFS_IOMUX0_FUNCTION(i2c0),
+ MPFS_IOMUX0_FUNCTION(i2c1),
+ MPFS_IOMUX0_FUNCTION(can0),
+ MPFS_IOMUX0_FUNCTION(can1),
+ MPFS_IOMUX0_FUNCTION(qspi),
+ MPFS_IOMUX0_FUNCTION(uart0),
+ MPFS_IOMUX0_FUNCTION(uart1),
+ MPFS_IOMUX0_FUNCTION(uart2),
+ MPFS_IOMUX0_FUNCTION(uart3),
+ MPFS_IOMUX0_FUNCTION(uart4),
+ MPFS_IOMUX0_FUNCTION(mdio0),
+ MPFS_IOMUX0_FUNCTION(mdio1),
+};
+
+static void mpfs_iomux0_pin_dbg_show(struct pinctrl_dev *pctrl_dev, struct seq_file *seq,
+ unsigned int pin)
+{
+ struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ u32 val;
+
+ seq_printf(seq, "reg: %x, pin: %u ", MPFS_IOMUX0_REG, pin);
+
+ regmap_read(pctrl->regmap, MPFS_IOMUX0_REG, &val);
+ val = (val & BIT(pin)) >> pin;
+
+ seq_printf(seq, "val: %x\n", val);
+}
+
+static int mpfs_iomux0_groups_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(mpfs_iomux0_pin_groups);
+}
+
+static const char *mpfs_iomux0_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
+{
+ return mpfs_iomux0_pin_groups[selector].name;
+}
+
+static int mpfs_iomux0_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
+ const unsigned int **pins, unsigned int *num_pins)
+{
+ *pins = mpfs_iomux0_pin_groups[selector].pins;
+ *num_pins = 1;
+
+ return 0;
+}
+
+static const struct pinctrl_ops mpfs_iomux0_pinctrl_ops = {
+ .get_groups_count = mpfs_iomux0_groups_count,
+ .get_group_name = mpfs_iomux0_group_name,
+ .get_group_pins = mpfs_iomux0_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
+ .dt_free_map = pinctrl_utils_free_map,
+ .pin_dbg_show = mpfs_iomux0_pin_dbg_show,
+};
+
+static int mpfs_iomux0_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, unsigned int fsel,
+ unsigned int gsel)
+{
+ struct mpfs_iomux0_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+ struct device *dev = pctrl->dev;
+ const struct mpfs_iomux0_pin_group *group;
+ const struct mpfs_iomux0_function *function;
+
+ group = &mpfs_iomux0_pin_groups[gsel];
+ function = &mpfs_iomux0_functions[fsel];
+
+ dev_dbg(dev, "Setting func %s mask %x setting %x\n",
+ function->name, group->mask, group->setting);
+ regmap_assign_bits(pctrl->regmap, MPFS_IOMUX0_REG, group->mask, group->setting);
+
+ return 0;
+}
+
+static int mpfs_iomux0_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(mpfs_iomux0_functions);
+}
+
+static const char *mpfs_iomux0_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int selector)
+{
+ return mpfs_iomux0_functions[selector].name;
+}
+
+static int mpfs_iomux0_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector,
+ const char * const **groups,
+ unsigned int * const num_groups)
+{
+ *groups = mpfs_iomux0_functions[selector].groups;
+ *num_groups = 2;
+
+ return 0;
+}
+
+static const struct pinmux_ops mpfs_iomux0_pinmux_ops = {
+ .get_functions_count = mpfs_iomux0_pinmux_get_funcs_count,
+ .get_function_name = mpfs_iomux0_pinmux_get_func_name,
+ .get_function_groups = mpfs_iomux0_pinmux_get_groups,
+ .set_mux = mpfs_iomux0_pinmux_set_mux,
+};
+
+static int mpfs_iomux0_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mpfs_iomux0_pinctrl *pctrl;
+
+ pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
+ if (!pctrl)
+ return -ENOMEM;
+
+ pctrl->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
+ if (IS_ERR(pctrl->regmap))
+ dev_err_probe(dev, PTR_ERR(pctrl->regmap), "Failed to find syscon regmap\n");
+
+ pctrl->desc.name = dev_name(dev);
+ pctrl->desc.pins = mpfs_iomux0_pins;
+ pctrl->desc.npins = ARRAY_SIZE(mpfs_iomux0_pins);
+ pctrl->desc.pctlops = &mpfs_iomux0_pinctrl_ops;
+ pctrl->desc.pmxops = &mpfs_iomux0_pinmux_ops;
+ pctrl->desc.owner = THIS_MODULE;
+
+ pctrl->dev = dev;
+
+ platform_set_drvdata(pdev, pctrl);
+
+ pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
+ if (IS_ERR(pctrl->pctrl))
+ return PTR_ERR(pctrl->pctrl);
+
+ return 0;
+}
+
+static const struct of_device_id mpfs_iomux0_of_match[] = {
+ { .compatible = "microchip,mpfs-pinctrl-iomux0" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, mpfs_iomux0_of_match);
+
+static struct platform_driver mpfs_iomux0_driver = {
+ .driver = {
+ .name = "mpfs-pinctrl-iomux0",
+ .of_match_table = mpfs_iomux0_of_match,
+ },
+ .probe = mpfs_iomux0_probe,
+};
+module_platform_driver(mpfs_iomux0_driver);
+
+MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+MODULE_DESCRIPTION("Polarfire SoC iomux0 pinctrl driver");
+MODULE_LICENSE("GPL");
--
2.51.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v3 5/5] MAINTAINERS: add Microchip RISC-V pinctrl drivers/bindings to entry
2025-10-22 10:09 [PATCH v3 0/5] Microchip mpfs/pic64gx pinctrl Conor Dooley
` (3 preceding siblings ...)
2025-10-22 10:09 ` [PATCH v3 4/5] pinctrl: add polarfire soc iomux0 pinmux driver Conor Dooley
@ 2025-10-22 10:09 ` Conor Dooley
4 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2025-10-22 10:09 UTC (permalink / raw)
To: linus.walleij
Cc: conor, Conor Dooley, Rob Herring, Krzysztof Kozlowski,
linux-kernel, linux-gpio, devicetree, Valentina.FernandezAlanis
From: Conor Dooley <conor.dooley@microchip.com>
Add the new gpio2 and iomux0 drivers and bindings to the existing entry
for Microchip RISC-V devices.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 46126ce2f968..5d4825073fcd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22089,6 +22089,8 @@ F: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
F: Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml
F: Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
F: Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml
+F: Documentation/devicetree/bindings/pinctrl/microchip,mpfs-pinctrl-iomux0.yaml
+F: Documentation/devicetree/bindings/pinctrl/microchip,pic64gx-pinctrl-gpio2.yaml
F: Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
F: Documentation/devicetree/bindings/riscv/microchip.yaml
F: Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -22102,6 +22104,8 @@ F: drivers/gpio/gpio-mpfs.c
F: drivers/i2c/busses/i2c-microchip-corei2c.c
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/pci/controller/plda/pcie-microchip-host.c
+F: drivers/pinctrl/pinctrl-mpfs-iomux0.c
+F: drivers/pinctrl/pinctrl-pic64gx-gpio2.c
F: drivers/pwm/pwm-microchip-core.c
F: drivers/reset/reset-mpfs.c
F: drivers/rtc/rtc-mpfs.c
--
2.51.0
^ permalink raw reply related [flat|nested] 7+ messages in thread