[PATCH v2 0/6] Add RTC support for the Renesas RZ/V2H SoC

[PATCH v2 0/6] Add RTC support for the Renesas RZ/V2H SoC

[Ovidiu Panait]

Hi,

This series adds RTC support for the Renesas RZ/V2H SoC.

The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
(r9a08g045), with the following differences:
- it lacks the time capture functionality
- the maximum supported periodic interrupt frequency is 128Hz instead
  of 256Hz
- it requires two reset lines instead of one

Best regards,
Ovidiu

v2:
- Updated bindings and RTC dts node with "reset-names" property.

Ovidiu Panait (6):
  clk: renesas: r9a09g057: Add clock and reset entries for RTC
  dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support
  rtc: renesas-rtca3: Use OF data for configuration
  rtc: renesas-rtca3: Add support for RZ/V2H SoC
  arm64: dts: renesas: r9a09g057: Add RTC node
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC

 .../bindings/rtc/renesas,rz-rtca3.yaml        | 45 ++++++++++++++++---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    | 15 +++++++
 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  4 ++
 drivers/clk/renesas/r9a09g057-cpg.c           |  4 ++
 drivers/rtc/rtc-renesas-rtca3.c               | 27 +++++++++--
 5 files changed, 87 insertions(+), 8 deletions(-)

-- 
2.51.0

[PATCH v2 1/6] clk: renesas: r9a09g057: Add clock and reset entries for RTC

[Ovidiu Panait]

Add module clock and reset entries for the RTC module on the Renesas RZ/V2H
(R9A09G057) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v2 changes: none

 drivers/clk/renesas/r9a09g057-cpg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index c9c117c6782c..100cd56c323e 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -241,6 +241,8 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
 						BUS_MSTOP(5, BIT(13))),
 	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,
 						BUS_MSTOP(5, BIT(13))),
+	DEF_MOD("rtc_0_clk_rtc",		CLK_PLLCM33_DIV16, 5, 3, 2, 19,
+						BUS_MSTOP(3, BIT(11) | BIT(12))),
 	DEF_MOD("rspi_0_pclk",			CLK_PLLCLN_DIV8, 5, 4, 2, 20,
 						BUS_MSTOP(11, BIT(0))),
 	DEF_MOD("rspi_0_pclk_sfr",		CLK_PLLCLN_DIV8, 5, 5, 2, 21,
@@ -411,6 +413,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
 	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
 	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */
 	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */
+	DEF_RST(7, 9, 3, 10),		/* RTC_0_RST_RTC */
+	DEF_RST(7, 10, 3, 11),		/* RTC_0_RST_RTC_V */
 	DEF_RST(7, 11, 3, 12),		/* RSPI_0_PRESETN */
 	DEF_RST(7, 12, 3, 13),		/* RSPI_0_TRESETN */
 	DEF_RST(7, 13, 3, 14),		/* RSPI_1_PRESETN */
-- 
2.51.0

[PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Ovidiu Panait]

The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
(r9a08g045), with the following differences:
- It lacks the time capture functionality
- The maximum supported periodic interrupt frequency is 128Hz instead
  of 256Hz
- It requires two reset lines instead of one

Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
the binding accordingly:
- Allow "resets" to contain one or two entries depending on the SoC.
- Add "reset-names" property, but make it required only for RZ/V2H.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v2 changes:
- Added "reset-names" property and made it required for RZ/V2H.

 .../bindings/rtc/renesas,rz-rtca3.yaml        | 45 ++++++++++++++++---
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
index e70eeb66aa64..2569cb494481 100644
--- a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
+++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
@@ -9,14 +9,12 @@ title: Renesas RTCA-3 Real Time Clock
 maintainers:
   - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
 
-allOf:
-  - $ref: rtc.yaml#
-
 properties:
   compatible:
     items:
       - enum:
           - renesas,r9a08g045-rtca3 # RZ/G3S
+          - renesas,r9a09g057-rtca3 # RZ/V2H
       - const: renesas,rz-rtca3
 
   reg:
@@ -48,8 +46,12 @@ properties:
     maxItems: 1
 
   resets:
-    items:
-      - description: VBATTB module reset
+    minItems: 1
+    maxItems: 2
+
+  reset-names:
+    minItems: 1
+    maxItems: 2
 
 required:
   - compatible
@@ -61,6 +63,39 @@ required:
   - power-domains
   - resets
 
+allOf:
+  - $ref: rtc.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g045-rtca3
+    then:
+      properties:
+        resets:
+          items:
+            - description: VBATTB module reset
+        reset-names:
+          const: vbattb
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g057-rtca3
+    then:
+      properties:
+        resets:
+          items:
+            - description: RTC reset
+            - description: Reset for the RTEST registers
+        reset-names:
+          items:
+            - const: rtc
+            - const: rtc_rtest
+      required:
+        - reset-names
+
 additionalProperties: false
 
 examples:
-- 
2.51.0

[PATCH v2 3/6] rtc: renesas-rtca3: Use OF data for configuration

[Ovidiu Panait]

Prepare for adding support for the Renesas RZ/V2H SoC RTC IP by making the
driver configuration selectable via OF match data.

For RZ/V2H RTC, the maximum periodic interrupt frequency is 128Hz instead
of 256Hz, so add this info to a SoC-specific struct and retrieve it
during probe.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v2 changes: none

 drivers/rtc/rtc-renesas-rtca3.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c
index ab816bdf0d77..90dda04fad33 100644
--- a/drivers/rtc/rtc-renesas-rtca3.c
+++ b/drivers/rtc/rtc-renesas-rtca3.c
@@ -101,6 +101,15 @@ enum rtca3_alrm_set_step {
 	RTCA3_ALRM_SSTEP_INIT = 3,
 };
 
+/**
+ * struct rtca3_of_data - OF data for RTCA3
+ *
+ * @max_periodic_irq_freq: maximum periodic interrupt frequency
+ */
+struct rtca3_of_data {
+	int max_periodic_irq_freq;
+};
+
 /**
  * struct rtca3_ppb_per_cycle - PPB per cycle
  * @ten_sec: PPB per cycle in 10 seconds adjutment mode
@@ -709,6 +718,7 @@ static void rtca3_action(void *data)
 
 static int rtca3_probe(struct platform_device *pdev)
 {
+	const struct rtca3_of_data *of_data;
 	struct device *dev = &pdev->dev;
 	struct rtca3_priv *priv;
 	struct clk *clk;
@@ -718,6 +728,8 @@ static int rtca3_probe(struct platform_device *pdev)
 	if (!priv)
 		return -ENOMEM;
 
+	of_data = of_device_get_match_data(dev);
+
 	priv->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(priv->base))
 		return PTR_ERR(priv->base);
@@ -772,7 +784,7 @@ static int rtca3_probe(struct platform_device *pdev)
 		return PTR_ERR(priv->rtc_dev);
 
 	priv->rtc_dev->ops = &rtca3_ops;
-	priv->rtc_dev->max_user_freq = 256;
+	priv->rtc_dev->max_user_freq = of_data->max_periodic_irq_freq;
 	priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
 	priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
 
@@ -875,8 +887,12 @@ static int rtca3_resume(struct device *dev)
 
 static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
 
+static const struct rtca3_of_data rtca3_of_data = {
+	.max_periodic_irq_freq = 256,
+};
+
 static const struct of_device_id rtca3_of_match[] = {
-	{ .compatible = "renesas,rz-rtca3", },
+	{ .compatible = "renesas,rz-rtca3", .data = &rtca3_of_data },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, rtca3_of_match);
-- 
2.51.0

[PATCH v2 4/6] rtc: renesas-rtca3: Add support for RZ/V2H SoC

[Ovidiu Panait]

Add a new compatible string for the Renesas RZ/V2H RTC along with the SoC
specific OF data, to account for the different maximum periodic interrupt
frequency (128Hz).

Also, switch from devm_reset_control_get_shared() to
devm_reset_control_array_get_shared() when retrieving resets.
The RZ/V2H SoC requires two resets for the RTC block instead of one,
so this will allow to handle multiple resets without additional changes.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v2 changes: none

 drivers/rtc/rtc-renesas-rtca3.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c
index 90dda04fad33..96f5d3734d93 100644
--- a/drivers/rtc/rtc-renesas-rtca3.c
+++ b/drivers/rtc/rtc-renesas-rtca3.c
@@ -738,7 +738,7 @@ static int rtca3_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	priv->rstc = devm_reset_control_get_shared(dev, NULL);
+	priv->rstc = devm_reset_control_array_get_shared(dev);
 	if (IS_ERR(priv->rstc))
 		return PTR_ERR(priv->rstc);
 
@@ -887,11 +887,16 @@ static int rtca3_resume(struct device *dev)
 
 static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
 
+static const struct rtca3_of_data rtca3_rzv2h_of_data = {
+	.max_periodic_irq_freq = 128,
+};
+
 static const struct rtca3_of_data rtca3_of_data = {
 	.max_periodic_irq_freq = 256,
 };
 
 static const struct of_device_id rtca3_of_match[] = {
+	{ .compatible = "renesas,r9a09g057-rtca3", .data = &rtca3_rzv2h_of_data },
 	{ .compatible = "renesas,rz-rtca3", .data = &rtca3_of_data },
 	{ /* sentinel */ }
 };
-- 
2.51.0

[PATCH v2 5/6] arm64: dts: renesas: r9a09g057: Add RTC node

[Ovidiu Panait]

Add RTC node to Renesas RZ/V2H ("R9A09G057") SoC DTSI.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v2 changes:
- Added "reset-names" to RTC dts node.

 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 40b15f1db930..724c4ce95c95 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -591,6 +591,21 @@ wdt3: watchdog@13000400 {
 			status = "disabled";
 		};
 
+		rtc: rtc@11c00800 {
+			compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
+			reg = <0 0x11c00800 0 0x400>;
+			interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "alarm", "period", "carry";
+			clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>;
+			clock-names = "bus", "counter";
+			power-domains = <&cpg>;
+			resets = <&cpg 0x79>, <&cpg 0x7a>;
+			reset-names = "rtc", "rtc_rtest";
+			status = "disabled";
+		};
+
 		scif: serial@11c01400 {
 			compatible = "renesas,scif-r9a09g057";
 			reg = <0 0x11c01400 0 0x400>;
-- 
2.51.0

[PATCH v2 6/6] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC

[Ovidiu Panait]

Enable RTC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
v2 changes: none

 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 3215ce53fe33..f20b63acca00 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -408,6 +408,10 @@ &qextal_clk {
 	clock-frequency = <24000000>;
 };
 
+&rtc {
+	status = "okay";
+};
+
 &rtxin_clk {
 	clock-frequency = <32768>;
 };
-- 
2.51.0

Re: [PATCH v2 1/6] clk: renesas: r9a09g057: Add clock and reset entries for RTC

[Geert Uytterhoeven]

On Tue, 21 Oct 2025 at 10:07, Ovidiu Panait
<ovidiu.panait.rb@renesas.com> wrote:
> Add module clock and reset entries for the RTC module on the Renesas RZ/V2H
> (R9A09G057) SoC.
>
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk for v6.19.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 759 bytes --]

On Tue, Oct 21, 2025 at 08:07:01AM +0000, Ovidiu Panait wrote:
> The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> (r9a08g045), with the following differences:
> - It lacks the time capture functionality
> - The maximum supported periodic interrupt frequency is 128Hz instead
>   of 256Hz
> - It requires two reset lines instead of one
> 
> Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
> the binding accordingly:
> - Allow "resets" to contain one or two entries depending on the SoC.
> - Add "reset-names" property, but make it required only for RZ/V2H.
> 
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v2 3/6] rtc: renesas-rtca3: Use OF data for configuration

[Alexandre Belloni]

Hello,

Since the RTC will never be used for PIE (we are using hrtimer), I guess
this patch is not necessary, instead, you could simply stop setting
max_user_freq.

On 21/10/2025 08:07:02+0000, Ovidiu Panait wrote:
> Prepare for adding support for the Renesas RZ/V2H SoC RTC IP by making the
> driver configuration selectable via OF match data.
> 
> For RZ/V2H RTC, the maximum periodic interrupt frequency is 128Hz instead
> of 256Hz, so add this info to a SoC-specific struct and retrieve it
> during probe.
> 
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> ---
> v2 changes: none
> 
>  drivers/rtc/rtc-renesas-rtca3.c | 20 ++++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c
> index ab816bdf0d77..90dda04fad33 100644
> --- a/drivers/rtc/rtc-renesas-rtca3.c
> +++ b/drivers/rtc/rtc-renesas-rtca3.c
> @@ -101,6 +101,15 @@ enum rtca3_alrm_set_step {
>  	RTCA3_ALRM_SSTEP_INIT = 3,
>  };
>  
> +/**
> + * struct rtca3_of_data - OF data for RTCA3
> + *
> + * @max_periodic_irq_freq: maximum periodic interrupt frequency
> + */
> +struct rtca3_of_data {
> +	int max_periodic_irq_freq;
> +};
> +
>  /**
>   * struct rtca3_ppb_per_cycle - PPB per cycle
>   * @ten_sec: PPB per cycle in 10 seconds adjutment mode
> @@ -709,6 +718,7 @@ static void rtca3_action(void *data)
>  
>  static int rtca3_probe(struct platform_device *pdev)
>  {
> +	const struct rtca3_of_data *of_data;
>  	struct device *dev = &pdev->dev;
>  	struct rtca3_priv *priv;
>  	struct clk *clk;
> @@ -718,6 +728,8 @@ static int rtca3_probe(struct platform_device *pdev)
>  	if (!priv)
>  		return -ENOMEM;
>  
> +	of_data = of_device_get_match_data(dev);
> +
>  	priv->base = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(priv->base))
>  		return PTR_ERR(priv->base);
> @@ -772,7 +784,7 @@ static int rtca3_probe(struct platform_device *pdev)
>  		return PTR_ERR(priv->rtc_dev);
>  
>  	priv->rtc_dev->ops = &rtca3_ops;
> -	priv->rtc_dev->max_user_freq = 256;
> +	priv->rtc_dev->max_user_freq = of_data->max_periodic_irq_freq;
>  	priv->rtc_dev->range_min = RTC_TIMESTAMP_BEGIN_2000;
>  	priv->rtc_dev->range_max = RTC_TIMESTAMP_END_2099;
>  
> @@ -875,8 +887,12 @@ static int rtca3_resume(struct device *dev)
>  
>  static DEFINE_SIMPLE_DEV_PM_OPS(rtca3_pm_ops, rtca3_suspend, rtca3_resume);
>  
> +static const struct rtca3_of_data rtca3_of_data = {
> +	.max_periodic_irq_freq = 256,
> +};
> +
>  static const struct of_device_id rtca3_of_match[] = {
> -	{ .compatible = "renesas,rz-rtca3", },
> +	{ .compatible = "renesas,rz-rtca3", .data = &rtca3_of_data },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, rtca3_of_match);
> -- 
> 2.51.0
> 

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Geert Uytterhoeven]

Hi Ovidiu,

Sorry, I still had outstanding review comments I hadn't sent yet, as
I hadn't finished my review yet.

On Tue, 21 Oct 2025 at 10:07, Ovidiu Panait
<ovidiu.panait.rb@renesas.com> wrote:
> The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> (r9a08g045), with the following differences:
> - It lacks the time capture functionality
> - The maximum supported periodic interrupt frequency is 128Hz instead
>   of 256Hz
> - It requires two reset lines instead of one
>
> Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
> the binding accordingly:
> - Allow "resets" to contain one or two entries depending on the SoC.
> - Add "reset-names" property, but make it required only for RZ/V2H.
>
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> ---
> v2 changes:
> - Added "reset-names" property and made it required for RZ/V2H.

Thanks for the update!

> --- a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
> +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml

> @@ -61,6 +63,39 @@ required:
>    - power-domains
>    - resets
>
> +allOf:
> +  - $ref: rtc.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a08g045-rtca3
> +    then:
> +      properties:
> +        resets:
> +          items:
> +            - description: VBATTB module reset
> +        reset-names:
> +          const: vbattb

Please add this property to the example at the bottom, too.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Ovidiu Panait]

Hi Geert,

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: Thursday, November 6, 2025 10:47 AM
> To: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> Cc: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>;
> alexandre.belloni@bootlin.com; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; magnus.damm <magnus.damm@gmail.com>;
> mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; linux-
> rtc@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> clk@vger.kernel.org
> Subject: Re: [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H
> support
> 
> Hi Ovidiu,
> 
> Sorry, I still had outstanding review comments I hadn't sent yet, as
> I hadn't finished my review yet.
> 
> On Tue, 21 Oct 2025 at 10:07, Ovidiu Panait
> <ovidiu.panait.rb@renesas.com> wrote:
> > The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> > (r9a08g045), with the following differences:
> > - It lacks the time capture functionality
> > - The maximum supported periodic interrupt frequency is 128Hz instead
> >   of 256Hz
> > - It requires two reset lines instead of one
> >
> > Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and
> update
> > the binding accordingly:
> > - Allow "resets" to contain one or two entries depending on the SoC.
> > - Add "reset-names" property, but make it required only for RZ/V2H.
> >
> > Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > ---
> > v2 changes:
> > - Added "reset-names" property and made it required for RZ/V2H.
> 
> Thanks for the update!
> 
> > --- a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
> > +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
> 
> > @@ -61,6 +63,39 @@ required:
> >    - power-domains
> >    - resets
> >
> > +allOf:
> > +  - $ref: rtc.yaml#
> > +
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: renesas,r9a08g045-rtca3
> > +    then:
> > +      properties:
> > +        resets:
> > +          items:
> > +            - description: VBATTB module reset
> > +        reset-names:
> > +          const: vbattb
> 
> Please add this property to the example at the bottom, too.
> 

Thanks for your review!

Please see the latest v3 series:
https://lore.kernel.org/all/20251103121848.6539-1-ovidiu.panait.rb@renesas.com/

The first two patches were applied by Alexandre in the meantime.

Alexandre, would it be possible to drop the patches from your queue and I
will send v4 to address the latest feedback from Geert and Conor? 

Thanks!
Ovidiu

> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
> 
> In personal conversations with technical people, I call myself a hacker.
> But
> when I'm talking to journalists I just say "programmer" or something like
> that.
>                                 -- Linus Torvalds

Re: [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Alexandre Belloni]

On 06/11/2025 09:13:53+0000, Ovidiu Panait wrote:
> Hi Geert,
> 
> > -----Original Message-----
> > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > Sent: Thursday, November 6, 2025 10:47 AM
> > To: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > Cc: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>;
> > alexandre.belloni@bootlin.com; robh@kernel.org; krzk+dt@kernel.org;
> > conor+dt@kernel.org; magnus.damm <magnus.damm@gmail.com>;
> > mturquette@baylibre.com; sboyd@kernel.org; p.zabel@pengutronix.de; linux-
> > rtc@vger.kernel.org; linux-renesas-soc@vger.kernel.org;
> > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-
> > clk@vger.kernel.org
> > Subject: Re: [PATCH v2 2/6] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H
> > support
> > 
> > Hi Ovidiu,
> > 
> > Sorry, I still had outstanding review comments I hadn't sent yet, as
> > I hadn't finished my review yet.
> > 
> > On Tue, 21 Oct 2025 at 10:07, Ovidiu Panait
> > <ovidiu.panait.rb@renesas.com> wrote:
> > > The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> > > (r9a08g045), with the following differences:
> > > - It lacks the time capture functionality
> > > - The maximum supported periodic interrupt frequency is 128Hz instead
> > >   of 256Hz
> > > - It requires two reset lines instead of one
> > >
> > > Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and
> > update
> > > the binding accordingly:
> > > - Allow "resets" to contain one or two entries depending on the SoC.
> > > - Add "reset-names" property, but make it required only for RZ/V2H.
> > >
> > > Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > > ---
> > > v2 changes:
> > > - Added "reset-names" property and made it required for RZ/V2H.
> > 
> > Thanks for the update!
> > 
> > > --- a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
> > > +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
> > 
> > > @@ -61,6 +63,39 @@ required:
> > >    - power-domains
> > >    - resets
> > >
> > > +allOf:
> > > +  - $ref: rtc.yaml#
> > > +
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            const: renesas,r9a08g045-rtca3
> > > +    then:
> > > +      properties:
> > > +        resets:
> > > +          items:
> > > +            - description: VBATTB module reset
> > > +        reset-names:
> > > +          const: vbattb
> > 
> > Please add this property to the example at the bottom, too.
> > 
> 
> Thanks for your review!
> 
> Please see the latest v3 series:
> https://lore.kernel.org/all/20251103121848.6539-1-ovidiu.panait.rb@renesas.com/
> 
> The first two patches were applied by Alexandre in the meantime.
> 
> Alexandre, would it be possible to drop the patches from your queue and I
> will send v4 to address the latest feedback from Geert and Conor? 
> 

Sure, I'll drop them later today.

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com