[PATCH v1 0/7] clk: mediatek: Add support for SPMI Clock Controllers

[PATCH v1 0/7] clk: mediatek: Add support for SPMI Clock Controllers

[AngeloGioacchino Del Regno]

Some new PMICs, Clock IC and combos are complex SPMI 2.0 devices that
contain multiple IPs, including clock controllers.

This series expands the MediaTek clock helpers to allow registering
clock controllers over SPMI, and adds a clock driver for the MT6685
SCK_TOP clock controller.

For now, only gate clocks are supported to reduce the complexity of
this change.

NOTE: This series depends on series [1] "SPMI: Implement sub-devices
and migrate drivers"

[1]: https://lore.kernel.org/all/20251021083219.17382-1-angelogioacchino.delregno@collabora.com

AngeloGioacchino Del Regno (7):
  clk: mediatek: Split out registration from mtk_clk_register_gates()
  clk: mediatek: clk-gate: Simplify and optimize registration iter
  clk: mediatek: clk-mtk: Split and rename __mtk_clk_simple_probe()
  clk: mediatek: Add and wire up mtk_spmi_clk_register_gates()
  clk: mediatek: Add support to register SPMI Clock Controllers
  dt-bindings: clock: Describe MT6685 PM/Clock IC Clock Controller
  clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller

 .../bindings/clock/mediatek,mt6685-clock.yaml | 37 ++++++++++
 drivers/clk/mediatek/Kconfig                  | 15 ++++
 drivers/clk/mediatek/Makefile                 |  7 +-
 drivers/clk/mediatek/clk-gate.c               | 70 ++++++++++++-------
 drivers/clk/mediatek/clk-gate.h               |  6 ++
 drivers/clk/mediatek/clk-mt6685.c             | 70 +++++++++++++++++++
 drivers/clk/mediatek/clk-mtk-spmi.c           | 62 ++++++++++++++++
 drivers/clk/mediatek/clk-mtk-spmi.h           | 31 ++++++++
 drivers/clk/mediatek/clk-mtk.c                | 66 ++++++++++++-----
 drivers/clk/mediatek/clk-mtk.h                |  5 ++
 .../dt-bindings/clock/mediatek,mt6685-clock.h | 17 +++++
 11 files changed, 339 insertions(+), 47 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
 create mode 100644 drivers/clk/mediatek/clk-mt6685.c
 create mode 100644 drivers/clk/mediatek/clk-mtk-spmi.c
 create mode 100644 drivers/clk/mediatek/clk-mtk-spmi.h
 create mode 100644 include/dt-bindings/clock/mediatek,mt6685-clock.h

-- 
2.51.1

[PATCH v1 1/7] clk: mediatek: Split out registration from mtk_clk_register_gates()

[AngeloGioacchino Del Regno]

In preparation for adding support for clock controllers over SPMI
bus, split out the actual registration iterator out of the function
mtk_clk_register_gates() to a new mtk_clk_register_all_gates()
private function, taking a handle to regmap and hwv_regmap as
parameters.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-gate.c | 43 ++++++++++++++++++++-------------
 1 file changed, 26 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index f6b1429ff757..fd8cec95cd8d 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -252,30 +252,17 @@ static void mtk_clk_unregister_gate(struct clk_hw *hw)
 	kfree(cg);
 }
 
-int mtk_clk_register_gates(struct device *dev, struct device_node *node,
-			   const struct mtk_gate *clks, int num,
-			   struct clk_hw_onecell_data *clk_data)
+static int mtk_clk_register_all_gates(struct device *dev, struct device_node *node,
+				      struct regmap *regmap, struct regmap *hwv_regmap,
+				      const struct mtk_gate *clks, int num,
+				      struct clk_hw_onecell_data *clk_data)
 {
 	int i;
 	struct clk_hw *hw;
-	struct regmap *regmap;
-	struct regmap *regmap_hwv;
 
 	if (!clk_data)
 		return -ENOMEM;
 
-	regmap = device_node_to_regmap(node);
-	if (IS_ERR(regmap)) {
-		pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
-		return PTR_ERR(regmap);
-	}
-
-	regmap_hwv = mtk_clk_get_hwv_regmap(node);
-	if (IS_ERR(regmap_hwv))
-		return dev_err_probe(
-			dev, PTR_ERR(regmap_hwv),
-			"Cannot find hardware voter regmap for %pOF\n", node);
-
 	for (i = 0; i < num; i++) {
 		const struct mtk_gate *gate = &clks[i];
 
@@ -311,6 +298,28 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
 
 	return PTR_ERR(hw);
 }
+
+int mtk_clk_register_gates(struct device *dev, struct device_node *node,
+			   const struct mtk_gate *clks, int num,
+			   struct clk_hw_onecell_data *clk_data)
+{
+	struct regmap *regmap, *regmap_hwv;
+
+	regmap = device_node_to_regmap(node);
+	if (IS_ERR(regmap)) {
+		pr_err("Cannot find regmap for %pOF: %pe\n", node, regmap);
+		return PTR_ERR(regmap);
+	}
+
+	regmap_hwv = mtk_clk_get_hwv_regmap(node);
+	if (IS_ERR(regmap_hwv))
+		return dev_err_probe(
+			dev, PTR_ERR(regmap_hwv),
+			"Cannot find hardware voter regmap for %pOF\n", node);
+
+	return mtk_clk_register_all_gates(dev, node, regmap, regmap_hwv,
+					  clks, num, clk_data);
+}
 EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
 
 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
-- 
2.51.1

[PATCH v1 2/7] clk: mediatek: clk-gate: Simplify and optimize registration iter

[AngeloGioacchino Del Regno]

Simplify and optimize mtk_clk_register_all_gates() by removing and
replacing the function-local clk_hw pointer assignment and check
and as last step the consequent assignment to the array containing
handles to the registered clocks with... just the last step.

This removes a bunch of useless assignments, and in case any error
happens, the tear down iterator will still do its job without any
change required, effectively bringing no functional change, and a
a small optimization.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-gate.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index fd8cec95cd8d..8d1cc6a98a5f 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -257,8 +257,7 @@ static int mtk_clk_register_all_gates(struct device *dev, struct device_node *no
 				      const struct mtk_gate *clks, int num,
 				      struct clk_hw_onecell_data *clk_data)
 {
-	int i;
-	struct clk_hw *hw;
+	int i, ret;
 
 	if (!clk_data)
 		return -ENOMEM;
@@ -272,21 +271,19 @@ static int mtk_clk_register_all_gates(struct device *dev, struct device_node *no
 			continue;
 		}
 
-		hw = mtk_clk_register_gate(dev, gate, regmap, regmap_hwv);
-
-		if (IS_ERR(hw)) {
+		clk_data->hws[gate->id] = mtk_clk_register_gate(dev, gate, regmap, hwv_regmap);
+		if (IS_ERR(clk_data->hws[gate->id])) {
 			pr_err("Failed to register clk %s: %pe\n", gate->name,
-			       hw);
+			       clk_data->hws[gate->id]);
+			ret = PTR_ERR(clk_data->hws[gate->id]);
 			goto err;
 		}
-
-		clk_data->hws[gate->id] = hw;
 	}
 
 	return 0;
 
 err:
-	while (--i >= 0) {
+	while (i-- >= 0) {
 		const struct mtk_gate *gate = &clks[i];
 
 		if (IS_ERR_OR_NULL(clk_data->hws[gate->id]))
@@ -296,7 +293,7 @@ static int mtk_clk_register_all_gates(struct device *dev, struct device_node *no
 		clk_data->hws[gate->id] = ERR_PTR(-ENOENT);
 	}
 
-	return PTR_ERR(hw);
+	return ret;
 }
 
 int mtk_clk_register_gates(struct device *dev, struct device_node *node,
-- 
2.51.1

[PATCH v1 3/7] clk: mediatek: clk-mtk: Split and rename __mtk_clk_simple_probe()

[AngeloGioacchino Del Regno]

In preparation for adding support to register clock controllers
that are not reachable over MMIO but rather over a different bus,
especially SPMI (for PMIC clocks!), split out the current private
__mtk_clk_simple_probe() function in two, make it accept a handle
to regmap in and call it mtk_clk_simple_probe_internal().

The new function is not static, but its symbol is *not* exported:
this is done on purpose, because this is supposed to be usable
only by clock registration helpers inside of clk/mediatek, and
only ones built inside of the same module as clk-mtk, as will be
done in a later change.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-mtk.c | 58 ++++++++++++++++++++++++----------
 drivers/clk/mediatek/clk-mtk.h |  5 +++
 2 files changed, 46 insertions(+), 17 deletions(-)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 19cd27941747..93c7e28ffb5f 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -2,6 +2,8 @@
 /*
  * Copyright (c) 2014 MediaTek Inc.
  * Author: James Liao <jamesjj.liao@mediatek.com>
+ * Copyright (c) 2025 Collabora Ltd
+ *		      AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  */
 
 #include <linux/bitops.h>
@@ -14,6 +16,7 @@
 #include <linux/of_address.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 #include <linux/slab.h>
 
 #include "clk-mtk.h"
@@ -464,26 +467,15 @@ void mtk_clk_unregister_dividers(const struct mtk_clk_divider *mcds, int num,
 }
 EXPORT_SYMBOL_GPL(mtk_clk_unregister_dividers);
 
-static int __mtk_clk_simple_probe(struct platform_device *pdev,
-				  struct device_node *node)
+int mtk_clk_simple_probe_internal(struct platform_device *pdev,
+				  struct device_node *node,
+				  const struct mtk_clk_desc *mcd,
+				  struct regmap *regmap)
 {
-	const struct platform_device_id *id;
-	const struct mtk_clk_desc *mcd;
 	struct clk_hw_onecell_data *clk_data;
 	void __iomem *base = NULL;
 	int num_clks, r;
 
-	mcd = device_get_match_data(&pdev->dev);
-	if (!mcd) {
-		/* Clock driver wasn't registered from devicetree */
-		id = platform_get_device_id(pdev);
-		if (id)
-			mcd = (const struct mtk_clk_desc *)id->driver_data;
-
-		if (!mcd)
-			return -EINVAL;
-	}
-
 	/* Composite and divider clocks needs us to pass iomem pointer */
 	if (mcd->composite_clks || mcd->divider_clks) {
 		if (!mcd->shared_io)
@@ -653,20 +645,52 @@ static void __mtk_clk_simple_remove(struct platform_device *pdev,
 	mtk_free_clk_data(clk_data);
 }
 
+static int mtk_clk_get_desc(struct platform_device *pdev, const struct mtk_clk_desc **d)
+{
+	const struct platform_device_id *id;
+	const struct mtk_clk_desc *mcd;
+
+	mcd = device_get_match_data(&pdev->dev);
+	if (!mcd) {
+		/* Clock driver wasn't registered from devicetree */
+		id = platform_get_device_id(pdev);
+		if (id)
+			mcd = (const struct mtk_clk_desc *)id->driver_data;
+
+		if (!mcd)
+			return -EINVAL;
+	}
+	*d = mcd;
+
+	return 0;
+}
+
 int mtk_clk_pdev_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *node = dev->parent->of_node;
+	const struct mtk_clk_desc *mcd;
+	int ret;
 
-	return __mtk_clk_simple_probe(pdev, node);
+	ret = mtk_clk_get_desc(pdev, &mcd);
+	if (ret)
+		return ret;
+
+	return mtk_clk_simple_probe_internal(pdev, node, mcd, NULL);
 }
 EXPORT_SYMBOL_GPL(mtk_clk_pdev_probe);
 
 int mtk_clk_simple_probe(struct platform_device *pdev)
 {
 	struct device_node *node = pdev->dev.of_node;
+	const struct mtk_clk_desc *mcd;
+	int ret;
+
+	ret = mtk_clk_get_desc(pdev, &mcd);
+	if (ret)
+		return ret;
 
-	return __mtk_clk_simple_probe(pdev, node);
+	return mtk_clk_simple_probe_internal(pdev, node, mcd, NULL);
 }
 EXPORT_SYMBOL_GPL(mtk_clk_simple_probe);
 
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 5417b9264e6d..945fd3ee79ca 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -262,6 +262,11 @@ struct mtk_clk_desc {
 	bool need_runtime_pm;
 };
 
+int mtk_clk_simple_probe_internal(struct platform_device *pdev,
+				  struct device_node *node,
+				  const struct mtk_clk_desc *mcd,
+				  struct regmap *regmap);
+
 int mtk_clk_pdev_probe(struct platform_device *pdev);
 void mtk_clk_pdev_remove(struct platform_device *pdev);
 int mtk_clk_simple_probe(struct platform_device *pdev);
-- 
2.51.1

[PATCH v1 4/7] clk: mediatek: Add and wire up mtk_spmi_clk_register_gates()

[AngeloGioacchino Del Regno]

In preparation for adding means to register SPMI clock controllers
add a new mtk_spmi_clk_register_gates() function and wire it up to
mtk_clk_simple_probe_internal().

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/clk-gate.c | 10 ++++++++++
 drivers/clk/mediatek/clk-gate.h |  6 ++++++
 drivers/clk/mediatek/clk-mtk.c  |  8 ++++++--
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c
index 8d1cc6a98a5f..1bc09c5ca897 100644
--- a/drivers/clk/mediatek/clk-gate.c
+++ b/drivers/clk/mediatek/clk-gate.c
@@ -319,6 +319,16 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
 }
 EXPORT_SYMBOL_GPL(mtk_clk_register_gates);
 
+int mtk_spmi_clk_register_gates(struct device *dev, struct device_node *node,
+				const struct mtk_gate *clks, int num,
+				struct clk_hw_onecell_data *clk_data,
+				struct regmap *regmap)
+{
+	return mtk_clk_register_all_gates(dev, node, regmap, NULL,
+					  clks, num, clk_data);
+}
+EXPORT_SYMBOL_GPL(mtk_spmi_clk_register_gates);
+
 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
 			      struct clk_hw_onecell_data *clk_data)
 {
diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h
index 4f05b9855dae..924219344021 100644
--- a/drivers/clk/mediatek/clk-gate.h
+++ b/drivers/clk/mediatek/clk-gate.h
@@ -14,6 +14,7 @@ struct clk_hw_onecell_data;
 struct clk_ops;
 struct device;
 struct device_node;
+struct regmap;
 
 extern const struct clk_ops mtk_clk_gate_ops_setclr;
 extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
@@ -57,6 +58,11 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
 			   const struct mtk_gate *clks, int num,
 			   struct clk_hw_onecell_data *clk_data);
 
+int mtk_spmi_clk_register_gates(struct device *dev, struct device_node *node,
+				const struct mtk_gate *clks, int num,
+				struct clk_hw_onecell_data *clk_data,
+				struct regmap *regmap);
+
 void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num,
 			      struct clk_hw_onecell_data *clk_data);
 
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 93c7e28ffb5f..b5b329f6fde7 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -552,8 +552,12 @@ int mtk_clk_simple_probe_internal(struct platform_device *pdev,
 	}
 
 	if (mcd->clks) {
-		r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
-					   mcd->num_clks, clk_data);
+		if (regmap)
+			r = mtk_spmi_clk_register_gates(&pdev->dev, node, mcd->clks,
+							mcd->num_clks, clk_data, regmap);
+		else
+			r = mtk_clk_register_gates(&pdev->dev, node, mcd->clks,
+						   mcd->num_clks, clk_data);
 		if (r)
 			goto unregister_dividers;
 	}
-- 
2.51.1

[PATCH v1 5/7] clk: mediatek: Add support to register SPMI Clock Controllers

[AngeloGioacchino Del Regno]

Add a new mtk_spmi_clk_simple_probe() helper in a new file to add
support for registering SPMI Clock Controllers, and change the
Makefile to conditionally embed the new clk-mtk-spmi inside of
a clk-mediatek object.

This was all done like that because clk-mtk-spmi wants to import
the "SPMI" namespace as it uses functions to register a new SPMI
subdevice (the clock controller), but doing so is not necessary
if SPMI Clock Controllers support is not desired.

This means that COMMON_CLK_MEDIATEK_SPMI may be either y or n,
as this conditionally includes or excludes it from the object
which will require said namespace only if support is desired.

As a last note, when COMMON_CLK_MEDIATEK_SPMI=n, the generated
object will be "the same as before" (bar the name), because the
object generated by COMMON_CLK_MEDIATEK was already containing
all of the ones that are included right now (again, if built
without support for SPMI Clock Controllers).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/Kconfig        |  8 ++++
 drivers/clk/mediatek/Makefile       |  5 ++-
 drivers/clk/mediatek/clk-mtk-spmi.c | 62 +++++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mtk-spmi.h | 31 +++++++++++++++
 4 files changed, 105 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/mediatek/clk-mtk-spmi.c
 create mode 100644 drivers/clk/mediatek/clk-mtk-spmi.h

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 0d52771d06b3..3452dcbc9e45 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -18,6 +18,14 @@ config COMMON_CLK_MEDIATEK_FHCTL
 	  This driver supports MediaTek frequency hopping and
 	  spread spectrum clocking features.
 
+config COMMON_CLK_MEDIATEK_SPMI
+	bool
+	depends on COMMON_CLK_MEDIATEK
+	select REGMAP_SPMI
+	select SPMI
+	help
+	  MediaTek PMICs clock support.
+
 config COMMON_CLK_MT2701
 	bool "Clock driver for MediaTek MT2701"
 	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 4daba371342f..1471d8affa44 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -1,5 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
+clk-mediatek-y := clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o reset.o clk-mux.o
+clk-mediatek-$(CONFIG_COMMON_CLK_MEDIATEK_SPMI) += clk-mtk-spmi.o
+obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mediatek.o
+
 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
 
 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
diff --git a/drivers/clk/mediatek/clk-mtk-spmi.c b/drivers/clk/mediatek/clk-mtk-spmi.c
new file mode 100644
index 000000000000..0206e1f8ec27
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mtk-spmi.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Collabora Ltd
+ *		      AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <linux/spmi.h>
+
+#include "clk-mtk.h"
+#include "clk-mtk-spmi.h"
+
+int mtk_spmi_clk_simple_probe(struct platform_device *pdev)
+{
+	struct regmap_config mtk_spmi_clk_regmap_config = {
+		.reg_bits = 16,
+		.val_bits = 8,
+		.fast_io = true
+	};
+	struct device_node *node = pdev->dev.of_node;
+	const struct mtk_spmi_clk_desc *mscd;
+	struct spmi_subdevice *sub_sdev;
+	struct spmi_device *sparent;
+	struct regmap *regmap;
+	int ret;
+
+	ret = of_property_read_u32(node, "reg", &mtk_spmi_clk_regmap_config.reg_base);
+	if (ret)
+		return ret;
+
+	/* If the max_register was not declared the pdata is not valid */
+	mscd = device_get_match_data(&pdev->dev);
+	if (mscd->max_register == 0)
+		return -EINVAL;
+
+	mtk_spmi_clk_regmap_config.max_register = mscd->max_register;
+
+	sparent = to_spmi_device(pdev->dev.parent);
+	sub_sdev = devm_spmi_subdevice_alloc_and_add(&pdev->dev, sparent);
+	if (IS_ERR(sub_sdev))
+		return PTR_ERR(sub_sdev);
+
+	regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev, &mtk_spmi_clk_regmap_config);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	return mtk_clk_simple_probe_internal(pdev, node, mscd->desc, regmap);
+}
+EXPORT_SYMBOL_GPL(mtk_spmi_clk_simple_probe);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("SPMI");
diff --git a/drivers/clk/mediatek/clk-mtk-spmi.h b/drivers/clk/mediatek/clk-mtk-spmi.h
new file mode 100644
index 000000000000..39499d1db10a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mtk-spmi.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2025 Collabora Ltd
+ * 		      AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef __DRV_CLK_MTK_SPMI_H
+#define __DRV_CLK_MTK_SPMI_H
+
+struct mtk_clk_desc;
+struct platform_device;
+
+struct mtk_spmi_clk_desc {
+	const struct mtk_clk_desc *desc;
+	u16 max_register;
+};
+
+#ifdef CONFIG_COMMON_CLK_MEDIATEK_SPMI
+
+int mtk_spmi_clk_simple_probe(struct platform_device *pdev);
+
+#else
+
+inline int mtk_spmi_clk_simple_probe(struct platform_device *pdev)
+{
+	return -ENXIO;
+}
+
+#endif /* CONFIG_COMMON_CLK_MEDIATEK_SPMI */
+
+#endif /* __DRV_CLK_MTK_SPMI_H */
-- 
2.51.1

[PATCH v1 6/7] dt-bindings: clock: Describe MT6685 PM/Clock IC Clock Controller

[AngeloGioacchino Del Regno]

Add bindings to describe the SCK_TOP clock controller embedded
in the MT6685 IC, reachable over the SPMI bus.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---

NOTE: This does not contain any example because the MT6685 RTC
      will be added to the mfd binding for MediaTek SPMI PMICs
      and examples will be there.

** For reviewing purposes, this is how the example will look like: **

  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    #include <dt-bindings/spmi/spmi.h>

    spmi {
      #address-cells = <2>;
      #size-cells = <0>;

      pmic@9 {
        compatible = "mediatek,mt6363";
        reg = <0x9 SPMI_USID>;
        interrupts = <9 1 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #address-cells = <1>;
        #interrupt-cells = <3>;
        #size-cells = <0>;

        clock-controller@514 {
          compatible = "mediatek,mt6685-sck-top";
          reg = <0x514>;
          #clock-cells = <1>;
        };

        rtc@580 {
          compatible = "mediatek,mt6685-rtc";
          reg = <0x580>;
          interrupts = <9 0 IRQ_TYPE_LEVEL_HIGH>;
        };
      };
    };

 .../bindings/clock/mediatek,mt6685-clock.yaml | 37 +++++++++++++++++++
 .../dt-bindings/clock/mediatek,mt6685-clock.h | 17 +++++++++
 2 files changed, 54 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
 create mode 100644 include/dt-bindings/clock/mediatek,mt6685-clock.h

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
new file mode 100644
index 000000000000..5407ebf2f3b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt6685-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Clock Controller for MT6685 SPMI PM/Clock IC
+
+maintainers:
+  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+
+description: |
+  The clock architecture in MediaTek PMICs+Clock ICs is structured like below:
+  Crystal(XO) or Internal ClockGen -->
+          dividers -->
+                      muxes
+                           -->
+                              clock gate
+
+  The device nodes provide clock gate control in different IP blocks.
+
+properties:
+  compatible:
+    const: mediatek,mt6685-sck-top
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
diff --git a/include/dt-bindings/clock/mediatek,mt6685-clock.h b/include/dt-bindings/clock/mediatek,mt6685-clock.h
new file mode 100644
index 000000000000..acc5e2e15ce1
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt6685-clock.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT6685_H
+#define _DT_BINDINGS_CLK_MT6685_H
+
+/* SCK_TOP_CKPDN */
+#define CLK_RTC_SEC_MCLK		0
+#define CLK_RTC_EOSC32			1
+#define CLK_RTC_SEC_32K			2
+#define CLK_RTC_MCLK			3
+#define CLK_RTC_32K			4
+
+#endif /* _DT_BINDINGS_CLK_MT6685_H */
-- 
2.51.1

[PATCH v1 7/7] clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller

[AngeloGioacchino Del Regno]

Add support for the SCK_TOP Clock Controller IP found in the
MediaTek MT6685 PM/Clock IC as a SPMI Sub-Device.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/clk/mediatek/Kconfig      |  7 ++++
 drivers/clk/mediatek/Makefile     |  2 +
 drivers/clk/mediatek/clk-mt6685.c | 70 +++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt6685.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 3452dcbc9e45..eb1764418b1e 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -132,6 +132,13 @@ config COMMON_CLK_MT2712_VENCSYS
 	help
 	  This driver supports MediaTek MT2712 vencsys clocks.
 
+config COMMON_CLK_MT6685
+	tristate "Clock driver for MediaTek MT6685 Clock IC"
+	depends on ARCH_MEDIATEK
+	select COMMON_CLK_MEDIATEK_SPMI
+	help
+	  This driver supports clocks provided by the MT6685 Clock IC.
+
 config COMMON_CLK_MT6735
 	tristate "Main clock drivers for MediaTek MT6735"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1471d8affa44..d68837f1aa06 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -5,6 +5,8 @@ obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mediatek.o
 
 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
 
+obj-$(CONFIG_COMMON_CLK_MT6685) += clk-mt6685.o
+
 obj-$(CONFIG_COMMON_CLK_MT6735) += clk-mt6735-apmixedsys.o clk-mt6735-infracfg.o clk-mt6735-pericfg.o clk-mt6735-topckgen.o
 obj-$(CONFIG_COMMON_CLK_MT6735_IMGSYS) += clk-mt6735-imgsys.o
 obj-$(CONFIG_COMMON_CLK_MT6735_MFGCFG) += clk-mt6735-mfgcfg.o
diff --git a/drivers/clk/mediatek/clk-mt6685.c b/drivers/clk/mediatek/clk-mt6685.c
new file mode 100644
index 000000000000..1d524aef61a5
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt6685.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+#include <dt-bindings/clock/mediatek,mt6685-clock.h>
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+#include "clk-mtk-spmi.h"
+#include "reset.h"
+
+static const struct mtk_gate_regs spmi_mt6685_sck_top_cg_regs = {
+	.set_ofs = 0x1,
+	.clr_ofs = 0x2,
+	.sta_ofs = 0x0
+};
+
+#define GATE_SCKTOP(_id, _name, _parent, _shift)	\
+{							\
+	.id = _id,					\
+	.name = _name,					\
+	.parent_name = _parent,				\
+	.regs = &spmi_mt6685_sck_top_cg_regs,		\
+	.shift = _shift,				\
+	.flags = CLK_IGNORE_UNUSED,			\
+	.ops = &mtk_clk_gate_ops_setclr,		\
+}
+
+static const struct mtk_gate sck_top_clks[] = {
+	GATE_SCKTOP(CLK_RTC_SEC_MCLK, "rtc_sec_mclk", "rtc_sec_32k", 0),
+	GATE_SCKTOP(CLK_RTC_EOSC32, "rtc_eosc32", "clk26m", 2),
+	GATE_SCKTOP(CLK_RTC_SEC_32K, "rtc_sec_32k", "clk26m", 3),
+	GATE_SCKTOP(CLK_RTC_MCLK, "rtc_mclk", "rtc_32k", 4),
+	GATE_SCKTOP(CLK_RTC_32K, "rtc_32k", "clk26m", 5),
+};
+
+static const struct mtk_clk_desc mt6685_sck_top_mcd = {
+	.clks = sck_top_clks,
+	.num_clks = ARRAY_SIZE(sck_top_clks),
+};
+
+static const struct mtk_spmi_clk_desc mt6685_sck_top_mscd = {
+	.desc = &mt6685_sck_top_mcd,
+	.max_register = 0x10,
+};
+
+static const struct of_device_id of_match_clk_mt6685[] = {
+	{ .compatible = "mediatek,mt6685-sck-top", .data = &mt6685_sck_top_mscd },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt6685);
+
+static struct platform_driver clk_mt6685_spmi_drv = {
+	.probe = mtk_spmi_clk_simple_probe,
+	.remove = mtk_clk_simple_remove,
+	.driver = {
+		.name = "clk-spmi-mt6685",
+		.of_match_table = of_match_clk_mt6685,
+	},
+};
+module_platform_driver(clk_mt6685_spmi_drv);
+
+MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>");
+MODULE_DESCRIPTION("MediaTek MT6685 SPMI Clock IC clocks driver");
+MODULE_LICENSE("GPL");
-- 
2.51.1

Re: [PATCH v1 6/7] dt-bindings: clock: Describe MT6685 PM/Clock IC Clock Controller

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 4231 bytes --]

On Fri, Oct 24, 2025 at 10:33:00AM +0200, AngeloGioacchino Del Regno wrote:
> Add bindings to describe the SCK_TOP clock controller embedded
> in the MT6685 IC, reachable over the SPMI bus.
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> 
> NOTE: This does not contain any example because the MT6685 RTC
>       will be added to the mfd binding for MediaTek SPMI PMICs
>       and examples will be there.
> 
> ** For reviewing purposes, this is how the example will look like: **
> 
>   - |
>     #include <dt-bindings/interrupt-controller/irq.h>
>     #include <dt-bindings/spmi/spmi.h>
> 
>     spmi {
>       #address-cells = <2>;
>       #size-cells = <0>;
> 
>       pmic@9 {
>         compatible = "mediatek,mt6363";
>         reg = <0x9 SPMI_USID>;
>         interrupts = <9 1 IRQ_TYPE_LEVEL_HIGH>;
>         interrupt-controller;
>         #address-cells = <1>;
>         #interrupt-cells = <3>;
>         #size-cells = <0>;
> 
>         clock-controller@514 {
>           compatible = "mediatek,mt6685-sck-top";
>           reg = <0x514>;
>           #clock-cells = <1>;
>         };
> 
>         rtc@580 {
>           compatible = "mediatek,mt6685-rtc";
>           reg = <0x580>;
>           interrupts = <9 0 IRQ_TYPE_LEVEL_HIGH>;
>         };
>       };
>     };
> 
>  .../bindings/clock/mediatek,mt6685-clock.yaml | 37 +++++++++++++++++++
>  .../dt-bindings/clock/mediatek,mt6685-clock.h | 17 +++++++++
>  2 files changed, 54 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
>  create mode 100644 include/dt-bindings/clock/mediatek,mt6685-clock.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
> new file mode 100644
> index 000000000000..5407ebf2f3b5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt6685-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Clock Controller for MT6685 SPMI PM/Clock IC
> +
> +maintainers:
> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> +
> +description: |
> +  The clock architecture in MediaTek PMICs+Clock ICs is structured like below:
> +  Crystal(XO) or Internal ClockGen -->
> +          dividers -->
> +                      muxes
> +                           -->
> +                              clock gate

Is this the intended formatting? Looks weird with "dividers" being
unaligned with the --> above it, but maybe you were just going for x
number of spaces?

> +
> +  The device nodes provide clock gate control in different IP blocks.

I think this is more understandable as "This device provides clock gate
control", if this sck-top is only doing gating. Otherwise, not clear if
the dividers and muxes are here or elsewhere.

> +properties:
> +  compatible:
> +    const: mediatek,mt6685-sck-top
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'
> +
> +additionalProperties: false
> diff --git a/include/dt-bindings/clock/mediatek,mt6685-clock.h b/include/dt-bindings/clock/mediatek,mt6685-clock.h
> new file mode 100644
> index 000000000000..acc5e2e15ce1
> --- /dev/null
> +++ b/include/dt-bindings/clock/mediatek,mt6685-clock.h
> @@ -0,0 +1,17 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (c) 2025 Collabora Ltd.
> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MT6685_H
> +#define _DT_BINDINGS_CLK_MT6685_H
> +
> +/* SCK_TOP_CKPDN */
> +#define CLK_RTC_SEC_MCLK		0
> +#define CLK_RTC_EOSC32			1
> +#define CLK_RTC_SEC_32K			2
> +#define CLK_RTC_MCLK			3
> +#define CLK_RTC_32K			4
> +
> +#endif /* _DT_BINDINGS_CLK_MT6685_H */
> -- 
> 2.51.1
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v1 7/7] clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller

[kernel test robot]

Hi AngeloGioacchino,

kernel test robot noticed the following build errors:

[auto build test ERROR on clk/clk-next]
[also build test ERROR on linus/master v6.18-rc2 next-20251024]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/AngeloGioacchino-Del-Regno/clk-mediatek-Split-out-registration-from-mtk_clk_register_gates/20251024-164213
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link:    https://lore.kernel.org/r/20251024083301.25845-8-angelogioacchino.delregno%40collabora.com
patch subject: [PATCH v1 7/7] clk: mediatek: Add support for MT6685 PM/Clock IC Clock Controller
config: arm-allmodconfig (https://download.01.org/0day-ci/archive/20251026/202510261450.oYPrwZwR-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251026/202510261450.oYPrwZwR-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510261450.oYPrwZwR-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/clk/mediatek/clk-mtk-spmi.c: In function 'mtk_spmi_clk_simple_probe':
>> drivers/clk/mediatek/clk-mtk-spmi.c:48:20: error: implicit declaration of function 'devm_spmi_subdevice_alloc_and_add' [-Wimplicit-function-declaration]
      48 |         sub_sdev = devm_spmi_subdevice_alloc_and_add(&pdev->dev, sparent);
         |                    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/clk/mediatek/clk-mtk-spmi.c:48:18: error: assignment to 'struct spmi_subdevice *' from 'int' makes pointer from integer without a cast [-Wint-conversion]
      48 |         sub_sdev = devm_spmi_subdevice_alloc_and_add(&pdev->dev, sparent);
         |                  ^
   In file included from drivers/clk/mediatek/clk-mtk-spmi.c:16:
>> drivers/clk/mediatek/clk-mtk-spmi.c:52:53: error: invalid use of undefined type 'struct spmi_subdevice'
      52 |         regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev, &mtk_spmi_clk_regmap_config);
         |                                                     ^~
   include/linux/regmap.h:775:20: note: in definition of macro '__regmap_lockdep_wrapper'
     775 |                 fn(__VA_ARGS__, &_key,                                  \
         |                    ^~~~~~~~~~~
   drivers/clk/mediatek/clk-mtk-spmi.c:52:18: note: in expansion of macro 'devm_regmap_init_spmi_ext'
      52 |         regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev, &mtk_spmi_clk_regmap_config);
         |                  ^~~~~~~~~~~~~~~~~~~~~~~~~


vim +/devm_spmi_subdevice_alloc_and_add +48 drivers/clk/mediatek/clk-mtk-spmi.c

0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  21  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  22  int mtk_spmi_clk_simple_probe(struct platform_device *pdev)
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  23  {
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  24  	struct regmap_config mtk_spmi_clk_regmap_config = {
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  25  		.reg_bits = 16,
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  26  		.val_bits = 8,
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  27  		.fast_io = true
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  28  	};
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  29  	struct device_node *node = pdev->dev.of_node;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  30  	const struct mtk_spmi_clk_desc *mscd;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  31  	struct spmi_subdevice *sub_sdev;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  32  	struct spmi_device *sparent;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  33  	struct regmap *regmap;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  34  	int ret;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  35  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  36  	ret = of_property_read_u32(node, "reg", &mtk_spmi_clk_regmap_config.reg_base);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  37  	if (ret)
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  38  		return ret;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  39  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  40  	/* If the max_register was not declared the pdata is not valid */
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  41  	mscd = device_get_match_data(&pdev->dev);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  42  	if (mscd->max_register == 0)
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  43  		return -EINVAL;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  44  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  45  	mtk_spmi_clk_regmap_config.max_register = mscd->max_register;
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  46  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  47  	sparent = to_spmi_device(pdev->dev.parent);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24 @48  	sub_sdev = devm_spmi_subdevice_alloc_and_add(&pdev->dev, sparent);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  49  	if (IS_ERR(sub_sdev))
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  50  		return PTR_ERR(sub_sdev);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  51  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24 @52  	regmap = devm_regmap_init_spmi_ext(&sub_sdev->sdev, &mtk_spmi_clk_regmap_config);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  53  	if (IS_ERR(regmap))
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  54  		return PTR_ERR(regmap);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  55  
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  56  	return mtk_clk_simple_probe_internal(pdev, node, mscd->desc, regmap);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  57  }
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  58  EXPORT_SYMBOL_GPL(mtk_spmi_clk_simple_probe);
0986bdc04bd40e AngeloGioacchino Del Regno 2025-10-24  59  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH v1 6/7] dt-bindings: clock: Describe MT6685 PM/Clock IC Clock Controller

[AngeloGioacchino Del Regno]

Il 24/10/25 18:25, Conor Dooley ha scritto:
> On Fri, Oct 24, 2025 at 10:33:00AM +0200, AngeloGioacchino Del Regno wrote:
>> Add bindings to describe the SCK_TOP clock controller embedded
>> in the MT6685 IC, reachable over the SPMI bus.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> ---
>>
>> NOTE: This does not contain any example because the MT6685 RTC
>>        will be added to the mfd binding for MediaTek SPMI PMICs
>>        and examples will be there.
>>
>> ** For reviewing purposes, this is how the example will look like: **
>>
>>    - |
>>      #include <dt-bindings/interrupt-controller/irq.h>
>>      #include <dt-bindings/spmi/spmi.h>
>>
>>      spmi {
>>        #address-cells = <2>;
>>        #size-cells = <0>;
>>
>>        pmic@9 {
>>          compatible = "mediatek,mt6363";
>>          reg = <0x9 SPMI_USID>;
>>          interrupts = <9 1 IRQ_TYPE_LEVEL_HIGH>;
>>          interrupt-controller;
>>          #address-cells = <1>;
>>          #interrupt-cells = <3>;
>>          #size-cells = <0>;
>>
>>          clock-controller@514 {
>>            compatible = "mediatek,mt6685-sck-top";
>>            reg = <0x514>;
>>            #clock-cells = <1>;
>>          };
>>
>>          rtc@580 {
>>            compatible = "mediatek,mt6685-rtc";
>>            reg = <0x580>;
>>            interrupts = <9 0 IRQ_TYPE_LEVEL_HIGH>;
>>          };
>>        };
>>      };
>>
>>   .../bindings/clock/mediatek,mt6685-clock.yaml | 37 +++++++++++++++++++
>>   .../dt-bindings/clock/mediatek,mt6685-clock.h | 17 +++++++++
>>   2 files changed, 54 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
>>   create mode 100644 include/dt-bindings/clock/mediatek,mt6685-clock.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
>> new file mode 100644
>> index 000000000000..5407ebf2f3b5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt6685-clock.yaml
>> @@ -0,0 +1,37 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/mediatek,mt6685-clock.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: MediaTek Clock Controller for MT6685 SPMI PM/Clock IC
>> +
>> +maintainers:
>> +  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> +
>> +description: |
>> +  The clock architecture in MediaTek PMICs+Clock ICs is structured like below:
>> +  Crystal(XO) or Internal ClockGen -->
>> +          dividers -->
>> +                      muxes
>> +                           -->
>> +                              clock gate
> 
> Is this the intended formatting? Looks weird with "dividers" being
> unaligned with the --> above it, but maybe you were just going for x
> number of spaces?
> 

Yeah I was just going for x number of spaces, otherwise that may become a bit
"too long"...

>> +
>> +  The device nodes provide clock gate control in different IP blocks.
> 
> I think this is more understandable as "This device provides clock gate
> control", if this sck-top is only doing gating. Otherwise, not clear if
> the dividers and muxes are here or elsewhere.

-> Datasheets are incomplete (sad-face-here) <-

Most of the information here is grabbed from more than one downstream kernel
for more than one SoC/device, and assembled together.

The XO/clockgen and dividers are not in SCKTOP - those should be partially in
the "TOP" portion (yeah, there's a top and a sck-top), and partially in another
block that controls only the clockgen.

I didn't want to implement those two, even though I almost precisely know how to
do that (and I did it in some local tests), because I could only gather partial
information and I didn't feel confident in upstreaming something that I'm not
entirely sure about.

Same goes for the MUX part: there's some here, some there, one in scktop as well
(but I didn't describe it because again incomplete info, and even downstream the
only mux in scktop seems to be unused).

So yeah - apart from one mux, anything before clock gate is elsewhere... I can
change that statement to the one you proposed, looks a bit better than what I
came up with, so thanks for that :-D

> 
>> +properties:
>> +  compatible:
>> +    const: mediatek,mt6685-sck-top
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - '#clock-cells'
>> +
>> +additionalProperties: false
>> diff --git a/include/dt-bindings/clock/mediatek,mt6685-clock.h b/include/dt-bindings/clock/mediatek,mt6685-clock.h
>> new file mode 100644
>> index 000000000000..acc5e2e15ce1
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/mediatek,mt6685-clock.h
>> @@ -0,0 +1,17 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
>> +/*
>> + * Copyright (c) 2025 Collabora Ltd.
>> + *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>> + */
>> +
>> +#ifndef _DT_BINDINGS_CLK_MT6685_H
>> +#define _DT_BINDINGS_CLK_MT6685_H
>> +
>> +/* SCK_TOP_CKPDN */
>> +#define CLK_RTC_SEC_MCLK		0
>> +#define CLK_RTC_EOSC32			1
>> +#define CLK_RTC_SEC_32K			2
>> +#define CLK_RTC_MCLK			3
>> +#define CLK_RTC_32K			4
>> +
>> +#endif /* _DT_BINDINGS_CLK_MT6685_H */
>> -- 
>> 2.51.1
>>