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From: Conor Dooley <conor@kernel.org>
To: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	pierre-henry.moussay@microchip.com,
	valentina.fernandezalanis@microchip.com,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	Brian Masney <bmasney@redhat.com>
Subject: Re: [PATCH v5 5/9] clk: microchip: mpfs: use regmap for clocks
Date: Fri, 24 Oct 2025 11:30:08 +0100	[thread overview]
Message-ID: <20251024-vocalist-irritable-dcac9f7db3ce@spud> (raw)
In-Reply-To: <20251024-dimness-everyday-1c074ce1f203@spud>

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On Fri, Oct 24, 2025 at 11:20:23AM +0100, Conor Dooley wrote:
> On Thu, Oct 23, 2025 at 07:06:01AM +0300, Claudiu Beznea wrote:
> > On 10/13/25 20:45, Conor Dooley wrote:
> > > From: Conor Dooley <conor.dooley@microchip.com>
> > > +static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
> > > +{
> > > +	struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
> > > +	struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
> > > +	unsigned long flags;
> > > +	u32 val;
> > > +	int divider_setting;
> > 
> > This could be moved near flags to keep the reverse christmas tree order as
> > in the rest of this patch.
> 
> The driver doesn't (intentionally) use reverse christmas tree. If it
> does, that's just a byproduct of putting bigger types before smaller
> ones.
> 
> > > +	divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
> > > +
> > > +	if (divider_setting < 0)
> > > +		return divider_setting;
> > > +
> > > +	spin_lock_irqsave(&mpfs_clk_lock, flags);
> > 
> > As spin locking is introduced in this file by this patch, you can go
> > directly w/ cleanup helpers for locking.

Actually, if using regmap_update_bits(), locking might be entirely
removable. Depends on if there's some rmw sequence that can't move to
that.

> > 
> > > +
> > > +	regmap_read(cfg->map, cfg->map_offset, &val);
> > > +	val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
> > 
> > Why cfg_hw->cfg.shift here --------------------^ but cfg->shift on the next
> > line?
> > 
> > > +	val |= divider_setting << cfg->shift;
> > > +	regmap_write(cfg->map, cfg->map_offset, val);
> > 
> > Can't the regmap_read() + updated + regmap_write() be replaced by
> > regmap_update_bits() ?
> 
> Yeah, I suppose it could. Ultimately what's here is a revert of with
> readl()/writel() replaced by regmap operations directly, so the answer
> to the above three items is that that's how they were done before the
> patch I am reverting. That's probably the answer to 90% of the things
> you've said here, this is how they were done prior to the commit I am
> reverting.
> 



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  reply	other threads:[~2025-10-24 10:30 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 17:45 [PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code Conor Dooley
2025-10-13 17:45 ` [PATCH v5 1/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Conor Dooley
2025-10-13 17:45 ` [PATCH v5 2/9] soc: microchip: add mfd drivers for two syscon regions " Conor Dooley
2025-10-23  4:04   ` Claudiu Beznea
2025-10-23  9:12     ` Conor Dooley
2025-10-23 10:15     ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 3/9] reset: mpfs: add non-auxiliary bus probing Conor Dooley
2025-10-23  4:06   ` Claudiu Beznea
2025-10-24 10:07     ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 4/9] dt-bindings: clk: microchip: mpfs: remove first reg region Conor Dooley
2025-10-13 17:45 ` [PATCH v5 5/9] clk: microchip: mpfs: use regmap for clocks Conor Dooley
2025-10-23  4:06   ` Claudiu Beznea
2025-10-23 14:42     ` Brian Masney
2025-10-24 10:20     ` Conor Dooley
2025-10-24 10:30       ` Conor Dooley [this message]
2025-10-13 17:45 ` [PATCH v5 6/9] riscv: dts: microchip: fix mailbox description Conor Dooley
2025-10-13 17:45 ` [PATCH v5 7/9] riscv: dts: microchip: convert clock and reset to use syscon Conor Dooley
2025-10-13 17:45 ` [PATCH v5 8/9] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Conor Dooley
2025-10-13 17:45 ` [PATCH v5 9/9] MAINTAINERS: rename " Conor Dooley
2025-10-21 13:31 ` (subset) [PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code Conor Dooley

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