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From: Conor Dooley <conor@kernel.org>
To: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	pierre-henry.moussay@microchip.com,
	valentina.fernandezalanis@microchip.com,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v5 3/9] reset: mpfs: add non-auxiliary bus probing
Date: Fri, 24 Oct 2025 11:07:03 +0100	[thread overview]
Message-ID: <20251024-void-esteemed-832b3bf5b965@spud> (raw)
In-Reply-To: <60544429-3eeb-41df-b42c-613da651b4a1@tuxon.dev>

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On Thu, Oct 23, 2025 at 07:06:48AM +0300, Claudiu Beznea wrote:
> Hi, Conor,
> 
> On 10/13/25 20:45, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > While the auxiliary bus was a nice bandaid, and meant that re-writing
> > the representation of the clock regions in devicetree was not required,
> > it has run its course. The "mss_top_sysreg" region that contains the
> > clock and reset regions, also contains pinctrl and an interrupt
> > controller, so the time has come rewrite the devicetree and probe the
> > reset controller from an mfd devicetree node, rather than implement
> > those drivers using the auxiliary bus. Wanting to avoid propagating this
> > naive/incorrect description of the hardware to the new pic64gx SoC is a
> > major motivating factor here.
> > 
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > v4:
> > - Only use driver specific lock for non-regmap writes
> > 
> > v2:
> > - Implement the request to use regmap_update_bits(). I found that I then
> >   hated the read/write helpers since they were just bloat, so I ripped
> >   them out. I replaced the regular spin_lock_irqsave() stuff with a
> >   guard(spinlock_irqsave), since that's a simpler way of handling the two
> >   different paths through such a trivial pair of functions.
> > ---
> >  drivers/reset/reset-mpfs.c | 83 ++++++++++++++++++++++++++++++--------
> >  1 file changed, 66 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c
> > index f6fa10e03ea8..8e5ed4deecf3 100644
> > --- a/drivers/reset/reset-mpfs.c
> > +++ b/drivers/reset/reset-mpfs.c
> > @@ -7,13 +7,16 @@
> >   *
> >   */
> >  #include <linux/auxiliary_bus.h>
> > +#include <linux/cleanup.h>
> >  #include <linux/delay.h>
> >  #include <linux/io.h>
> > +#include <linux/mfd/syscon.h>
> 
> Should you add a depends on MFD_SYSCON ?

Perhaps, but it's a NOP. This driver depends on the clock driver, which
does have a depends on MFD_SYSCON. I'll add it, but makes no difference
to either the build or functionality.

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  reply	other threads:[~2025-10-24 10:07 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-13 17:45 [PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code Conor Dooley
2025-10-13 17:45 ` [PATCH v5 1/9] dt-bindings: soc: microchip: document the simple-mfd syscon on PolarFire SoC Conor Dooley
2025-10-13 17:45 ` [PATCH v5 2/9] soc: microchip: add mfd drivers for two syscon regions " Conor Dooley
2025-10-23  4:04   ` Claudiu Beznea
2025-10-23  9:12     ` Conor Dooley
2025-10-23 10:15     ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 3/9] reset: mpfs: add non-auxiliary bus probing Conor Dooley
2025-10-23  4:06   ` Claudiu Beznea
2025-10-24 10:07     ` Conor Dooley [this message]
2025-10-13 17:45 ` [PATCH v5 4/9] dt-bindings: clk: microchip: mpfs: remove first reg region Conor Dooley
2025-10-13 17:45 ` [PATCH v5 5/9] clk: microchip: mpfs: use regmap for clocks Conor Dooley
2025-10-23  4:06   ` Claudiu Beznea
2025-10-23 14:42     ` Brian Masney
2025-10-24 10:20     ` Conor Dooley
2025-10-24 10:30       ` Conor Dooley
2025-10-13 17:45 ` [PATCH v5 6/9] riscv: dts: microchip: fix mailbox description Conor Dooley
2025-10-13 17:45 ` [PATCH v5 7/9] riscv: dts: microchip: convert clock and reset to use syscon Conor Dooley
2025-10-13 17:45 ` [PATCH v5 8/9] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Conor Dooley
2025-10-13 17:45 ` [PATCH v5 9/9] MAINTAINERS: rename " Conor Dooley
2025-10-21 13:31 ` (subset) [PATCH v5 0/9] Redo PolarFire SoC's mailbox/clock devicestrees and related code Conor Dooley

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