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[75.72.117.212]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-5abb7fdb7c7sm2427824173.44.2025.10.24.12.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Oct 2025 12:15:54 -0700 (PDT) From: Alex Elder To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, han.xu@nxp.com, broonie@kernel.org, dlan@gentoo.org, pjw@kernel.org Cc: Frank.li@nxp.com, p.zabel@pengutronix.de, guodong@riscstar.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, apatel@ventanamicro.com, joel@jms.id.au, geert+renesas@glider.be, cyy@cyyself.name, heylenay@4d2.org, conor.dooley@microchip.com, fustini@kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, spacemit@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/9] spi: enable the SpacemiT K1 SoC QSPI Date: Fri, 24 Oct 2025 14:15:40 -0500 Message-ID: <20251024191550.194946-1-elder@riscstar.com> X-Mailer: git-send-email 2.48.1 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the SpacemiT K1 SoC QSPI. This IP is generally compatible with the Freescale QSPI driver, requiring three minor changes to enable it to be supported. The changes are: - Adding support for optional resets - Having the clock *not* be disabled when changing its rate - Allowing the size of storage blocks written to flash chips to be set to something different from the AHB buffer size This version of the series addresses comments received in review of version 2. -Alex This series is available here: https://github.com/riscstar/linux/tree/outgoing/qspi-v3 Version 3 addresses comments recieved during review of v2: - This version fully tested and confirmed to work on BPI-F3 - Added Acked-by from Conor on patches 1 and 2 - Added Reviewed-by from Frank on patches 1 and 6 - Moved the reset property conditional under allOf in the binding - In patch 5, needs_clk_disable() is no longer inline - Tweaked the description in patch 5 - Renamed a local variable to be "sfa_size" in patch 6 - Changed the subject line in patch 6 - The sfa_size field was not being assigned in spacemit_k1_data; now it is set to SZ_1K Here is version 2: https://lore.kernel.org/lkml/20251023175922.528868-1-elder@riscstar.com/ Version 2 addresses comments recieved during review of v1: - The "reset" property now only applies to spacemit,k1-qspi compatible. - Patch 1 (previously patch 2) now points out that this is the first non-Freescale device using the binding. - Added Frank Li's Reviewed-by on patch 3. - A quirk flag has been renamed to be QUADSPI_QUIRK_SKIP_CLK_DISABLE. - The predicate for that quirk now returns bool type. - All other similar predicates now return bool type; this is done in a new patch (patch 4). - If non-zero, new field fsl_qspi_devtype_data->sfa_size defines the size of the serial flash regions, rather than ahb_buf_size. - A continued line in the Kconfig is now aligned. - Patch descriptions are wrapped at 75 columns. Here is version 1: https://lore.kernel.org/lkml/20251020165152.666221-1-elder@riscstar.com/ Alex Elder (9): dt-bindings: spi: fsl-qspi: support SpacemiT K1 dt-bindings: spi: fsl-qspi: add optional resets spi: fsl-qspi: add optional reset support spi: fsl-qspi: switch predicates to bool spi: fsl-qspi: add a clock disable quirk spi: fsl-qspi: introduce sfa_size devtype data spi: fsl-qspi: support the SpacemiT K1 SoC riscv: dts: spacemit: enable K1 SoC QSPI on BPI-F3 riscv: defconfig: enable SPI_FSL_QUADSPI as a module .../bindings/spi/fsl,spi-fsl-qspi.yaml | 15 ++++ .../boot/dts/spacemit/k1-bananapi-f3.dts | 6 ++ arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 21 +++++ arch/riscv/boot/dts/spacemit/k1.dtsi | 16 ++++ arch/riscv/configs/defconfig | 1 + drivers/spi/Kconfig | 3 +- drivers/spi/spi-fsl-qspi.c | 88 +++++++++++++------ 7 files changed, 124 insertions(+), 26 deletions(-) base-commit: 72fb0170ef1f45addf726319c52a0562b6913707 -- 2.48.1