From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Andrew Lunn <andrew@lunn.ch>,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
Daniel Scally <dan.scally@ideasonboard.com>,
Kieran Bingham <kieran.bingham@ideasonboard.com>,
Stefan Klug <stefan.klug@ideasonboard.com>,
Conor Dooley <conor+dt@kernel.org>,
Fabio Estevam <festevam@gmail.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Shawn Guo <shawnguo@kernel.org>
Subject: Re: [PATCH] arm64: dts: imx8mp-debix-model-a: Disable EEE for 1000T
Date: Tue, 28 Oct 2025 01:08:21 +0200 [thread overview]
Message-ID: <20251027230821.GA24987@pendragon.ideasonboard.com> (raw)
In-Reply-To: <aP88KO8uVrEQlmMm@shell.armlinux.org.uk>
On Mon, Oct 27, 2025 at 09:32:24AM +0000, Russell King (Oracle) wrote:
> On Mon, Oct 27, 2025 at 09:27:49AM +0200, Laurent Pinchart wrote:
> > I've tried to diagnose the issue by adding interrupt counters to
> > dwmac4_irq_status(), counting interrupts for each bit of GMAC_INT_STATUS
> > (0x00b0). Bit RGSMIIIS (0) is the only one that seems linked to the
> > interrupts storm, increasing at around 10k per second. However, the
> > corresponding bit in GMAC_INT_EN (0x00b4) is *not* set.
>
> This is a change in the PCS series rather than the EEE series. It would
> be good to narrow down whehn this problem appeared for you.
>
> The RGSMIIIS bit set without RGSMIIIM (0x00b4 bit 0) shouldn't result
> in an interrupt storm since the status will be masked. That doens't
> mean that RGSMIIIS won't be set. So, at this point I'm not worried
> about that.
>
> Can you print the intr_status and intr_values in dwmac4_irq_status(),
> maybe something like this:
>
> static int ctr = 0;
>
> if (ctr++ >= 9996) {
> printk("stmmac: INTS=%08x INTE=%08x\n", intr_status,
> intr_enable);
>
> if (ctr >= 10000)
> ctr = 0;
> }
>
> /* Discard disabled bits */
> intr_status &= intr_enable;
>
> which should avoid too much noise during "normal" operation. It'll
> print six consecutive interrupts every 10000.
I'm always getting the same values:
[ 62.638187] stmmac: INTS=00000001 INTE=00001030
Now the funny part. I get about 20 of those messages printed to the
serial console every time I press enter, and rarely otherwise. Typing
other characters in the console do not trigger the messages.
> > I ould suspect that the LPI RX exit interrupt is the one that fires
> > constantly given its name, but I'm not sure how to test that.
>
> You can check this because the LPI interrupts have statistic counter
> associated with them. ethtool -S should give these, look for
> lpi_mode_n.
# ethtool -S eth0 | grep lpi
irq_tx_path_in_lpi_mode_n: 32
irq_tx_path_exit_lpi_mode_n: 32
irq_rx_path_in_lpi_mode_n: 2512
irq_rx_path_exit_lpi_mode_n: 2508
That seems reasonable.
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2025-10-27 23:08 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-26 12:29 [PATCH] arm64: dts: imx8mp-debix-model-a: Disable EEE for 1000T Laurent Pinchart
2025-10-27 1:31 ` Fabio Estevam
2025-10-27 3:08 ` Andrew Lunn
2025-10-27 7:27 ` Laurent Pinchart
2025-10-27 8:47 ` Emanuele Ghidoli
2025-10-27 9:00 ` Russell King (Oracle)
2025-10-27 9:18 ` Emanuele Ghidoli
2025-10-27 9:32 ` Russell King (Oracle)
2025-10-27 23:08 ` Laurent Pinchart [this message]
2025-10-27 11:22 ` Russell King (Oracle)
2025-10-27 23:15 ` Laurent Pinchart
2025-10-27 9:12 ` Oleksij Rempel
2025-10-27 10:02 ` Laurent Pinchart
2025-10-27 10:23 ` Oleksij Rempel
2025-10-27 10:31 ` Laurent Pinchart
2025-10-27 10:34 ` Russell King (Oracle)
2025-10-27 10:44 ` Oleksij Rempel
2025-10-27 10:48 ` Russell King (Oracle)
2025-10-27 12:50 ` Andrew Lunn
2025-10-27 14:50 ` Oleksij Rempel
2025-11-12 12:34 ` Russell King (Oracle)
2025-11-12 12:41 ` Kieran Bingham
2025-11-12 12:56 ` Russell King (Oracle)
2025-11-13 1:17 ` Laurent Pinchart
2025-11-12 21:32 ` Laurent Pinchart
2025-10-27 9:07 ` Russell King (Oracle)
2025-10-27 9:33 ` Laurent Pinchart
2025-10-27 9:45 ` Russell King (Oracle)
2025-10-27 9:55 ` Laurent Pinchart
2025-10-27 13:33 ` Russell King (Oracle)
2025-10-27 15:13 ` Russell King (Oracle)
2025-10-27 19:52 ` Andrew Lunn
2025-10-27 23:46 ` Laurent Pinchart
2025-10-28 0:57 ` Russell King (Oracle)
2025-10-28 7:18 ` Laurent Pinchart
2025-11-11 23:54 ` Laurent Pinchart
2025-11-12 12:03 ` Russell King (Oracle)
2025-11-12 22:25 ` Laurent Pinchart
2025-11-13 1:06 ` Laurent Pinchart
2025-11-13 10:59 ` Russell King (Oracle)
2025-11-14 22:26 ` Laurent Pinchart
2025-11-18 1:50 ` Wei Fang
2025-11-22 7:22 ` Laurent Pinchart
2025-11-22 9:57 ` Russell King (Oracle)
2025-11-23 5:38 ` Laurent Pinchart
2025-11-23 8:52 ` Russell King (Oracle)
2025-11-23 15:23 ` Laurent Pinchart
2025-11-23 17:11 ` Russell King (Oracle)
2025-11-24 0:12 ` Laurent Pinchart
2025-11-24 5:44 ` Oleksij Rempel
2025-11-24 8:43 ` Russell King (Oracle)
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