Re: [PATCH v4 3/7] dt-bindings: pci: spacemit: introduce PCIe host controller

Rob Herring
2025-10-31T00:58:50Z

On Thu, Oct 30, 2025 at 05:02:54PM -0500, Alex Elder wrote:
> Add the Device Tree binding for the PCIe root complex found on the
> SpacemiT K1 SoC. This device is derived from the Synopsys Designware
> PCIe IP. It supports up to three PCIe ports operating at PCIe gen 2
> link speeds (5 GT/sec). One of the ports uses a combo PHY, which is
> typically used to support a USB 3 port.
>
> Signed-off-by: Alex Elder <elder@riscstar.com>
> ---
> .../bindings/pci/spacemit,k1-pcie-host.yaml | 157 ++++++++++++++++++
> 1 file changed, 157 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> new file mode 100644
> index 0000000000000..58239a155ecc0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml
> @@ -0,0 +1,157 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/spacemit,k1-pcie-host.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 PCI Express Host Controller
> +
> +maintainers:
> + - Alex Elder <elder@riscstar.com>
> +
> +description: >
> + The SpacemiT K1 SoC PCIe host controller is based on the Synopsys
> + DesignWare PCIe IP. The controller uses the DesignWare built-in
> + MSI interrupt controller, and supports 256 MSIs.

Wrap lines at 80.

> +
> +allOf:
> + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> +
> +properties:
> + compatible:
> + const: spacemit,k1-pcie
> +
> + reg:
> + items:
> + - description: DesignWare PCIe registers
> + - description: ATU address space
> + - description: PCIe configuration space
> + - description: Link control registers
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: atu
> + - const: config
> + - const: link
> +
> + clocks:
> + items:
> + - description: DWC PCIe Data Bus Interface (DBI) clock
> + - description: DWC PCIe application AXI-bus master interface clock
> + - description: DWC PCIe application AXI-bus slave interface clock
> +
> + clock-names:
> + items:
> + - const: dbi
> + - const: mstr
> + - const: slv
> +
> + resets:
> + items:
> + - description: DWC PCIe Data Bus Interface (DBI) reset
> + - description: DWC PCIe application AXI-bus master interface reset
> + - description: DWC PCIe application AXI-bus slave interface reset
> +
> + reset-names:
> + items:
> + - const: dbi
> + - const: mstr
> + - const: slv
> +
> + interrupts:
> + items:
> + - description: Interrupt used for MSIs
> +
> + interrupt-names:
> + const: msi
> +
> + spacemit,apmu:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description:
> + A phandle that refers to the APMU system controller, whose
> + regmap is used in managing resets and link state, along with
> + and offset of its reset control register.
> + items:
> + - items:
> + - description: phandle to APMU system controller
> + - description: register offset
> +
> +patternProperties:
> + '^pcie?@':

It's always PCIe, so drop the '?'.

With that,

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>