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[34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47732fe1075sm31814585e9.11.2025.10.31.05.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 05:56:07 -0700 (PDT) From: Tudor Ambarus Date: Fri, 31 Oct 2025 12:56:05 +0000 Subject: [PATCH 06/11] soc: samsung: exynos-chipid: make asv_init opt-in Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251031-gs101-chipid-v1-6-d78d1076b210@linaro.org> References: <20251031-gs101-chipid-v1-0-d78d1076b210@linaro.org> In-Reply-To: <20251031-gs101-chipid-v1-0-d78d1076b210@linaro.org> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: Krzysztof Kozlowski , semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761915362; l=2276; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=2b2RMRAbQHJoSplfNlNFCrm413eCNhV1Uu0eYavspbw=; b=Y7M8VEUe8Ma3wIFBHexvsVQYqz1qW9K3xn6HQU8oL0V54u5FhpPmhqkF0rW372bcl2eRdsAb/ mahZ6Jb2R/0AW1hOGjVtZBKdJz6HTZeH+NKyzbFB+XoMLLo+kDS0/zg X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Current ASV handling is tightly coupled with a specific Product ID (0xe5422000) - only one from the list of Product IDs defined in the soc_ids[] array. Since the implementation is highly specific, make te asv_init opt-in. Note that the exynos850_chipid_data was intentionally filled with .asv_init = true to not add any change in functionality, even if ASV bails out early for these chips. We can follow up with a patch to remove the ASV init for these chips, or better, to update them to use the nvmem API that GS101 will use, as I suspect they reference OTP controller registers too. Signed-off-by: Tudor Ambarus --- drivers/soc/samsung/exynos-chipid.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 7b1951f28e8d4958ab941af91dab4b0183ceda5f..5678bc85c4d93547e446caade64a0b650d06a332 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -39,6 +39,7 @@ struct exynos_chipid_variant { unsigned int rev_reg; /* revision register offset */ unsigned int main_rev_shift; /* main revision offset in rev_reg */ unsigned int sub_rev_shift; /* sub revision offset in rev_reg */ + bool asv_init; }; static const struct exynos_soc_id { @@ -163,9 +164,11 @@ static int exynos_chipid_probe(struct platform_device *pdev) if (IS_ERR(soc_dev)) return PTR_ERR(soc_dev); - ret = exynos_asv_init(dev, exynos_chipid->regmap); - if (ret) - goto err; + if (data->asv_init) { + ret = exynos_asv_init(dev, exynos_chipid->regmap); + if (ret) + goto err; + } platform_set_drvdata(pdev, soc_dev); @@ -193,6 +196,7 @@ static const struct exynos_chipid_variant exynos4210_chipid_data = { .rev_reg = 0x0, .main_rev_shift = 4, .sub_rev_shift = 0, + .asv_init = true, }; static const struct exynos_chipid_variant exynos850_chipid_data = { @@ -200,6 +204,7 @@ static const struct exynos_chipid_variant exynos850_chipid_data = { .rev_reg = 0x10, .main_rev_shift = 20, .sub_rev_shift = 16, + .asv_init = true, }; static const struct of_device_id exynos_chipid_of_device_ids[] = { -- 2.51.1.930.gacf6e81ea2-goog