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[34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47732ff7fdbsm31077535e9.16.2025.10.31.05.45.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 05:45:16 -0700 (PDT) From: Tudor Ambarus Subject: [PATCH 0/5] nvmem: add Samsung Exynos OTP support Date: Fri, 31 Oct 2025 12:45:08 +0000 Message-Id: <20251031-gs101-otp-v1-0-2a54f6c4e7b6@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAFSvBGkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDI1NDA2ND3fRiQwND3fySAl2jNGOLVIskkyRzS2MloPqCotS0zAqwWdGxtbU Av8ZwdFsAAAA= X-Change-ID: 20251031-gs101-otp-2f38e8b4b793 To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761914715; l=1825; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=eShtlJ8Q5lLAIYL5hn7v+uZe4nyW0U4dTV2Vv/o37Is=; b=Cav6xp6EkVef+kR5+xm0NcqzjGfCB8JtxlbVHdTW7e4KMSsgOBlOfS4QS/NSWUZKRyXAq0Ff3 4hPYHB6jVi2BPtPgXa6/b8DGjvet/fG+YJ7cfBVavtwrAhttcx6A8OS X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= The patch set has the typical dependency of the DT patch depending on the bindings patch. I propose thus to have the bindings patch taken via the Samsung SoC tree, if not all. Add support for the Samsung Exynos OTP controller. On the Google GS101 SoC, this controller provides 32 Kbit of OTP memory space that can be read/program/lock using a specific sequence of register accesses. The OTP controller register space is of interest as well because it contains dedicated registers for the Product ID and the Chip ID (apart from other things like TMU or ASV info). Register the OTP controller register space as a nvmem device so that other drivers can access its contents using nvmem cells. Support for the OTP memory space can follow and be modeled as a dedicated nvmem device. Signed-off-by: Tudor Ambarus --- Tudor Ambarus (5): dt-bindings: nvmem: add google,gs101-otp nvmem: add Samsung Exynos OTP support arm64: dts: exynos: gs101: add OTP node arm64: defconfig: enable Samsung Exynos OTP controller MAINTAINERS: add entry for the Samsung Exynos OTP controller driver .../bindings/nvmem/google,gs101-otp.yaml | 68 +++++++++++++++ MAINTAINERS | 8 ++ arch/arm64/boot/dts/exynos/google/gs101.dtsi | 17 ++++ arch/arm64/configs/defconfig | 1 + drivers/nvmem/Kconfig | 10 +++ drivers/nvmem/Makefile | 2 + drivers/nvmem/exynos-otp.c | 98 ++++++++++++++++++++++ 7 files changed, 204 insertions(+) --- base-commit: 73f7017e663620a616171cc80d62504a624dc4de change-id: 20251031-gs101-otp-2f38e8b4b793 Best regards, -- Tudor Ambarus