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[34.77.53.213]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47732ff7fdbsm31077535e9.16.2025.10.31.05.45.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Oct 2025 05:45:20 -0700 (PDT) From: Tudor Ambarus Date: Fri, 31 Oct 2025 12:45:12 +0000 Subject: [PATCH 4/5] arm64: defconfig: enable Samsung Exynos OTP controller Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251031-gs101-otp-v1-4-2a54f6c4e7b6@linaro.org> References: <20251031-gs101-otp-v1-0-2a54f6c4e7b6@linaro.org> In-Reply-To: <20251031-gs101-otp-v1-0-2a54f6c4e7b6@linaro.org> To: Srinivas Kandagatla , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Alim Akhtar , Peter Griffin , =?utf-8?q?Andr=C3=A9_Draszik?= Cc: semen.protsenko@linaro.org, willmcvicker@google.com, kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Tudor Ambarus X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761914716; l=915; i=tudor.ambarus@linaro.org; s=20241212; h=from:subject:message-id; bh=jbtOQh+KZGaronPKGSCjW9AW/6hcLTFo8o99haI6DgE=; b=anPmmraBvSuRYrza8lT7XXPyLkgmlAH/yyD7w1SjaBtSE3hCPJZEkgDHb0kPl8CtR+4Ta8bjR mEUElj9TnrgDeBa4TOQQUClCBg6x6jMhPpnKkx/DI+wT0L+NvF59rcO X-Developer-Key: i=tudor.ambarus@linaro.org; a=ed25519; pk=uQzE0NXo3dIjeowMTOPCpIiPHEz12IA/MbyzrZVh9WI= Enable the exynos-otp nvmem driver for fuse access on the Samsung Exynos SoCs. The fuse block stores various system information (Product ID, Chip ID, TMU, ASV, etc.) which will be accessed by client drivers. Signed-off-by: Tudor Ambarus --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 646097e94efe7f1a18fb59d5b6dfc6268be91383..6433e3c0f88b892ce6f2ee190f866a6ab4889771 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1682,6 +1682,7 @@ CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m CONFIG_NVIDIA_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m CONFIG_MESON_DDR_PMU=m CONFIG_NVMEM_LAYOUT_SL28_VPD=m +CONFIG_NVMEM_EXYNOS_OTP=m CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_ELE=m CONFIG_NVMEM_IMX_OCOTP_SCU=y -- 2.51.1.930.gacf6e81ea2-goog