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Mon, 03 Nov 2025 10:20:17 -0800 (PST) Received: from QCOM-eG0v1AUPpu.qualcomm.com ([2a01:e0a:82c:5f0:8842:5746:daeb:a8f8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4773c53ec2csm169096545e9.11.2025.11.03.10.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Nov 2025 10:20:16 -0800 (PST) From: Loic Poulain To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, sre@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, Loic Poulain Subject: [PATCH 2/5] power: reset: qcom-pon: Add support for WARM reset Date: Mon, 3 Nov 2025 19:20:03 +0100 Message-Id: <20251103182006.1158383-3-loic.poulain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251103182006.1158383-1-loic.poulain@oss.qualcomm.com> References: <20251103182006.1158383-1-loic.poulain@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: GWyE54Ab4ajhaEDDQ_2e37MrwDae8VwV X-Authority-Analysis: v=2.4 cv=bqBBxUai c=1 sm=1 tr=0 ts=6908f262 cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=xqWC_Br6kY4A:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=SLKSYyjenuDOKbfwxIIA:9 a=kacYvNCVWA4VmyqE58fU:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTAzMDE2NCBTYWx0ZWRfXwehAab73v+kV 8LsnN8nzr/5ud+in16oQRc57jfzhwyymJOa8eaO7+JGcMrvjy+1gAD+pBUVJ8JPoe24EBJccSUc Kb2XH78pFV82RnGh6I/EyWf14usSTe8Zp1kh7oO4i74tjdCAYNE8Ly+b2CF5A58+2RXQO7c+ftq 07+/cfVePjmb+9EBmrXQF4h+hs+Pp/X6NXU1YkdE91FAkuLaNcfrMXFwE7Fc9ZECH0RL6BpI1rU KYp7s8SpiD12WAp1SQUtzzvX9Ue3CUv+5KckL5k3D8Pty810TSZbNYuzsyQlHTFe/KSlj1j0yjc 9+O3G6/ZxB5yp0l07g14tMNVUMYCMnzpZvbDFzBdgByLE6JqJYG7fm8f5r9LwC7ERIiqW8hViJx wZsjXZmwOUd90scoxIY0X8k3Y+tWuA== X-Proofpoint-GUID: GWyE54Ab4ajhaEDDQ_2e37MrwDae8VwV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-03_04,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 spamscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511030164 This mechanism can be used when firmware lacks proper warm-reset handling, for example, when the PSCI SYSTEM_RESET2 function is not implemented. It enables the warm reset functionality via the PMIC. This fallback is only enabled if qcom,warm-reset property is present. Signed-off-by: Loic Poulain --- drivers/power/reset/qcom-pon.c | 47 ++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/power/reset/qcom-pon.c b/drivers/power/reset/qcom-pon.c index 7e108982a582..684e9fe9987d 100644 --- a/drivers/power/reset/qcom-pon.c +++ b/drivers/power/reset/qcom-pon.c @@ -19,12 +19,20 @@ #define NO_REASON_SHIFT 0 +#define PON_SW_RESET_S2_CTL 0x62 +#define PON_SW_RESET_S2_CTL_WARM_RST 0x01 +#define PON_SW_RESET_S2_CTL2 0x63 +#define PON_SW_RESET_S2_CTL2_RST_EN BIT(7) +#define PON_SW_RESET_GO 0x64 +#define PON_SW_RESET_GO_MAGIC 0xa5 + struct qcom_pon { struct device *dev; struct regmap *regmap; u32 baseaddr; struct reboot_mode_driver reboot_mode; long reason_shift; + bool warm_reset; }; static int qcom_pon_reboot_mode_write(struct reboot_mode_driver *reboot, @@ -44,6 +52,37 @@ static int qcom_pon_reboot_mode_write(struct reboot_mode_driver *reboot, return ret; } +static int pm8916_pon_reset(struct sys_off_data *data) +{ + struct qcom_pon *pon = data->cb_data; + int ret; + + if (!pon->warm_reset || data->mode != REBOOT_WARM) + return NOTIFY_DONE; + + ret = regmap_write(pon->regmap, + pon->baseaddr + PON_SW_RESET_S2_CTL, + PON_SW_RESET_S2_CTL_WARM_RST); + if (ret) + return NOTIFY_BAD; + + ret = regmap_update_bits(pon->regmap, + pon->baseaddr + PON_SW_RESET_S2_CTL2, + PON_SW_RESET_S2_CTL2_RST_EN, + PON_SW_RESET_S2_CTL2_RST_EN); + if (ret) + return NOTIFY_BAD; + + ret = regmap_write(pon->regmap, pon->baseaddr + PON_SW_RESET_GO, + PON_SW_RESET_GO_MAGIC); + if (ret) + return NOTIFY_BAD; + + mdelay(100); + + return NOTIFY_DONE; +} + static int qcom_pon_probe(struct platform_device *pdev) { struct qcom_pon *pon; @@ -80,8 +119,16 @@ static int qcom_pon_probe(struct platform_device *pdev) } } + pon->warm_reset = of_property_read_bool(pdev->dev.of_node, "qcom,warm-reset"); + platform_set_drvdata(pdev, pon); + /* Higher priority than psci to handle warm-reset properly */ + error = devm_register_sys_off_handler(&pdev->dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH, + pm8916_pon_reset, pon); + if (error) + return dev_err_probe(&pdev->dev, error, "reboot registration fail\n"); + return devm_of_platform_populate(&pdev->dev); } -- 2.34.1