* [PATCH 0/2] Enable ETR and CTCU device for hamoa
@ 2025-11-04 8:10 Jie Gan
2025-11-04 8:10 ` [PATCH 1/2] dt-binding: arm: add " Jie Gan
2025-11-04 8:10 ` [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices Jie Gan
0 siblings, 2 replies; 9+ messages in thread
From: Jie Gan @ 2025-11-04 8:10 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Jie Gan
Enable support for ETR and CTCU devices on the Hamoa platform. The
newly added CTCU compatible will fallback to qcom,sa8775p-ctcu for device
probing.
Dependency of the binding path:
https://lore.kernel.org/all/20251103-enable-ctcu-for-monaco-v4-1-92ff83201584@oss.qualcomm.com/
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Jie Gan (2):
dt-binding: arm: add CTCU device for hamoa
arm64: dts: qcom: hamoa: enable ETR and CTCU devices
.../bindings/arm/qcom,coresight-ctcu.yaml | 1 +
arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 ++++++++++++++++++++-
2 files changed, 160 insertions(+), 1 deletion(-)
---
base-commit: 23ece2b586cd740840b5b9359a767477435e94d0
change-id: 20251104-enable-etr-and-ctcu-for-hamoa-5dc4959e438e
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 1/2] dt-binding: arm: add CTCU device for hamoa
2025-11-04 8:10 [PATCH 0/2] Enable ETR and CTCU device for hamoa Jie Gan
@ 2025-11-04 8:10 ` Jie Gan
2025-11-05 8:59 ` Krzysztof Kozlowski
2025-11-04 8:10 ` [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices Jie Gan
1 sibling, 1 reply; 9+ messages in thread
From: Jie Gan @ 2025-11-04 8:10 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Jie Gan
Document the CTCU compatible for Hamoa, enabling support for the
CTCU device on the Hamoa platform.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index 460f38ddbd73..57dede7a90e9 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -29,6 +29,7 @@ properties:
oneOf:
- items:
- enum:
+ - qcom,hamoa-ctcu
- qcom,qcs8300-ctcu
- const: qcom,sa8775p-ctcu
- enum:
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices
2025-11-04 8:10 [PATCH 0/2] Enable ETR and CTCU device for hamoa Jie Gan
2025-11-04 8:10 ` [PATCH 1/2] dt-binding: arm: add " Jie Gan
@ 2025-11-04 8:10 ` Jie Gan
2025-11-04 12:47 ` Konrad Dybcio
1 sibling, 1 reply; 9+ messages in thread
From: Jie Gan @ 2025-11-04 8:10 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel, Jie Gan
Embedded Trace Router(ETR) is working as a DDR memory sink to collect
tracing data from source device.
The CTCU serves as the control unit for the ETR device, managing its
behavior to determine how trace data is collected.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++++++++++-
1 file changed, 159 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index a17900eacb20..ca4a473614ee 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -6713,6 +6713,35 @@ data-pins {
};
};
+ ctcu@10001000 {
+ compatible = "qcom,hamoa-ctcu","qcom,sa8775p-ctcu";
+ reg = <0x0 0x10001000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ ctcu_in0: endpoint {
+ remote-endpoint = <&etr0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ctcu_in1: endpoint {
+ remote-endpoint = <&etr1_out>;
+ };
+ };
+ };
+ };
+
stm@10002000 {
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x0 0x10002000 0x0 0x1000>,
@@ -6927,6 +6956,122 @@ qdss_funnel_out: endpoint {
};
};
+ replicator@10046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x10046000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ qdss_rep_in: endpoint {
+ remote-endpoint = <&swao_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ qdss_rep_out0: endpoint {
+ remote-endpoint = <&etr_rep_in>;
+ };
+ };
+ };
+ };
+
+ tmc_etr: tmc@10048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x10048000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x04e0 0x0>;
+
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr0_in: endpoint {
+ remote-endpoint = <&etr_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr0_out: endpoint {
+ remote-endpoint = <&ctcu_in0>;
+ };
+ };
+ };
+ };
+
+ replicator@1004e000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x0 0x1004e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ etr_rep_in: endpoint {
+ remote-endpoint = <&qdss_rep_out0>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ etr_rep_out0: endpoint {
+ remote-endpoint = <&etr0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ etr_rep_out1: endpoint {
+ remote-endpoint = <&etr1_in>;
+ };
+ };
+ };
+ };
+
+ tmc_etr1: tmc@1004f000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x1004f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ iommus = <&apps_smmu 0x0500 0x0>;
+
+ arm,scatter-gather;
+ arm,buffer-size = <0x400000>;
+
+ in-ports {
+ port {
+ etr1_in: endpoint {
+ remote-endpoint = <&etr_rep_out1>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etr1_out: endpoint {
+ remote-endpoint = <&ctcu_in1>;
+ };
+ };
+ };
+ };
+
tpdm@10800000 {
compatible = "qcom,coresight-tpdm", "arm,primecell";
reg = <0x0 0x10800000 0x0 0x1000>;
@@ -7240,7 +7385,20 @@ swao_rep_in: endpoint {
};
out-ports {
- port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ swao_rep_out0: endpoint {
+ remote-endpoint = <&qdss_rep_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
swao_rep_out1: endpoint {
remote-endpoint = <&eud_in>;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices
2025-11-04 8:10 ` [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices Jie Gan
@ 2025-11-04 12:47 ` Konrad Dybcio
2025-11-05 1:14 ` Jie Gan
0 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2025-11-04 12:47 UTC (permalink / raw)
To: Jie Gan, Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel
On 11/4/25 9:10 AM, Jie Gan wrote:
> Embedded Trace Router(ETR) is working as a DDR memory sink to collect
> tracing data from source device.
>
> The CTCU serves as the control unit for the ETR device, managing its
> behavior to determine how trace data is collected.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++++++++++-
> 1 file changed, 159 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> index a17900eacb20..ca4a473614ee 100644
> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
> @@ -6713,6 +6713,35 @@ data-pins {
> };
> };
>
> + ctcu@10001000 {
> + compatible = "qcom,hamoa-ctcu","qcom,sa8775p-ctcu";
Missing space between after the comma
no issues otherwise
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices
2025-11-04 12:47 ` Konrad Dybcio
@ 2025-11-05 1:14 ` Jie Gan
2025-11-05 9:09 ` Konrad Dybcio
0 siblings, 1 reply; 9+ messages in thread
From: Jie Gan @ 2025-11-05 1:14 UTC (permalink / raw)
To: Konrad Dybcio, Suzuki K Poulose, Mike Leach, James Clark,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel
On 11/4/2025 8:47 PM, Konrad Dybcio wrote:
> On 11/4/25 9:10 AM, Jie Gan wrote:
>> Embedded Trace Router(ETR) is working as a DDR memory sink to collect
>> tracing data from source device.
>>
>> The CTCU serves as the control unit for the ETR device, managing its
>> behavior to determine how trace data is collected.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++++++++++-
>> 1 file changed, 159 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> index a17900eacb20..ca4a473614ee 100644
>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>> @@ -6713,6 +6713,35 @@ data-pins {
>> };
>> };
>>
>> + ctcu@10001000 {
>> + compatible = "qcom,hamoa-ctcu","qcom,sa8775p-ctcu";
>
> Missing space between after the comma
>
> no issues otherwise
sorry for the mistake. Do I need send a new version to fix it?
Thanks,
Jie
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>
> Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] dt-binding: arm: add CTCU device for hamoa
2025-11-04 8:10 ` [PATCH 1/2] dt-binding: arm: add " Jie Gan
@ 2025-11-05 8:59 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-05 8:59 UTC (permalink / raw)
To: Jie Gan
Cc: Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, coresight,
linux-arm-kernel, devicetree, linux-kernel
On Tue, Nov 04, 2025 at 04:10:17PM +0800, Jie Gan wrote:
> Document the CTCU compatible for Hamoa, enabling support for the
> CTCU device on the Hamoa platform.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index 460f38ddbd73..57dede7a90e9 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -29,6 +29,7 @@ properties:
> oneOf:
> - items:
> - enum:
> + - qcom,hamoa-ctcu
There is no such hunk. Dependency should be noted here, anyway, this
cannot be tested by tooling so no review. Please be sure your patches
can be actually tested.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices
2025-11-05 1:14 ` Jie Gan
@ 2025-11-05 9:09 ` Konrad Dybcio
2025-11-05 9:17 ` Krzysztof Kozlowski
0 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2025-11-05 9:09 UTC (permalink / raw)
To: Jie Gan, Suzuki K Poulose, Mike Leach, James Clark, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang, Mao Jinlong,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel
On 11/5/25 2:14 AM, Jie Gan wrote:
>
>
> On 11/4/2025 8:47 PM, Konrad Dybcio wrote:
>> On 11/4/25 9:10 AM, Jie Gan wrote:
>>> Embedded Trace Router(ETR) is working as a DDR memory sink to collect
>>> tracing data from source device.
>>>
>>> The CTCU serves as the control unit for the ETR device, managing its
>>> behavior to determine how trace data is collected.
>>>
>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++++++++++-
>>> 1 file changed, 159 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>> index a17900eacb20..ca4a473614ee 100644
>>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>> @@ -6713,6 +6713,35 @@ data-pins {
>>> };
>>> };
>>> + ctcu@10001000 {
>>> + compatible = "qcom,hamoa-ctcu","qcom,sa8775p-ctcu";
>>
>> Missing space between after the comma
>>
>> no issues otherwise
>
> sorry for the mistake. Do I need send a new version to fix it?
I think you do since Krzysztof made some comments
Konrad
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices
2025-11-05 9:09 ` Konrad Dybcio
@ 2025-11-05 9:17 ` Krzysztof Kozlowski
2025-11-06 1:14 ` Jie Gan
0 siblings, 1 reply; 9+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-05 9:17 UTC (permalink / raw)
To: Konrad Dybcio, Jie Gan, Suzuki K Poulose, Mike Leach, James Clark,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang,
Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel
On 05/11/2025 10:09, Konrad Dybcio wrote:
> On 11/5/25 2:14 AM, Jie Gan wrote:
>>
>>
>> On 11/4/2025 8:47 PM, Konrad Dybcio wrote:
>>> On 11/4/25 9:10 AM, Jie Gan wrote:
>>>> Embedded Trace Router(ETR) is working as a DDR memory sink to collect
>>>> tracing data from source device.
>>>>
>>>> The CTCU serves as the control unit for the ETR device, managing its
>>>> behavior to determine how trace data is collected.
>>>>
>>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++++++++++-
>>>> 1 file changed, 159 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> index a17900eacb20..ca4a473614ee 100644
>>>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>> @@ -6713,6 +6713,35 @@ data-pins {
>>>> };
>>>> };
>>>> + ctcu@10001000 {
>>>> + compatible = "qcom,hamoa-ctcu","qcom,sa8775p-ctcu";
>>>
>>> Missing space between after the comma
>>>
>>> no issues otherwise
>>
>> sorry for the mistake. Do I need send a new version to fix it?
>
> I think you do since Krzysztof made some comments
Not a technical ones, but about the process.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices
2025-11-05 9:17 ` Krzysztof Kozlowski
@ 2025-11-06 1:14 ` Jie Gan
0 siblings, 0 replies; 9+ messages in thread
From: Jie Gan @ 2025-11-06 1:14 UTC (permalink / raw)
To: Krzysztof Kozlowski, Konrad Dybcio, Suzuki K Poulose, Mike Leach,
James Clark, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Tingwei Zhang, Mao Jinlong, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, coresight, linux-arm-kernel, devicetree,
linux-kernel
On 11/5/2025 5:17 PM, Krzysztof Kozlowski wrote:
> On 05/11/2025 10:09, Konrad Dybcio wrote:
>> On 11/5/25 2:14 AM, Jie Gan wrote:
>>>
>>>
>>> On 11/4/2025 8:47 PM, Konrad Dybcio wrote:
>>>> On 11/4/25 9:10 AM, Jie Gan wrote:
>>>>> Embedded Trace Router(ETR) is working as a DDR memory sink to collect
>>>>> tracing data from source device.
>>>>>
>>>>> The CTCU serves as the control unit for the ETR device, managing its
>>>>> behavior to determine how trace data is collected.
>>>>>
>>>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/hamoa.dtsi | 160 +++++++++++++++++++++++++++++++++++-
>>>>> 1 file changed, 159 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>>> index a17900eacb20..ca4a473614ee 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
>>>>> @@ -6713,6 +6713,35 @@ data-pins {
>>>>> };
>>>>> };
>>>>> + ctcu@10001000 {
>>>>> + compatible = "qcom,hamoa-ctcu","qcom,sa8775p-ctcu";
>>>>
>>>> Missing space between after the comma
>>>>
>>>> no issues otherwise
>>>
>>> sorry for the mistake. Do I need send a new version to fix it?
>>
>> I think you do since Krzysztof made some comments
>
>
> Not a technical ones, but about the process.
will send a new version to address all comments.
Thanks,
Jie
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2025-11-06 1:15 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2025-11-04 8:10 [PATCH 0/2] Enable ETR and CTCU device for hamoa Jie Gan
2025-11-04 8:10 ` [PATCH 1/2] dt-binding: arm: add " Jie Gan
2025-11-05 8:59 ` Krzysztof Kozlowski
2025-11-04 8:10 ` [PATCH 2/2] arm64: dts: qcom: hamoa: enable ETR and CTCU devices Jie Gan
2025-11-04 12:47 ` Konrad Dybcio
2025-11-05 1:14 ` Jie Gan
2025-11-05 9:09 ` Konrad Dybcio
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