From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4D9E2DC332 for ; Tue, 4 Nov 2025 06:42:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762238535; cv=none; b=CHHf5wm0/7Y9fMR/oJ0Jy06S+XWLAd2i+P+RUHfzj5+Lcw/ANMjW1kpUecqx35jmYPqNlPYl6nnIT3C77o2wOr0Zj0I7F9PYeCtHkUiCKA9Ki2LX5qxmOth7N60YCUiPtP8lzH8CedhvYqdoj7fGOv0G+DsmG/wwp0uuFUVToFk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762238535; c=relaxed/simple; bh=OPlgz5dQx2tfW9c2Sve/gGeYnzGFQMRsvIxlcSMDM20=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=BMuBzhHMLTkibk0ksxnD4QZ5ofnM2ahyiIK2SbloP3qBPr5aaH17fa63Jf54lXuKRg2gdLwGFzqrXEJLYHp4l3R7HWmlIUceLsh3A6RhARIhnOPfWrvA1aqYm99x99hA9bmcwLv6vqojKDruukuFBRXCEFMHgJRWL4wKCoJHjZY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=MsTFuudg; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=dmClm156; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="MsTFuudg"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="dmClm156" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 5A46QP851192048 for ; Tue, 4 Nov 2025 06:42:13 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=2RO8fIpOHfq mxM+0mgaFLjsUaSf8VFX1gHKMlkhde3Y=; b=MsTFuudgKWhkeEo2ZvbTQPqtRnY VM9MHxR2CJ0askIQnK59Slb0LrjMg2l/tyjEsNZm6FTFDTMkfgkQ2PHVjOc2Ex1m BQWLMU5YPgwHpXnvuVGH1IIjdXn6O/+pVfDg2RZeFntR53g04D/WAekH6qZ46wmQ WFyoxG9HVr4TMwHbRUZmapa9lA0HyzgoqntpqgPcycPokExACmm4sl7YJaU6PhFc 457HxaPk6Oo7GpvamATy72Prb6bGY82di//AF7N4LiRci5xzTIxNNrcpUKSxvccT 57ELM8sZQQI9a8L0i7nuWKoE1xL6RZBgdHdEbTi7hlQ0/3C/UH5ZR2lJyjA== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4a7c7jg1g9-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 04 Nov 2025 06:42:12 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-295b713530cso23857915ad.1 for ; Mon, 03 Nov 2025 22:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1762238532; x=1762843332; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2RO8fIpOHfqmxM+0mgaFLjsUaSf8VFX1gHKMlkhde3Y=; b=dmClm156zc0bYkWdIrJxU46OeYhuTRG2gF+7kxC0qEghY+0lEzMPUjtJ0j116G0wfb nAKH2Jv7CuEE1Bm0MNiBNiBUX6G1pgSKgzaZ16iFQOYxvOY2ijIXgdSY/hPSbo1JvCNu ZhuRM+WV9V3VqfPlgTqCs5YzcPWxZN2Fby/1eJpaoIt9QSI0CNHKPv4Q9tdLDuuJvytD Kwu+RS38aJ3JpsJ8zbhy6wAtQKPIRG6odqMBnkSVPo1I7WYeDwuZmMxACEnOILUylevv ENjit9Sz3yDam/j42alIiXOcRj5gE6fOF2dKmYDNJjqYWqq4LCwq+bfEEyuajjyTFH/7 6KYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762238532; x=1762843332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2RO8fIpOHfqmxM+0mgaFLjsUaSf8VFX1gHKMlkhde3Y=; b=bd2KoVfeCym6tEfKspvWuwVadcqI5aFTUItinObzow+XThvik/fbxrZiFsZ7Vfpx00 sr7AV2nDPy0A+a2JEe+EDQDFfAXHkubpizBwJFD5K532I6KWB3Y10AHCAwyfzqciXkSi VGx2uX0jlqk3aPTO/BMEzXlXQ9SxauUOzIr06tCuHNnPWr0/521zohqyqclvz8EzUkJv 62QAgPKCGEP7kFmbwBeQbkr/9wy+ztiKM6AKZ80/uxt0vcVT3FytjKWy6JsJeioUH3+a Fh1yhirbnR1Y8pWcSujGxkc5M/t3cN2yeyij56yG198MlZx1kmDQpbvDqmeYndRtCfTA 65vg== X-Forwarded-Encrypted: i=1; AJvYcCWnVHrBJQBtVns1Fq8o8ymh+YOKtOlPv2fXhgebaLjzM1pc1N8+WUSnP3Eh8baRPqkA4cIXh7J9Nixs@vger.kernel.org X-Gm-Message-State: AOJu0YwtpEkKc+6JxiEPwCJaA9qZS6z/FiahECoGGiEfR8XohlA7AtrM fd0a2hYXUEly4CFaDxFKKg9RY5R4X61/U9rqELe0X+8GnmzRhh+Z9fk9VZiczQiW68R3g26RvEN U77MDFqvWT+taDFFSxvfUrfKAhFJxSacg8gyillTTsOp0dWtdk6CPbm8yUTc4aA3f X-Gm-Gg: ASbGnctBk/RfcrKQLJFaouxR0lSP+i6np976BdzIdvc/zKrDrfyOjYupy7OZSbC9NtS 4iJfdaBabNefIp8RYG2Kn9GuHRS1M0nKYk4vF0YiHk51bR73y7D6WcASizLWAAi6zOwaEisTzYp tNXWivnvENVo0u2lCyy8uVKvrcxOIIapUNrQ1j7IS88QqEnzhcINQzpMA+PKKT4zsdHCofYFzv5 mhpDkuurycmp4qHpXtBR1t+jO3KDb69/eCwdUVsw/LJaArGd81podgSl69WW9EvFm+7A/Z4KMYh Da+P1qEjA6xnRR1LxD+6qIRlkyjsQVlxLlSvAAq7VCBS3SaQQ57BLv2W4ynVVLuPXZNMqKYPIUL dnY2RMlJ+OjIrj7MXKoYlJeEd+opYF9NOHoq59XWBDhegnHPSweG2yw== X-Received: by 2002:a17:90b:3fc6:b0:340:ca32:bcad with SMTP id 98e67ed59e1d1-340ca32bdadmr11870453a91.19.1762238531702; Mon, 03 Nov 2025 22:42:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IGaDGJ5kHqXdsHNG3Ni7vTzkdk26k/VRa7ZAhaz4muWnIrhrMWUOVIJK8FEKySBHz5CIyXpYg== X-Received: by 2002:a17:90b:3fc6:b0:340:ca32:bcad with SMTP id 98e67ed59e1d1-340ca32bdadmr11870429a91.19.1762238531103; Mon, 03 Nov 2025 22:42:11 -0800 (PST) Received: from hu-songchai-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34159a0780dsm3294791a91.16.2025.11.03.22.42.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Nov 2025 22:42:10 -0800 (PST) From: Songwei Chai To: andersson@kernel.org, alexander.shishkin@linux.intel.com, kernel@oss.qualcomm.com, mike.leach@linaro.org, suzuki.poulose@arm.com Cc: Songwei Chai , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, devicetree@vger.kernel.org Subject: [PATCH v7 3/7] qcom-tgu: Add signal priority support Date: Mon, 3 Nov 2025 22:40:39 -0800 Message-Id: <20251104064043.88972-4-songwei.chai@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251104064043.88972-1-songwei.chai@oss.qualcomm.com> References: <20251104064043.88972-1-songwei.chai@oss.qualcomm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTA0MDA1MyBTYWx0ZWRfXwVAG+6c3optt 256ghxJi58hdZ723w//RQ98fhI8CJOxt9+YuHwenBUJn2KCr4yKh8OcvKUUSzPPHrBog36mtxWf Kaa9kuR7w/wnoCeiZfYZzt8ImZNjjbdIsMgD0XFKU4ttCKV4l8roTdJxwMWQduvOGFRv5/d73/G WghvbkTpNvhhFjfaP/rBRKEgWduSjpYjj6dDT70S6cZWZq4+vSWltojicQCN3ksOnsRabuVOBBx oxDPNZUytUXnlf0BC9ZFB3cR/YgKfXaGQbsXlxYaRW3UTQLzt/pmFEln/5a0T0uZ1emlCY4vXag Vn/avvHx2Aanpy9+GT9fJCQBCTkMafTU4WTjAjSLwi+RpX+keUPQmElGUODz2hlSlyMzbyfKpIZ z+Jiz9bCGkydQWsEo7DGncZR+UbZgw== X-Proofpoint-ORIG-GUID: 49C_oMRqvOvV1wLFHztY1L1v3oAtmzZK X-Proofpoint-GUID: 49C_oMRqvOvV1wLFHztY1L1v3oAtmzZK X-Authority-Analysis: v=2.4 cv=DvNbOW/+ c=1 sm=1 tr=0 ts=6909a044 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=HMmvC-cB1bDe2h_eLOYA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-03_06,2025-11-03_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 malwarescore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511040053 Like circuit of a Logic analyzer, in TGU, the requirement could be configured in each step and the trigger will be created once the requirements are met. Add priority functionality here to sort the signals into different priorities. The signal which is wanted could be configured in each step's priority node, the larger number means the higher priority and the signal with higher priority will be sensed more preferentially. Signed-off-by: Songwei Chai --- .../testing/sysfs-bus-coresight-devices-tgu | 7 + drivers/hwtracing/qcom/tgu.c | 155 ++++++++++++++++++ drivers/hwtracing/qcom/tgu.h | 111 +++++++++++++ 3 files changed, 273 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu index 17d8449599a1..082fddac9ff0 100644 --- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu @@ -7,3 +7,10 @@ Description: Accepts only one of the 2 values - 0 or 1. 0 : disable TGU. 1 : enable TGU. + +What: /sys/bus/coresight/devices//step[0:7]_priority[0:3]/reg[0:17] +Date: November 2025 +KernelVersion 6.18 +Contact: Jinlong Mao , Songwei Chai +Description: + (RW) Set/Get the sensed signal with specific step and priority for TGU. diff --git a/drivers/hwtracing/qcom/tgu.c b/drivers/hwtracing/qcom/tgu.c index 368bb196b984..a1ad8d97e9d2 100644 --- a/drivers/hwtracing/qcom/tgu.c +++ b/drivers/hwtracing/qcom/tgu.c @@ -17,14 +17,120 @@ DEFINE_CORESIGHT_DEVLIST(tgu_devs, "tgu"); +static int calculate_array_location(struct tgu_drvdata *drvdata, + int step_index, int operation_index, + int reg_index) +{ + return operation_index * (drvdata->max_step) * (drvdata->max_reg) + + step_index * (drvdata->max_reg) + reg_index; +} + +static ssize_t tgu_dataset_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int index; + struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent); + struct tgu_attribute *tgu_attr = + container_of(attr, struct tgu_attribute, attr); + + index = calculate_array_location(drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + return sysfs_emit(buf, "0x%x\n", + drvdata->value_table->priority[index]); +} + +static ssize_t tgu_dataset_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int index; + unsigned long val; + + struct tgu_drvdata *tgu_drvdata = dev_get_drvdata(dev->parent); + struct tgu_attribute *tgu_attr = + container_of(attr, struct tgu_attribute, attr); + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(spinlock)(&tgu_drvdata->lock); + index = calculate_array_location(tgu_drvdata, tgu_attr->step_index, + tgu_attr->operation_index, + tgu_attr->reg_num); + + tgu_drvdata->value_table->priority[index] = val; + return size; +} + +static umode_t tgu_node_visible(struct kobject *kobject, + struct attribute *attr, + int n) +{ + struct device *dev = kobj_to_dev(kobject); + struct tgu_drvdata *drvdata = dev_get_drvdata(dev->parent); + int ret = SYSFS_GROUP_INVISIBLE; + + struct device_attribute *dev_attr = + container_of(attr, struct device_attribute, attr); + struct tgu_attribute *tgu_attr = + container_of(dev_attr, struct tgu_attribute, attr); + + if (tgu_attr->step_index < drvdata->max_step) { + ret = (tgu_attr->reg_num < drvdata->max_reg) ? + attr->mode : 0; + } + return ret; +} + static void tgu_write_all_hw_regs(struct tgu_drvdata *drvdata) { + int i, j, k, index; + CS_UNLOCK(drvdata->base); + for (i = 0; i < drvdata->max_step; i++) { + for (j = 0; j < MAX_PRIORITY; j++) { + for (k = 0; k < drvdata->max_reg; k++) { + index = calculate_array_location( + drvdata, i, j, k); + + writel(drvdata->value_table->priority[index], + drvdata->base + + PRIORITY_REG_STEP(i, j, k)); + } + } + } /* Enable TGU to program the triggers */ writel(1, drvdata->base + TGU_CONTROL); CS_LOCK(drvdata->base); } +static void tgu_set_reg_number(struct tgu_drvdata *drvdata) +{ + int num_sense_input; + int num_reg; + u32 devid; + + devid = readl(drvdata->base + CORESIGHT_DEVID); + + num_sense_input = TGU_DEVID_SENSE_INPUT(devid); + if (((num_sense_input * NUMBER_BITS_EACH_SIGNAL) % LENGTH_REGISTER) == 0) + num_reg = (num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTER; + else + num_reg = ((num_sense_input * NUMBER_BITS_EACH_SIGNAL) / LENGTH_REGISTER) + 1; + drvdata->max_reg = num_reg; +} + +static void tgu_set_steps(struct tgu_drvdata *drvdata) +{ + u32 devid; + + devid = readl(drvdata->base + CORESIGHT_DEVID); + + drvdata->max_step = TGU_DEVID_STEPS(devid); +} + static int tgu_enable(struct coresight_device *csdev, enum cs_mode mode, void *data) { @@ -122,6 +228,38 @@ static const struct attribute_group tgu_common_grp = { static const struct attribute_group *tgu_attr_groups[] = { &tgu_common_grp, + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(0, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(1, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(2, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(3, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(4, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(5, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(6, 3), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 0), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 1), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 2), + PRIORITY_ATTRIBUTE_GROUP_INIT(7, 3), NULL, }; @@ -156,6 +294,23 @@ static int tgu_probe(struct amba_device *adev, const struct amba_id *id) spin_lock_init(&drvdata->lock); + tgu_set_reg_number(drvdata); + tgu_set_steps(drvdata); + + drvdata->value_table = + devm_kzalloc(dev, sizeof(*drvdata->value_table), GFP_KERNEL); + if (!drvdata->value_table) + return -ENOMEM; + + drvdata->value_table->priority = devm_kzalloc( + dev, + MAX_PRIORITY * drvdata->max_reg * drvdata->max_step * + sizeof(*(drvdata->value_table->priority)), + GFP_KERNEL); + + if (!drvdata->value_table->priority) + return -ENOMEM; + drvdata->enable = false; desc.type = CORESIGHT_DEV_TYPE_HELPER; desc.pdata = adev->dev.platform_data; diff --git a/drivers/hwtracing/qcom/tgu.h b/drivers/hwtracing/qcom/tgu.h index 1a55da90f521..444804e52337 100644 --- a/drivers/hwtracing/qcom/tgu.h +++ b/drivers/hwtracing/qcom/tgu.h @@ -9,6 +9,111 @@ /* Register addresses */ #define TGU_CONTROL 0x0000 +#define TGU_DEVID_SENSE_INPUT(devid_val) ((int) BMVAL(devid_val, 10, 17)) +#define TGU_DEVID_STEPS(devid_val) ((int)BMVAL(devid_val, 3, 6)) +#define NUMBER_BITS_EACH_SIGNAL 4 +#define LENGTH_REGISTER 32 + +/* + * TGU configuration space Step configuration + * offset table space layout + * x-------------------------x$ x-------------x$ + * | |$ | |$ + * | | | reserve |$ + * | | | |$ + * |coresight management | |-------------|base+n*0x1D8+0x1F4$ + * | registe | |---> |prioroty[3] |$ + * | | | |-------------|base+n*0x1D8+0x194$ + * | | | |prioroty[2] |$ + * |-------------------------| | |-------------|base+n*0x1D8+0x134$ + * | | | |prioroty[1] |$ + * | step[7] | | |-------------|base+n*0x1D8+0xD4$ + * |-------------------------|->base+0x40+7*0x1D8 | |prioroty[0] |$ + * | | | |-------------|base+n*0x1D8+0x74$ + * | ... | | | condition |$ + * | | | | select |$ + * |-------------------------|->base+0x40+1*0x1D8 | |-------------|base+n*0x1D8+0x60$ + * | | | | condition |$ + * | step[0] |--------------------> | decode |$ + * |-------------------------|-> base+0x40 |-------------|base+n*0x1D8+0x50$ + * | | | |$ + * | Control and status space| |Timer/Counter|$ + * | space | | |$ + * x-------------------------x->base x-------------x base+n*0x1D8+0x40$ + * + */ +#define STEP_OFFSET 0x1D8 +#define PRIORITY_START_OFFSET 0x0074 +#define PRIORITY_OFFSET 0x60 +#define REG_OFFSET 0x4 + +/* Calculate compare step addresses */ +#define PRIORITY_REG_STEP(step, priority, reg)\ + (PRIORITY_START_OFFSET + PRIORITY_OFFSET * priority +\ + REG_OFFSET * reg + STEP_OFFSET * step) + +#define tgu_dataset_rw(name, step_index, type, reg_num) \ + (&((struct tgu_attribute[]){ { \ + __ATTR(name, 0644, tgu_dataset_show, tgu_dataset_store), \ + step_index, \ + type, \ + reg_num, \ + } })[0].attr.attr) + +#define STEP_PRIORITY(step_index, reg_num, priority) \ + tgu_dataset_rw(reg##reg_num, step_index, TGU_PRIORITY##priority, \ + reg_num) + +#define STEP_PRIORITY_LIST(step_index, priority) \ + {STEP_PRIORITY(step_index, 0, priority), \ + STEP_PRIORITY(step_index, 1, priority), \ + STEP_PRIORITY(step_index, 2, priority), \ + STEP_PRIORITY(step_index, 3, priority), \ + STEP_PRIORITY(step_index, 4, priority), \ + STEP_PRIORITY(step_index, 5, priority), \ + STEP_PRIORITY(step_index, 6, priority), \ + STEP_PRIORITY(step_index, 7, priority), \ + STEP_PRIORITY(step_index, 8, priority), \ + STEP_PRIORITY(step_index, 9, priority), \ + STEP_PRIORITY(step_index, 10, priority), \ + STEP_PRIORITY(step_index, 11, priority), \ + STEP_PRIORITY(step_index, 12, priority), \ + STEP_PRIORITY(step_index, 13, priority), \ + STEP_PRIORITY(step_index, 14, priority), \ + STEP_PRIORITY(step_index, 15, priority), \ + STEP_PRIORITY(step_index, 16, priority), \ + STEP_PRIORITY(step_index, 17, priority), \ + NULL \ + } + +#define PRIORITY_ATTRIBUTE_GROUP_INIT(step, priority)\ + (&(const struct attribute_group){\ + .attrs = (struct attribute*[])STEP_PRIORITY_LIST(step, priority),\ + .is_visible = tgu_node_visible,\ + .name = "step" #step "_priority" #priority \ + }) + +enum operation_index { + TGU_PRIORITY0, + TGU_PRIORITY1, + TGU_PRIORITY2, + TGU_PRIORITY3, +}; + +/* Maximum priority that TGU supports */ +#define MAX_PRIORITY 4 + +struct tgu_attribute { + struct device_attribute attr; + u32 step_index; + enum operation_index operation_index; + u32 reg_num; +}; + +struct value_table { + unsigned int *priority; +}; + /** * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) * @base: Memory-mapped base address of the TGU device @@ -16,6 +121,9 @@ * @csdev: Pointer to the associated coresight device * @lock: Spinlock for handling concurrent access * @enable: Flag indicating whether the TGU device is enabled + * @value_table: Store given value based on relevant parameters. + * @max_reg: Maximum number of registers + * @max_step: Maximum step size * * This structure defines the data associated with a TGU device, * including its base address, device pointers, clock, spinlock for @@ -28,6 +136,9 @@ struct tgu_drvdata { struct coresight_device *csdev; spinlock_t lock; bool enable; + struct value_table *value_table; + int max_reg; + int max_step; }; #endif -- 2.34.1