[PATCH v3 0/4] Add RTC support for the Renesas RZ/V2H SoC

[PATCH v3 0/4] Add RTC support for the Renesas RZ/V2H SoC

[Ovidiu Panait]

Hi,

This series adds RTC support for the Renesas RZ/V2H SoC.

The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
(r9a08g045), with the following differences:
- it lacks the time capture functionality
- the maximum supported periodic interrupt frequency is 128Hz instead
  of 256Hz
- it requires two reset lines instead of one

Best regards,
Ovidiu

v3:
- Dropped all changes related to "max_user_freq", as it was removed from
  all drivers by:
  https://lore.kernel.org/all/20251101-max_user_freq-v1-0-c9a274fd6883@bootlin.com/

v2:
- Updated bindings and RTC dts node with "reset-names" property.

Ovidiu Panait (4):
  dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support
  rtc: renesas-rtca3: Add support for multiple reset lines
  arm64: dts: renesas: r9a09g057: Add RTC node
  arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC

 .../bindings/rtc/renesas,rz-rtca3.yaml        | 45 ++++++++++++++++---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    | 15 +++++++
 .../dts/renesas/r9a09g057h44-rzv2h-evk.dts    |  4 ++
 drivers/rtc/rtc-renesas-rtca3.c               |  2 +-
 4 files changed, 60 insertions(+), 6 deletions(-)

-- 
2.51.0

[PATCH v3 1/4] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Ovidiu Panait]

The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
(r9a08g045), with the following differences:
- It lacks the time capture functionality
- The maximum supported periodic interrupt frequency is 128Hz instead
  of 256Hz
- It requires two reset lines instead of one

Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
the binding accordingly:
- Allow "resets" to contain one or two entries depending on the SoC.
- Add "reset-names" property, but make it required only for RZ/V2H.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 .../bindings/rtc/renesas,rz-rtca3.yaml        | 45 ++++++++++++++++---
 1 file changed, 40 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
index e70eeb66aa64..2569cb494481 100644
--- a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
+++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml
@@ -9,14 +9,12 @@ title: Renesas RTCA-3 Real Time Clock
 maintainers:
   - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
 
-allOf:
-  - $ref: rtc.yaml#
-
 properties:
   compatible:
     items:
       - enum:
           - renesas,r9a08g045-rtca3 # RZ/G3S
+          - renesas,r9a09g057-rtca3 # RZ/V2H
       - const: renesas,rz-rtca3
 
   reg:
@@ -48,8 +46,12 @@ properties:
     maxItems: 1
 
   resets:
-    items:
-      - description: VBATTB module reset
+    minItems: 1
+    maxItems: 2
+
+  reset-names:
+    minItems: 1
+    maxItems: 2
 
 required:
   - compatible
@@ -61,6 +63,39 @@ required:
   - power-domains
   - resets
 
+allOf:
+  - $ref: rtc.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a08g045-rtca3
+    then:
+      properties:
+        resets:
+          items:
+            - description: VBATTB module reset
+        reset-names:
+          const: vbattb
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a09g057-rtca3
+    then:
+      properties:
+        resets:
+          items:
+            - description: RTC reset
+            - description: Reset for the RTEST registers
+        reset-names:
+          items:
+            - const: rtc
+            - const: rtc_rtest
+      required:
+        - reset-names
+
 additionalProperties: false
 
 examples:
-- 
2.51.0

[PATCH v3 2/4] rtc: renesas-rtca3: Add support for multiple reset lines

[Ovidiu Panait]

Switch from devm_reset_control_get_shared() to
devm_reset_control_array_get_shared() when retrieving resets.

The RZ/V2H SoC requires two resets for the RTC block instead of one,
so this will allow to handle multiple resets without additional changes.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 drivers/rtc/rtc-renesas-rtca3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/rtc/rtc-renesas-rtca3.c b/drivers/rtc/rtc-renesas-rtca3.c
index ab816bdf0d77..3524053269ef 100644
--- a/drivers/rtc/rtc-renesas-rtca3.c
+++ b/drivers/rtc/rtc-renesas-rtca3.c
@@ -726,7 +726,7 @@ static int rtca3_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	priv->rstc = devm_reset_control_get_shared(dev, NULL);
+	priv->rstc = devm_reset_control_array_get_shared(dev);
 	if (IS_ERR(priv->rstc))
 		return PTR_ERR(priv->rstc);
 
-- 
2.51.0

[PATCH v3 3/4] arm64: dts: renesas: r9a09g057: Add RTC node

[Ovidiu Panait]

Add RTC node to Renesas RZ/V2H ("R9A09G057") SoC DTSI.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 40b15f1db930..724c4ce95c95 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -591,6 +591,21 @@ wdt3: watchdog@13000400 {
 			status = "disabled";
 		};
 
+		rtc: rtc@11c00800 {
+			compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3";
+			reg = <0 0x11c00800 0 0x400>;
+			interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>;
+			interrupt-names = "alarm", "period", "carry";
+			clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>;
+			clock-names = "bus", "counter";
+			power-domains = <&cpg>;
+			resets = <&cpg 0x79>, <&cpg 0x7a>;
+			reset-names = "rtc", "rtc_rtest";
+			status = "disabled";
+		};
+
 		scif: serial@11c01400 {
 			compatible = "renesas,scif-r9a09g057";
 			reg = <0 0x11c01400 0 0x400>;
-- 
2.51.0

[PATCH v3 4/4] arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable RTC

[Ovidiu Panait]

Enable RTC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 7fff8bea9494..99dfb40b6ea8 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -407,6 +407,10 @@ &qextal_clk {
 	clock-frequency = <24000000>;
 };
 
+&rtc {
+	status = "okay";
+};
+
 &rtxin_clk {
 	clock-frequency = <32768>;
 };
-- 
2.51.0

Re: (subset) [PATCH v3 0/4] Add RTC support for the Renesas RZ/V2H SoC

[Alexandre Belloni]

On Mon, 03 Nov 2025 12:18:44 +0000, Ovidiu Panait wrote:
> This series adds RTC support for the Renesas RZ/V2H SoC.
> 
> The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> (r9a08g045), with the following differences:
> - it lacks the time capture functionality
> - the maximum supported periodic interrupt frequency is 128Hz instead
>   of 256Hz
> - it requires two reset lines instead of one
> 
> [...]

Applied, thanks!

[1/4] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support
      https://git.kernel.org/abelloni/c/8056f175606a
[2/4] rtc: renesas-rtca3: Add support for multiple reset lines
      https://git.kernel.org/abelloni/c/d034c9ca6a47

Best regards,

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/4] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Conor Dooley]

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On Mon, Nov 03, 2025 at 12:18:45PM +0000, Ovidiu Panait wrote:
> The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> (r9a08g045), with the following differences:
> - It lacks the time capture functionality
> - The maximum supported periodic interrupt frequency is 128Hz instead
>   of 256Hz
> - It requires two reset lines instead of one
> 
> Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
> the binding accordingly:
> - Allow "resets" to contain one or two entries depending on the SoC.
> - Add "reset-names" property, but make it required only for RZ/V2H.
> 
> Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> +        reset-names:
> +          items:
> +            - const: rtc
> +            - const: rtc_rtest

If you respin, just make this second one rtest.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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Re: [PATCH v3 1/4] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Alexandre Belloni]

On 04/11/2025 17:28:27+0000, Conor Dooley wrote:
> On Mon, Nov 03, 2025 at 12:18:45PM +0000, Ovidiu Panait wrote:
> > The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> > (r9a08g045), with the following differences:
> > - It lacks the time capture functionality
> > - The maximum supported periodic interrupt frequency is 128Hz instead
> >   of 256Hz
> > - It requires two reset lines instead of one
> > 
> > Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
> > the binding accordingly:
> > - Allow "resets" to contain one or two entries depending on the SoC.
> > - Add "reset-names" property, but make it required only for RZ/V2H.
> > 
> > Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > +        reset-names:
> > +          items:
> > +            - const: rtc
> > +            - const: rtc_rtest
> 
> If you respin, just make this second one rtest.

I already applied it as it had your ack but I can still change it

> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> pw-bot: not-applicable



-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH v3 1/4] dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2H support

[Conor Dooley]

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On Tue, Nov 04, 2025 at 09:20:49PM +0100, Alexandre Belloni wrote:
> On 04/11/2025 17:28:27+0000, Conor Dooley wrote:
> > On Mon, Nov 03, 2025 at 12:18:45PM +0000, Ovidiu Panait wrote:
> > > The Renesas RZ/V2H RTC IP is based on the same RTCA3 IP as RZ/G3S
> > > (r9a08g045), with the following differences:
> > > - It lacks the time capture functionality
> > > - The maximum supported periodic interrupt frequency is 128Hz instead
> > >   of 256Hz
> > > - It requires two reset lines instead of one
> > > 
> > > Add new compatible string "renesas,r9a09g057-rtca3" for RZ/V2H and update
> > > the binding accordingly:
> > > - Allow "resets" to contain one or two entries depending on the SoC.
> > > - Add "reset-names" property, but make it required only for RZ/V2H.
> > > 
> > > Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
> > > +        reset-names:
> > > +          items:
> > > +            - const: rtc
> > > +            - const: rtc_rtest
> > 
> > If you respin, just make this second one rtest.
> 
> I already applied it as it had your ack but I can still change it

It's fine.

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