[PATCH v2 0/3] arm64: tegra: Add DBB clock to EMC on Tegra264

[PATCH v2 0/3] arm64: tegra: Add DBB clock to EMC on Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Hi,

Tegra264 requires the DBB clock to be enabled anytime an IP block needs
to access external memory. The external memory controller is the right
place to put this logic. This short series of patches adds the DBB clock
to the bindings, adds code to the driver to use that clock and finally
passes the clock into the EMC so that it can be used.

Thierry

Thierry Reding (3):
  dt-bindings: memory: tegra: Document DBB clock for Tegra264
  memory: tegra: Add support for DBB clock on Tegra264
  arm64: tegra: Add DBB clock to EMC on Tegra264

 .../memory-controllers/nvidia,tegra186-mc.yaml      | 13 +++++++++++++
 arch/arm64/boot/dts/nvidia/tegra264.dtsi            |  5 +++--
 drivers/memory/tegra/tegra186-emc.c                 |  8 ++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)

-- 
2.51.2

[PATCH v2 1/3] dt-bindings: memory: tegra: Document DBB clock for Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Accesses to external memory are routed through the data backbone (DBB)
on Tegra264. A separate clock feeds this path and needs to be enabled
whenever an IP block makes an access to external memory. The external
memory controller driver is the best place to control this clock since
it knows how many devices are actively accessing memory.

Document the presence of this clock on Tegra264 only.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
Changes in v2:
- add minItems to clocks and clock-names properties

 .../memory-controllers/nvidia,tegra186-mc.yaml      | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index b901f1b3e0fc..7b03b589168b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -92,10 +92,14 @@ patternProperties:
       clocks:
         items:
           - description: external memory clock
+          - description: data backbone clock
+        minItems: 1
 
       clock-names:
         items:
           - const: emc
+          - const: dbb
+        minItems: 1
 
       "#interconnect-cells":
         const: 0
@@ -115,6 +119,9 @@ patternProperties:
             reg:
               maxItems: 1
 
+            clocks:
+              maxItems: 1
+
       - if:
           properties:
             compatible:
@@ -124,6 +131,9 @@ patternProperties:
             reg:
               minItems: 2
 
+            clocks:
+              maxItems: 1
+
       - if:
           properties:
             compatible:
@@ -133,6 +143,9 @@ patternProperties:
             reg:
               minItems: 2
 
+            clocks:
+              maxItems: 1
+
       - if:
           properties:
             compatible:
-- 
2.51.2

Re: [PATCH v2 1/3] dt-bindings: memory: tegra: Document DBB clock for Tegra264

[Rob Herring (Arm)]

On Wed, 05 Nov 2025 20:53:40 +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Accesses to external memory are routed through the data backbone (DBB)
> on Tegra264. A separate clock feeds this path and needs to be enabled
> whenever an IP block makes an access to external memory. The external
> memory controller driver is the best place to control this clock since
> it knows how many devices are actively accessing memory.
> 
> Document the presence of this clock on Tegra264 only.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> Changes in v2:
> - add minItems to clocks and clock-names properties
> 
>  .../memory-controllers/nvidia,tegra186-mc.yaml      | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 2/3] memory: tegra: Add support for DBB clock on Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The DBB clock is needed by many IP blocks in order to access system
memory via the data backbone. The memory controller and external memory
controllers are the central place where these accesses are managed, so
make sure that the clock can be controlled from the corresponding
driver.

Note that not all drivers fully register bandwidth requests, and hence
the EMC driver doesn't have enough information to know when it's safe to
switch the clock off, so for now it will be kept on permanently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/memory/tegra/tegra186-emc.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c
index 74be09968baa..7a26d8830172 100644
--- a/drivers/memory/tegra/tegra186-emc.c
+++ b/drivers/memory/tegra/tegra186-emc.c
@@ -33,6 +33,7 @@ struct tegra186_emc {
 	struct tegra_bpmp *bpmp;
 	struct device *dev;
 	struct clk *clk;
+	struct clk *clk_dbb;
 
 	struct tegra186_emc_dvfs *dvfs;
 	unsigned int num_dvfs;
@@ -452,6 +453,13 @@ static int tegra186_emc_probe(struct platform_device *pdev)
 		return dev_err_probe(&pdev->dev, PTR_ERR(emc->clk),
 				     "failed to get EMC clock\n");
 
+	emc->clk_dbb = devm_clk_get_optional_enabled(&pdev->dev, "dbb");
+	if (IS_ERR(emc->clk_dbb)) {
+		err = PTR_ERR(emc->clk_dbb);
+		dev_err(&pdev->dev, "failed to get DBB clock: %d\n", err);
+		goto put_bpmp;
+	}
+
 	platform_set_drvdata(pdev, emc);
 	emc->dev = &pdev->dev;
 
-- 
2.51.2

Re: [PATCH v2 2/3] memory: tegra: Add support for DBB clock on Tegra264

[Krzysztof Kozlowski]

On 05/11/2025 20:53, Thierry Reding wrote:

> 
> diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c
> index 74be09968baa..7a26d8830172 100644
> --- a/drivers/memory/tegra/tegra186-emc.c
> +++ b/drivers/memory/tegra/tegra186-emc.c
> @@ -33,6 +33,7 @@ struct tegra186_emc {
>  	struct tegra_bpmp *bpmp;
>  	struct device *dev;
>  	struct clk *clk;
> +	struct clk *clk_dbb;
>  
>  	struct tegra186_emc_dvfs *dvfs;
>  	unsigned int num_dvfs;
> @@ -452,6 +453,13 @@ static int tegra186_emc_probe(struct platform_device *pdev)
>  		return dev_err_probe(&pdev->dev, PTR_ERR(emc->clk),
>  				     "failed to get EMC clock\n");
>  
> +	emc->clk_dbb = devm_clk_get_optional_enabled(&pdev->dev, "dbb");
> +	if (IS_ERR(emc->clk_dbb)) {
> +		err = PTR_ERR(emc->clk_dbb);
> +		dev_err(&pdev->dev, "failed to get DBB clock: %d\n", err);

Entire code was converted to dev_err_probe, see other clk_get() and
similar in the driver. Please switch to that syntax, so dropping earlier
line with assignment and printing 'err' in printk.



Best regards,
Krzysztof

[PATCH v2 3/3] arm64: tegra: Add DBB clock to EMC on Tegra264

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The DBB clock is used by the EMC to enable the data path from various IP
blocks to external memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra264.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index c66ea12ef5a3..f1cf370f6363 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3444,8 +3444,9 @@ emc: external-memory-controller@8800000 {
 				reg = <0x00 0x8800000 0x0 0x20000>,
 				      <0x00 0x8890000 0x0 0x20000>;
 				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&bpmp TEGRA264_CLK_EMC>;
-				clock-names = "emc";
+				clocks = <&bpmp TEGRA264_CLK_EMC>,
+					 <&bpmp TEGRA264_CLK_DBB_UPHY0>;
+				clock-names = "emc", "dbb";
 
 				#interconnect-cells = <0>;
 				nvidia,bpmp = <&bpmp>;
-- 
2.51.2