From: Thierry Reding <thierry.reding@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Krzysztof Kozlowski <krzk@kernel.org>
Cc: Rob Herring <robh@kernel.org>, Conor Dooley <conor+dt@kernel.org>,
Jon Hunter <jonathanh@nvidia.com>,
linux-tegra@vger.kernel.org, devicetree@vger.kernel.org
Subject: [PATCH v2 3/3] arm64: tegra: Add DBB clock to EMC on Tegra264
Date: Wed, 5 Nov 2025 20:53:42 +0100 [thread overview]
Message-ID: <20251105195342.2705855-4-thierry.reding@gmail.com> (raw)
In-Reply-To: <20251105195342.2705855-1-thierry.reding@gmail.com>
From: Thierry Reding <treding@nvidia.com>
The DBB clock is used by the EMC to enable the data path from various IP
blocks to external memory.
Signed-off-by: Thierry Reding <treding@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index c66ea12ef5a3..f1cf370f6363 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3444,8 +3444,9 @@ emc: external-memory-controller@8800000 {
reg = <0x00 0x8800000 0x0 0x20000>,
<0x00 0x8890000 0x0 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bpmp TEGRA264_CLK_EMC>;
- clock-names = "emc";
+ clocks = <&bpmp TEGRA264_CLK_EMC>,
+ <&bpmp TEGRA264_CLK_DBB_UPHY0>;
+ clock-names = "emc", "dbb";
#interconnect-cells = <0>;
nvidia,bpmp = <&bpmp>;
--
2.51.2
prev parent reply other threads:[~2025-11-05 19:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-05 19:53 [PATCH v2 0/3] arm64: tegra: Add DBB clock to EMC on Tegra264 Thierry Reding
2025-11-05 19:53 ` [PATCH v2 1/3] dt-bindings: memory: tegra: Document DBB clock for Tegra264 Thierry Reding
2025-11-14 18:21 ` Rob Herring (Arm)
2025-11-05 19:53 ` [PATCH v2 2/3] memory: tegra: Add support for DBB clock on Tegra264 Thierry Reding
2025-11-07 15:26 ` Krzysztof Kozlowski
2025-11-05 19:53 ` Thierry Reding [this message]
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