[PATCH 0/2] clk: renesas: r8a779a0: Add clocks needed for GPU

[PATCH 0/2] clk: renesas: r8a779a0: Add clocks needed for GPU

[Niklas Söderlund]

Hi Geert,

This small series adds the clocks needed to use the GPU on V3U. The 
first is by far the most complex as the whole tree branch needed to be 
described.

With this and soon to be posted DT patches the GPU on V3U.

    powervr fd000000.gsx: [drm] loaded firmware powervr/rogue_15.5.1.64_v1.fw
    powervr fd000000.gsx: [drm] FW version v1.0 (build 6889268 OS)
    powervr fd000000.gsx: [drm] Unsupported quirks in firmware image
    [drm] Initialized powervr 1.0.0 for fd000000.gsx on minor 1

And run test applications such as gears.

Niklas Söderlund (2):
  clk: renesas: r8a779a0: Add ZG Core clock
  clk: renesas: r8a779a0: Add 3dge module clock

 drivers/clk/renesas/r8a779a0-cpg-mssr.c       | 9 ++++++++-
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 1 +
 2 files changed, 9 insertions(+), 1 deletion(-)

-- 
2.51.1

[PATCH 1/2] clk: renesas: r8a779a0: Add ZG Core clock

[Niklas Söderlund]

Describe the ZG Core clock needed to operate the PowerVR GPU.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c       | 8 +++++++-
 include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 1 +
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 1be7b9592aa6..a35110349769 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -26,7 +26,7 @@
 
 enum clk_ids {
 	/* Core Clock Outputs exported to DT */
-	LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,
+	LAST_DT_CORE_CLK = R8A779A0_CLK_ZG,
 
 	/* External Input Clocks */
 	CLK_EXTAL,
@@ -35,6 +35,7 @@ enum clk_ids {
 	/* Internal Core Clocks */
 	CLK_MAIN,
 	CLK_PLL1,
+	CLK_PLL4,
 	CLK_PLL20,
 	CLK_PLL21,
 	CLK_PLL30,
@@ -45,6 +46,7 @@ enum clk_ids {
 	CLK_PLL21_DIV2,
 	CLK_PLL30_DIV2,
 	CLK_PLL31_DIV2,
+	CLK_PLL4_DIV2,
 	CLK_PLL5_DIV2,
 	CLK_PLL5_DIV4,
 	CLK_S1,
@@ -65,6 +67,7 @@ enum clk_ids {
 #define CPG_PLL21CR	0x0838	/* PLL21 Control Register */
 #define CPG_PLL30CR	0x083c	/* PLL30 Control Register */
 #define CPG_PLL31CR	0x0840	/* PLL31 Control Register */
+#define CPG_PLL4CR	0x0844	/* PLL4 Control Register */
 
 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	/* External Clock Inputs */
@@ -79,12 +82,14 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_PLL(".pll21", CLK_PLL21,	CPG_PLL21CR),
 	DEF_PLL(".pll30", CLK_PLL30,	CPG_PLL30CR),
 	DEF_PLL(".pll31", CLK_PLL31,	CPG_PLL31CR),
+	DEF_PLL(".pll4",  CLK_PLL4,	CPG_PLL4CR),
 
 	DEF_FIXED(".pll1_div2",		CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),
 	DEF_FIXED(".pll20_div2",	CLK_PLL20_DIV2,	CLK_PLL20,	2, 1),
 	DEF_FIXED(".pll21_div2",	CLK_PLL21_DIV2,	CLK_PLL21,	2, 1),
 	DEF_FIXED(".pll30_div2",	CLK_PLL30_DIV2,	CLK_PLL30,	2, 1),
 	DEF_FIXED(".pll31_div2",	CLK_PLL31_DIV2,	CLK_PLL31,	2, 1),
+	DEF_FIXED(".pll4_div2",		CLK_PLL4_DIV2,	CLK_PLL4,	2, 1),
 	DEF_FIXED(".pll5_div2",		CLK_PLL5_DIV2,	CLK_PLL5,	2, 1),
 	DEF_FIXED(".pll5_div4",		CLK_PLL5_DIV4,	CLK_PLL5_DIV2,	2, 1),
 	DEF_FIXED(".s1",		CLK_S1,		CLK_PLL1_DIV2,	2, 1),
@@ -98,6 +103,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	/* Core Clock Outputs */
 	DEF_GEN4_Z("z0",	R8A779A0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL20,	2, 0),
 	DEF_GEN4_Z("z1",	R8A779A0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL21,	2, 8),
+	DEF_FIXED("zg",		R8A779A0_CLK_ZG,	CLK_PLL4_DIV2,	2, 1),
 	DEF_FIXED("zx",		R8A779A0_CLK_ZX,	CLK_PLL20_DIV2,	2, 1),
 	DEF_FIXED("s1d1",	R8A779A0_CLK_S1D1,	CLK_S1,		1, 1),
 	DEF_FIXED("s1d2",	R8A779A0_CLK_S1D2,	CLK_S1,		2, 1),
diff --git a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
index f1d737ca7ca1..124a6b8856df 100644
--- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
@@ -51,5 +51,6 @@
 #define R8A779A0_CLK_CBFUSA		40
 #define R8A779A0_CLK_R			41
 #define R8A779A0_CLK_OSC		42
+#define R8A779A0_CLK_ZG			43
 
 #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */
-- 
2.51.1

[PATCH 2/2] clk: renesas: r8a779a0: Add 3dge module clock

[Niklas Söderlund]

Describe the 3DGE module clock needed to operate the PowerVR GPU.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index a35110349769..c77b9b6977ec 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -144,6 +144,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 };
 
 static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
+	DEF_MOD("3dge",		  0,	R8A779A0_CLK_ZG),
 	DEF_MOD("isp0",		 16,	R8A779A0_CLK_S1D1),
 	DEF_MOD("isp1",		 17,	R8A779A0_CLK_S1D1),
 	DEF_MOD("isp2",		 18,	R8A779A0_CLK_S1D1),
-- 
2.51.1

Re: [PATCH 0/2] clk: renesas: r8a779a0: Add clocks needed for GPU

[Krzysztof Kozlowski]

On Thu, Nov 06, 2025 at 12:18:13AM +0100, Niklas Söderlund wrote:
> Hi Geert,
> 
> This small series adds the clocks needed to use the GPU on V3U. The 
> first is by far the most complex as the whole tree branch needed to be 
> described.
> 
> With this and soon to be posted DT patches the GPU on V3U.

You have checkpatch warning which is important, because would block from
merging DTS if it uses the binding header constant.

DTS cannot depend or even be based on driver patches.

Best regards,
Krzysztof

Re: [PATCH 0/2] clk: renesas: r8a779a0: Add clocks needed for GPU

[Niklas Söderlund]

Hello Krzysztof,

Thanks for your feedback.

On 2025-11-06 10:10:51 +0100, Krzysztof Kozlowski wrote:
> On Thu, Nov 06, 2025 at 12:18:13AM +0100, Niklas Söderlund wrote:
> > Hi Geert,
> > 
> > This small series adds the clocks needed to use the GPU on V3U. The 
> > first is by far the most complex as the whole tree branch needed to be 
> > described.
> > 
> > With this and soon to be posted DT patches the GPU on V3U.
> 
> You have checkpatch warning which is important, because would block from
> merging DTS if it uses the binding header constant.
> 
> DTS cannot depend or even be based on driver patches.

Indeed, my bad. I saw the warning and check how this was handled in the 
past. I found other commits doing what I did here, but I have now been 
educated that the ones I looked at where a special case and the correct 
thing is to split this.

Will fix, and thank you for your time letting me know!

> 
> Best regards,
> Krzysztof
> 

-- 
Kind Regards,
Niklas Söderlund

Re: [PATCH 1/2] clk: renesas: r8a779a0: Add ZG Core clock

[Geert Uytterhoeven]

Hi Niklas,

On Thu, 6 Nov 2025 at 00:18, Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Describe the ZG Core clock needed to operate the PowerVR GPU.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c

> @@ -35,6 +35,7 @@ enum clk_ids {
>         /* Internal Core Clocks */
>         CLK_MAIN,
>         CLK_PLL1,
> +       CLK_PLL4,

Please preserve sort order (see CLK_PLL5 below, out of context).

>         CLK_PLL20,
>         CLK_PLL21,
>         CLK_PLL30,

> @@ -98,6 +103,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
>         /* Core Clock Outputs */
>         DEF_GEN4_Z("z0",        R8A779A0_CLK_Z0,        CLK_TYPE_GEN4_Z,        CLK_PLL20,      2, 0),
>         DEF_GEN4_Z("z1",        R8A779A0_CLK_Z1,        CLK_TYPE_GEN4_Z,        CLK_PLL21,      2, 8),
> +       DEF_FIXED("zg",         R8A779A0_CLK_ZG,        CLK_PLL4_DIV2,  2, 1),

ZG is not a fixed clock, but has a programmable divider through the
FRQCRB.ZGFC register field.  Hence it should use CLK_TYPE_GEN4_Z.
As currently drivers/clk/renesas/rcar-gen4-cpg.c:cpg_z_clk_register()
supports only the FRQCRC(0) and FRQCRC1 registers, you will have to
extend the offset-to-register mapping support for that, too.

>         DEF_FIXED("zx",         R8A779A0_CLK_ZX,        CLK_PLL20_DIV2, 2, 1),
>         DEF_FIXED("s1d1",       R8A779A0_CLK_S1D1,      CLK_S1,         1, 1),
>         DEF_FIXED("s1d2",       R8A779A0_CLK_S1D2,      CLK_S1,         2, 1),

> --- a/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> +++ b/include/dt-bindings/clock/r8a779a0-cpg-mssr.h
> @@ -51,5 +51,6 @@
>  #define R8A779A0_CLK_CBFUSA            40
>  #define R8A779A0_CLK_R                 41
>  #define R8A779A0_CLK_OSC               42
> +#define R8A779A0_CLK_ZG                        43
>
>  #endif /* __DT_BINDINGS_CLOCK_R8A779A0_CPG_MSSR_H__ */

This should be a separate patch, so I can queue it in a branch shared
by clock driver and DT source files.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] clk: renesas: r8a779a0: Add 3dge module clock

[Geert Uytterhoeven]

On Thu, 6 Nov 2025 at 00:18, Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Describe the 3DGE module clock needed to operate the PowerVR GPU.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds