[PATCH 0/2] arm64: dts: renesas: Describe GPU on V3U

[PATCH 0/2] arm64: dts: renesas: Describe GPU on V3U

[Niklas Söderlund]

Hello,

This series adds the needed bindings to operate the PowerVR GPU on R-Car 
V3U SoCs. The works build on the efforts of Marek in [1], and patch 1/2 
depends that series.

I'm able to load the firmware from [2].

    powervr fd000000.gsx: [drm] loaded firmware powervr/rogue_15.5.1.64_v1.fw
    powervr fd000000.gsx: [drm] FW version v1.0 (build 6889268 OS)
    powervr fd000000.gsx: [drm] Unsupported quirks in firmware image
    [drm] Initialized powervr 1.0.0 for fd000000.gsx on minor 1

I can get run vulkaninfo from mesa.

    # PVR_I_WANT_A_BROKEN_VULKAN_DRIVER=1 meson devenv -C builddir vulkaninfo --summary
    'DISPLAY' environment variable not set... skipping surface info
    WARNING: powervr is not a conformant Vulkan implementation, testing use only.
    MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:73: FINISHME: Missing reset support for brn58839
    MESA: warning: ../src/imagination/vulkan/pvr_job_context.c:521: FINISHME: Missing support for brn62269
    MESA: warning: ../src/imagination/vulkan/pvr_border.c:117: FINISHME: Devices without tpu_border_colour_enhanced require entries for compressed formats to be stored in the table pre-compressed.
    ==========
    VULKANINFO
    ==========

    Vulkan Instance Version: 1.4.328


    Instance Extensions: count = 20
    -------------------------------
    VK_EXT_debug_report                    : extension revision 10
    VK_EXT_debug_utils                     : extension revision 2
    VK_EXT_headless_surface                : extension revision 1
    VK_EXT_surface_maintenance1            : extension revision 1
    VK_EXT_swapchain_colorspace            : extension revision 5
    VK_KHR_device_group_creation           : extension revision 1
    VK_KHR_display                         : extension revision 23
    VK_KHR_external_fence_capabilities     : extension revision 1
    VK_KHR_external_memory_capabilities    : extension revision 1
    VK_KHR_external_semaphore_capabilities : extension revision 1
    VK_KHR_get_display_properties2         : extension revision 1
    VK_KHR_get_physical_device_properties2 : extension revision 2
    VK_KHR_get_surface_capabilities2       : extension revision 1
    VK_KHR_portability_enumeration         : extension revision 1
    VK_KHR_surface                         : extension revision 25
    VK_KHR_surface_protected_capabilities  : extension revision 1
    VK_KHR_wayland_surface                 : extension revision 6
    VK_KHR_xcb_surface                     : extension revision 6
    VK_KHR_xlib_surface                    : extension revision 6
    VK_LUNARG_direct_driver_loading        : extension revision 1

    Instance Layers:
    ----------------

    Devices:
    ========
    GPU0:
	    apiVersion         = 1.2.330
	    driverVersion      = 25.99.99
	    vendorID           = 0x1010
	    deviceID           = 0x15001064
	    deviceType         = PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
	    deviceName         = PowerVR Rogue GE7800
	    driverID           = DRIVER_ID_IMAGINATION_OPEN_SOURCE_MESA
	    driverName         = Imagination open-source Mesa driver
	    driverInfo         = Mesa 26.0.0-devel (git-8fb0621f2d)
	    conformanceVersion = 1.3.8.4
	    deviceUUID         = 10131290-a76c-6b0d-6850-cdf5a340a60d
	    driverUUID         = 2e8b7d4b-71a8-3b5a-e19f-86a7a450b7ab
    GPU1:
	    apiVersion         = 1.4.330
	    driverVersion      = 25.99.99
	    vendorID           = 0x10005
	    deviceID           = 0x0000
	    deviceType         = PHYSICAL_DEVICE_TYPE_CPU
	    deviceName         = llvmpipe (LLVM 21.1.4, 128 bits)
	    driverID           = DRIVER_ID_MESA_LLVMPIPE
	    driverName         = llvmpipe
	    driverInfo         = Mesa 26.0.0-devel (git-8fb0621f2d) (LLVM 21.1.4)
	    conformanceVersion = 1.3.1.1
	    deviceUUID         = 6d657361-3236-2e30-2e30-2d6465766500

And test applications such as gears work as they should.

1. https://lore.kernel.org/linux-renesas-soc/20251104135716.12497-3-marek.vasut%2Brenesas@mailbox.org/
2. https://gitlab.freedesktop.org/imagination/linux-firmware/-/issues/13

Niklas Söderlund (2):
  dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas
    R-Car V3U
  arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

 .../bindings/gpu/img,powervr-rogue.yaml         |  4 +++-
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi       | 17 +++++++++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

-- 
2.51.1

[PATCH 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3U

[Niklas Söderlund]

Document Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
present in Renesas R-Car R8A779A0 V3U SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
 Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
index c89dbc92325a..142d6b0add85 100644
--- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
@@ -20,7 +20,9 @@ properties:
           - const: img,img-gx6250
           - const: img,img-rogue
       - items:
-          - const: renesas,r8a77965-gpu
+          - enum:
+              - renesas,r8a77965-gpu
+              - renesas,r8a779a0-gpu
           - const: img,img-ge7800
           - const: img,img-rogue
       - items:
-- 
2.51.1

[PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Niklas Söderlund]

Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
present in Renesas R-Car R8A779A0 V3U SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
---
 arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
index b08865841476..aa347b699340 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
@@ -338,6 +338,23 @@ cmt3: timer@e6148000 {
 			status = "disabled";
 		};
 
+		gsx: gsx@fd000000 {
+			compatible = "renesas,r8a779a0-gpu",
+				     "img,img-ge7800",
+				     "img,img-rogue";
+			reg = <0 0xfd000000 0 0x40000>;
+			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
+				 <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
+				 <&cpg CPG_MOD 0>;
+			clock-names = "core", "mem", "sys";
+			power-domains = <&sysc R8A779A0_PD_3DG_A>,
+					<&sysc R8A779A0_PD_3DG_B>;
+			power-domain-names = "a", "b";
+			resets = <&cpg 0>;
+			status = "disabled";
+		};
+
 		cpg: clock-controller@e6150000 {
 			compatible = "renesas,r8a779a0-cpg-mssr";
 			reg = <0 0xe6150000 0 0x4000>;
-- 
2.51.1

Re: [PATCH 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3U

[Marek Vasut]

On 11/6/25 12:27 AM, Niklas Söderlund wrote:
> Document Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> present in Renesas R-Car R8A779A0 V3U SoC.
> 
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Re: [PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Marek Vasut]

On 11/6/25 12:27 AM, Niklas Söderlund wrote:
> Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> present in Renesas R-Car R8A779A0 V3U SoC.
> 
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Re: [PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Matt Coster]

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Hi Niklas,

On 05/11/2025 23:27, Niklas Söderlund wrote:
> Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> present in Renesas R-Car R8A779A0 V3U SoC.
> 
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
>  arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> index b08865841476..aa347b699340 100644
> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -338,6 +338,23 @@ cmt3: timer@e6148000 {
>  			status = "disabled";
>  		};
>  
> +		gsx: gsx@fd000000 {

Why gsx? Marek's equivalent patch for r8a77965-gpu[1] used gpu (as we do
for every dt so far).

> +			compatible = "renesas,r8a779a0-gpu",
> +				     "img,img-ge7800",
> +				     "img,img-rogue";
> +			reg = <0 0xfd000000 0 0x40000>;
> +			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
> +				 <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
> +				 <&cpg CPG_MOD 0>;

I don't have access to a TRM for V3U (it's too new apparently, despite
already being obsolete), but I believe the GPU integration should be
similar to the M3N in [1]. In that case, the TRM (v2.40, fig 23.3) shows
S2D1 and 112 in place of S3D1 and 0 – are these definitely correct? The
0 especially feels wrong (see also 8A.2.1.2 MSTPSR1).

> +			clock-names = "core", "mem", "sys";
> +			power-domains = <&sysc R8A779A0_PD_3DG_A>,
> +					<&sysc R8A779A0_PD_3DG_B>;
> +			power-domain-names = "a", "b";
> +			resets = <&cpg 0>;

Same 0 concern as above.

Cheers,
Matt

[1]: https://lore.kernel.org/r/20251104135716.12497-3-marek.vasut+renesas@mailbox.org/

> +			status = "disabled";
> +		};
> +
>  		cpg: clock-controller@e6150000 {
>  			compatible = "renesas,r8a779a0-cpg-mssr";
>  			reg = <0 0xe6150000 0 0x4000>;

-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3U

[Matt Coster]

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Hi Niklas,

On 05/11/2025 23:27, Niklas Söderlund wrote:
> Document Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> present in Renesas R-Car R8A779A0 V3U SoC.
> 
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Thanks for your contribution!

Reviewed-by: Matt Coster <matt.coster@imgtec.com>

I just have a couple comments on the dts half of this series that I'm
sure will be easily resolved, then I'll take this patch via
drm-misc-next.

Cheers,
Matt

> ---
>  Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> index c89dbc92325a..142d6b0add85 100644
> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
> @@ -20,7 +20,9 @@ properties:
>            - const: img,img-gx6250
>            - const: img,img-rogue
>        - items:
> -          - const: renesas,r8a77965-gpu
> +          - enum:
> +              - renesas,r8a77965-gpu
> +              - renesas,r8a779a0-gpu
>            - const: img,img-ge7800
>            - const: img,img-rogue
>        - items:

-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Niklas Söderlund]

Hi Matt,

Thanks for your feedback.

On 2025-11-06 10:19:13 +0000, Matt Coster wrote:
> Hi Niklas,
> 
> On 05/11/2025 23:27, Niklas Söderlund wrote:
> > Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> > present in Renesas R-Car R8A779A0 V3U SoC.
> > 
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++++++
> >  1 file changed, 17 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> > index b08865841476..aa347b699340 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> > @@ -338,6 +338,23 @@ cmt3: timer@e6148000 {
> >  			status = "disabled";
> >  		};
> >  
> > +		gsx: gsx@fd000000 {
> 
> Why gsx? Marek's equivalent patch for r8a77965-gpu[1] used gpu (as we do
> for every dt so far).

Wops, will fix.

> 
> > +			compatible = "renesas,r8a779a0-gpu",
> > +				     "img,img-ge7800",
> > +				     "img,img-rogue";
> > +			reg = <0 0xfd000000 0 0x40000>;
> > +			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
> > +				 <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
> > +				 <&cpg CPG_MOD 0>;
> 
> I don't have access to a TRM for V3U (it's too new apparently, despite
> already being obsolete), but I believe the GPU integration should be
> similar to the M3N in [1]. In that case, the TRM (v2.40, fig 23.3) shows
> S2D1 and 112 in place of S3D1 and 0 – are these definitely correct? The
> 0 especially feels wrong (see also 8A.2.1.2 MSTPSR1).

Yea the V3U doc I have is not the latest. The diagram in the GPU chapter 
list the same as you say here (S2D1 and 112), however the diagram seems 
to just be a copy-past of the Gen3 document. Looking elsewhere in the 
document I see:

- In the clock chapter the GPU is list as MSTP0 and not MSTP112.  
  Comparing with the Gen3 doc this looks correct so MSTP0 is good IMHO.

- The V3U don't have a S2D1 clock... but the GPU chapter lists it in the 
  (assumed) copy-pasted diagram...  What I did was track which clocks 
  where S2D1 on Gen3 and compared that to what those IP where using on 
  V3U. The overlap was the DU and that uses S3D1 on V3U so I just 
  followed that.

> 
> > +			clock-names = "core", "mem", "sys";
> > +			power-domains = <&sysc R8A779A0_PD_3DG_A>,
> > +					<&sysc R8A779A0_PD_3DG_B>;
> > +			power-domain-names = "a", "b";
> > +			resets = <&cpg 0>;
> 
> Same 0 concern as above.
> 
> Cheers,
> Matt
> 
> [1]: https://lore.kernel.org/r/20251104135716.12497-3-marek.vasut+renesas@mailbox.org/
> 
> > +			status = "disabled";
> > +		};
> > +
> >  		cpg: clock-controller@e6150000 {
> >  			compatible = "renesas,r8a779a0-cpg-mssr";
> >  			reg = <0 0xe6150000 0 0x4000>;
> 
> -- 
> Matt Coster
> E: matt.coster@imgtec.com




-- 
Kind Regards,
Niklas Söderlund

Re: [PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Matt Coster]

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Hi Niklas,

On 06/11/2025 10:39, Niklas Söderlund wrote:
> Hi Matt,
> 
> Thanks for your feedback.
> 
> On 2025-11-06 10:19:13 +0000, Matt Coster wrote:
>> Hi Niklas,
>>
>> On 05/11/2025 23:27, Niklas Söderlund wrote:
>>> Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
>>> present in Renesas R-Car R8A779A0 V3U SoC.
>>>
>>> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>>> ---
>>>  arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++++++
>>>  1 file changed, 17 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
>>> index b08865841476..aa347b699340 100644
>>> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
>>> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
>>> @@ -338,6 +338,23 @@ cmt3: timer@e6148000 {
>>>  			status = "disabled";
>>>  		};
>>>  
>>> +		gsx: gsx@fd000000 {
>>
>> Why gsx? Marek's equivalent patch for r8a77965-gpu[1] used gpu (as we do
>> for every dt so far).
> 
> Wops, will fix.
> 
>>
>>> +			compatible = "renesas,r8a779a0-gpu",
>>> +				     "img,img-ge7800",
>>> +				     "img,img-rogue";
>>> +			reg = <0 0xfd000000 0 0x40000>;
>>> +			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
>>> +			clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
>>> +				 <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
>>> +				 <&cpg CPG_MOD 0>;
>>
>> I don't have access to a TRM for V3U (it's too new apparently, despite
>> already being obsolete), but I believe the GPU integration should be
>> similar to the M3N in [1]. In that case, the TRM (v2.40, fig 23.3) shows
>> S2D1 and 112 in place of S3D1 and 0 – are these definitely correct? The
>> 0 especially feels wrong (see also 8A.2.1.2 MSTPSR1).
> 
> Yea the V3U doc I have is not the latest. The diagram in the GPU chapter 
> list the same as you say here (S2D1 and 112), however the diagram seems 
> to just be a copy-past of the Gen3 document. Looking elsewhere in the 
> document I see:
> 
> - In the clock chapter the GPU is list as MSTP0 and not MSTP112.  
>   Comparing with the Gen3 doc this looks correct so MSTP0 is good IMHO.

Sounds reasonable. Just to cross-reference that, does 3DGE appear in the
0-bit row of the table under the register definition of MSTPSR0? I see
from renesas-cpg-mssr.c that these registers have moved for gen4 though,
so this could be a blind alley.

A similar thought – is a new entry in r8a779a0_mod_clks (defined in
r8a779a0-cpg-mssr.c) required? The equivalent table for r8a77965 has a
"3dge" entry at 112.

> 
> - The V3U don't have a S2D1 clock... but the GPU chapter lists it in the 
>   (assumed) copy-pasted diagram...  What I did was track which clocks 
>   where S2D1 on Gen3 and compared that to what those IP where using on 
>   V3U. The overlap was the DU and that uses S3D1 on V3U so I just 
>   followed that.

There's a top-level clock diagram near the top of the CPG chapter in the
TRM I have (fig 8.1d for M3N) that annotates S2D1 as being an AXI-bus
clock. Is there a similar annotation on S3D1 for V3U in your TRM? If
not, I'm happy to just follow your logic and ack this patch :)

Cheers,
Matt

> 
>>
>>> +			clock-names = "core", "mem", "sys";
>>> +			power-domains = <&sysc R8A779A0_PD_3DG_A>,
>>> +					<&sysc R8A779A0_PD_3DG_B>;
>>> +			power-domain-names = "a", "b";
>>> +			resets = <&cpg 0>;
>>
>> Same 0 concern as above.
>>
>> Cheers,
>> Matt
>>
>> [1]: https://lore.kernel.org/r/20251104135716.12497-3-marek.vasut+renesas@mailbox.org/ 
>>
>>> +			status = "disabled";
>>> +		};
>>> +
>>>  		cpg: clock-controller@e6150000 {
>>>  			compatible = "renesas,r8a779a0-cpg-mssr";
>>>  			reg = <0 0xe6150000 0 0x4000>;
>>
>> -- 
>> Matt Coster
>> E: matt.coster@imgtec.com

-- 
Matt Coster
E: matt.coster@imgtec.com

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Re: [PATCH 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3U

[Geert Uytterhoeven]

On Thu, 6 Nov 2025 at 00:28, Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Document Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> present in Renesas R-Car R8A779A0 V3U SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Geert Uytterhoeven]

Hi Niklas,

On Thu, 6 Nov 2025 at 00:28, Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> present in Renesas R-Car R8A779A0 V3U SoC.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> @@ -338,6 +338,23 @@ cmt3: timer@e6148000 {
>                         status = "disabled";
>                 };
>
> +               gsx: gsx@fd000000 {

Please preserve sort order (by unit address).

> +                       compatible = "renesas,r8a779a0-gpu",
> +                                    "img,img-ge7800",
> +                                    "img,img-rogue";
> +                       reg = <0 0xfd000000 0 0x40000>;
> +                       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
> +                                <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
> +                                <&cpg CPG_MOD 0>;
> +                       clock-names = "core", "mem", "sys";
> +                       power-domains = <&sysc R8A779A0_PD_3DG_A>,
> +                                       <&sysc R8A779A0_PD_3DG_B>;
> +                       power-domain-names = "a", "b";
> +                       resets = <&cpg 0>;
> +                       status = "disabled";
> +               };
> +
>                 cpg: clock-controller@e6150000 {
>                         compatible = "renesas,r8a779a0-cpg-mssr";
>                         reg = <0 0xe6150000 0 0x4000>;

The rest LGTM, so with the node name and sort order fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/2] dt-bindings: gpu: img,powervr-rogue: Document GE7800 GPU in Renesas R-Car V3U

[Conor Dooley]

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Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

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Re: [PATCH 2/2] arm64: dts: renesas: r8a779a0: Add GE7800 GPU node

[Niklas Söderlund]

Hi Matt,

On 2025-11-06 13:04:19 +0000, Matt Coster wrote:
> Hi Niklas,
> 
> On 06/11/2025 10:39, Niklas Söderlund wrote:
> > Hi Matt,
> > 
> > Thanks for your feedback.
> > 
> > On 2025-11-06 10:19:13 +0000, Matt Coster wrote:
> >> Hi Niklas,
> >>
> >> On 05/11/2025 23:27, Niklas Söderlund wrote:
> >>> Describe Imagination Technologies PowerVR Rogue GE7800 BNVC 15.5.1.64
> >>> present in Renesas R-Car R8A779A0 V3U SoC.
> >>>
> >>> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> >>> ---
> >>>  arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++++++
> >>>  1 file changed, 17 insertions(+)
> >>>
> >>> diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> >>> index b08865841476..aa347b699340 100644
> >>> --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> >>> +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi
> >>> @@ -338,6 +338,23 @@ cmt3: timer@e6148000 {
> >>>  			status = "disabled";
> >>>  		};
> >>>  
> >>> +		gsx: gsx@fd000000 {
> >>
> >> Why gsx? Marek's equivalent patch for r8a77965-gpu[1] used gpu (as we do
> >> for every dt so far).
> > 
> > Wops, will fix.
> > 
> >>
> >>> +			compatible = "renesas,r8a779a0-gpu",
> >>> +				     "img,img-ge7800",
> >>> +				     "img,img-rogue";
> >>> +			reg = <0 0xfd000000 0 0x40000>;
> >>> +			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> >>> +			clocks = <&cpg CPG_CORE R8A779A0_CLK_ZG>,
> >>> +				 <&cpg CPG_CORE R8A779A0_CLK_S3D1>,
> >>> +				 <&cpg CPG_MOD 0>;
> >>
> >> I don't have access to a TRM for V3U (it's too new apparently, despite
> >> already being obsolete), but I believe the GPU integration should be
> >> similar to the M3N in [1]. In that case, the TRM (v2.40, fig 23.3) shows
> >> S2D1 and 112 in place of S3D1 and 0 – are these definitely correct? The
> >> 0 especially feels wrong (see also 8A.2.1.2 MSTPSR1).
> > 
> > Yea the V3U doc I have is not the latest. The diagram in the GPU chapter 
> > list the same as you say here (S2D1 and 112), however the diagram seems 
> > to just be a copy-past of the Gen3 document. Looking elsewhere in the 
> > document I see:
> > 
> > - In the clock chapter the GPU is list as MSTP0 and not MSTP112.  
> >   Comparing with the Gen3 doc this looks correct so MSTP0 is good IMHO.
> 
> Sounds reasonable. Just to cross-reference that, does 3DGE appear in the
> 0-bit row of the table under the register definition of MSTPSR0? I see
> from renesas-cpg-mssr.c that these registers have moved for gen4 though,
> so this could be a blind alley.

It do appear on the 0-bit row of MSTPSR0. But on V3U the bit is called 
RGX not 3DGE as in Gen3.

> 
> A similar thought – is a new entry in r8a779a0_mod_clks (defined in
> r8a779a0-cpg-mssr.c) required? The equivalent table for r8a77965 has a
> "3dge" entry at 112.

Yes. Both for MSTP112 module clock and the ZG core clock. Patches 
posted. Will try to do the v2 of that series at the same time as the 
fixes for this one.

https://lore.kernel.org/linux-renesas-soc/20251105231815.1927239-1-niklas.soderlund%2Brenesas@ragnatech.se/

> 
> > 
> > - The V3U don't have a S2D1 clock... but the GPU chapter lists it in the 
> >   (assumed) copy-pasted diagram...  What I did was track which clocks 
> >   where S2D1 on Gen3 and compared that to what those IP where using on 
> >   V3U. The overlap was the DU and that uses S3D1 on V3U so I just 
> >   followed that.
> 
> There's a top-level clock diagram near the top of the CPG chapter in the
> TRM I have (fig 8.1d for M3N) that annotates S2D1 as being an AXI-bus
> clock.

I see the M3-N S2D1 clock in the Gen3 doc.

> Is there a similar annotation on S3D1 for V3U in your TRM? If
> not, I'm happy to just follow your logic and ack this patch :)

I do not see the S3D1 in the same diagram for V3U, only S3. I do however 
see S3D1 a few pages below in the table below the diagram. In the Gen3 
doc that would be the equivalent of table Table 8.2d.

> 
> Cheers,
> Matt
> 
> > 
> >>
> >>> +			clock-names = "core", "mem", "sys";
> >>> +			power-domains = <&sysc R8A779A0_PD_3DG_A>,
> >>> +					<&sysc R8A779A0_PD_3DG_B>;
> >>> +			power-domain-names = "a", "b";
> >>> +			resets = <&cpg 0>;
> >>
> >> Same 0 concern as above.
> >>
> >> Cheers,
> >> Matt
> >>
> >> [1]: https://lore.kernel.org/r/20251104135716.12497-3-marek.vasut+renesas@mailbox.org/ 
> >>
> >>> +			status = "disabled";
> >>> +		};
> >>> +
> >>>  		cpg: clock-controller@e6150000 {
> >>>  			compatible = "renesas,r8a779a0-cpg-mssr";
> >>>  			reg = <0 0xe6150000 0 0x4000>;
> >>
> >> -- 
> >> Matt Coster
> >> E: matt.coster@imgtec.com
> 
> -- 
> Matt Coster
> E: matt.coster@imgtec.com




-- 
Kind Regards,
Niklas Söderlund