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Fri, 07 Nov 2025 19:23:48 -0800 (PST) Received: from [192.168.0.104] ([106.219.179.230]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-297d83c941esm19942445ad.44.2025.11.07.19.23.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Nov 2025 19:23:48 -0800 (PST) From: Manivannan Sadhasivam Date: Sat, 08 Nov 2025 08:53:20 +0530 Subject: [PATCH v2 2/4] PCI/pwrctrl: Add support for handling PCIe M.2 connectors Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251108-pci-m2-v2-2-e8bc4d7bf42d@oss.qualcomm.com> References: <20251108-pci-m2-v2-0-e8bc4d7bf42d@oss.qualcomm.com> In-Reply-To: <20251108-pci-m2-v2-0-e8bc4d7bf42d@oss.qualcomm.com> To: Bjorn Helgaas , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski Cc: linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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These connectors are exposed as the Power Sequencing devices as they often support multiple interfaces like PCIe/SATA, USB/UART to the host machine and each interfaces could be driven by different client drivers at the same time. This driver handles the PCIe interface of these connectors. It first checks for the presence of the graph port in the Root Port node with the help of of_graph_is_present() API, if present, it acquires/poweres ON the corresponding pwrseq device. Once the pwrseq device is powered ON, the driver will skip parsing the Root Port/Slot resources and registers with the pwrctrl framework. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/Kconfig | 1 + drivers/pci/pwrctrl/slot.c | 35 ++++++++++++++++++++++++++++++----- 2 files changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pwrctrl/Kconfig b/drivers/pci/pwrctrl/Kconfig index 6956c18548114ce12247b560f1ef159eb7e90b10..9a195cb7e117465625c68301534af22000dfca8d 100644 --- a/drivers/pci/pwrctrl/Kconfig +++ b/drivers/pci/pwrctrl/Kconfig @@ -13,6 +13,7 @@ config PCI_PWRCTRL_PWRSEQ config PCI_PWRCTRL_SLOT tristate "PCI Power Control driver for PCI slots" + select POWER_SEQUENCING select PCI_PWRCTRL help Say Y here to enable the PCI Power Control driver to control the power diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 3320494b62d890ffbae6f125e2704167ebccf7b9..d46c2365208ac87c4e83ba8d69ac1914d9bf9088 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -8,8 +8,10 @@ #include #include #include +#include #include #include +#include #include #include @@ -17,12 +19,18 @@ struct pci_pwrctrl_slot_data { struct pci_pwrctrl ctx; struct regulator_bulk_data *supplies; int num_supplies; + struct pwrseq_desc *pwrseq; }; static void devm_pci_pwrctrl_slot_power_off(void *data) { struct pci_pwrctrl_slot_data *slot = data; + if (slot->pwrseq) { + pwrseq_power_off(slot->pwrseq); + return; + } + regulator_bulk_disable(slot->num_supplies, slot->supplies); regulator_bulk_free(slot->num_supplies, slot->supplies); } @@ -38,6 +46,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev) if (!slot) return -ENOMEM; + if (of_graph_is_present(dev_of_node(dev))) { + slot->pwrseq = devm_pwrseq_get(dev, "pcie"); + if (IS_ERR(slot->pwrseq)) + return dev_err_probe(dev, PTR_ERR(slot->pwrseq), + "Failed to get the power sequencer\n"); + + ret = pwrseq_power_on(slot->pwrseq); + if (ret) + return dev_err_probe(dev, ret, + "Failed to power-on the device\n"); + + goto skip_resources; + } + ret = of_regulator_bulk_get_all(dev, dev_of_node(dev), &slot->supplies); if (ret < 0) { @@ -53,17 +75,20 @@ static int pci_pwrctrl_slot_probe(struct platform_device *pdev) return ret; } - ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, - slot); - if (ret) - return ret; - clk = devm_clk_get_optional_enabled(dev, NULL); if (IS_ERR(clk)) { + regulator_bulk_disable(slot->num_supplies, slot->supplies); + regulator_bulk_free(slot->num_supplies, slot->supplies); return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable slot clock\n"); } +skip_resources: + ret = devm_add_action_or_reset(dev, devm_pci_pwrctrl_slot_power_off, + slot); + if (ret) + return ret; + pci_pwrctrl_init(&slot->ctx, dev); ret = devm_pci_pwrctrl_device_set_ready(dev, &slot->ctx); -- 2.48.1