From: Conor Dooley <conor@kernel.org>
To: claudiu.beznea@tuxon.dev
Cc: conor@kernel.org, Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
pierre-henry.moussay@microchip.com,
valentina.fernandezalanis@microchip.com,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v7 5/5] MAINTAINERS: rename Microchip RISC-V entry
Date: Mon, 10 Nov 2025 11:23:54 +0000 [thread overview]
Message-ID: <20251110-feminine-aware-9a4b62e8ac0a@spud> (raw)
In-Reply-To: <20251110-zookeeper-femur-68a0ae346397@spud>
From: Conor Dooley <conor.dooley@microchip.com>
There's now non-FPGA RISC-V SoCs from Microchip, so rename the entry
to reflect that.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index a28740a7d87a..24efae3df425 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22079,7 +22079,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
F: drivers/iommu/riscv/
-RISC-V MICROCHIP FPGA SUPPORT
+RISC-V MICROCHIP SUPPORT
M: Conor Dooley <conor.dooley@microchip.com>
M: Daire McNamara <daire.mcnamara@microchip.com>
L: linux-riscv@lists.infradead.org
--
2.51.0
prev parent reply other threads:[~2025-11-10 11:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-10 11:23 [PATCH v7 0/5] Redo PolarFire SoC's mailbox/clock devicestrees and related code Conor Dooley
2025-11-10 11:23 ` [PATCH v7 1/5] reset: mpfs: add non-auxiliary bus probing Conor Dooley
2025-11-10 11:34 ` Philipp Zabel
2025-11-11 16:46 ` Conor Dooley
2025-11-11 16:49 ` Conor Dooley
2025-11-10 11:23 ` [PATCH v7 2/5] riscv: dts: microchip: fix mailbox description Conor Dooley
2025-11-10 11:23 ` [PATCH v7 3/5] riscv: dts: microchip: convert clock and reset to use syscon Conor Dooley
2025-11-10 11:23 ` [PATCH v7 4/5] MAINTAINERS: add new soc drivers to Microchip RISC-V entry Conor Dooley
2025-11-10 11:23 ` Conor Dooley [this message]
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