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([2a01:e0a:f:6020:d5ec:666a:8d59:87fa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47774df2d80sm140111375e9.14.2025.11.10.09.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 09:33:35 -0800 (PST) From: Vincent Guittot To: chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com, s32@nxp.com, bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com, ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com, Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev Cc: cassel@kernel.org Subject: [PATCH 0/4 v4] PCI: s32g: Add support for PCIe controller Date: Mon, 10 Nov 2025 18:33:30 +0100 Message-ID: <20251110173334.234303-1-vincent.guittot@linaro.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The S32G SoC family has 2 PCIe controllers based on Designware IP. Add the support for Host mode. Change since v3: - Added Root Port node and reorder irq in binding - Added Root Port management in driver - Fix Kconfig PCIE_NXP_S32G position - Use default pme_turn_off method - Use ops->init() to simplify init and suspend/resume sequence - Fix some typos. - Removed MPS and ERROR config. Let core code configs them. - Removed s32g_pcie_disable_equalization() from internal team request - Removed dw_pcie_link_up() from suspend/resume functions with [1] - I'm still waiting feedback from internal team before removing .get_ltssm() and .link_up() functions. [1] https://lore.kernel.org/all/20251107044319.8356-1-manivannan.sadhasivam@oss.qualcomm.com/ Change since v2: - More cleanup on DT binding to comply with schemas/pci/snps,dw-pcie.yaml - Added new reg and bit fields in pcie-designware.h - Rename Kconfig PCIE_NXP_S32G and files to use pcie-nxp-s32g prefix - Prefixed s32G registers with PCIE_S32G_ and use generic regs otherwise - Use memblock_start_of_DRAM to set coherency boundary and add comments - Fixed suspend/resume sequence by adding missing pme_turn_off function - Added .probe_type = PROBE_PREFER_ASYNCHRONOUS to speedup probe - Added pm_runtime_no_callbacks() as device doesn't have runtime ops - Use writel/readl in ctrl function instead of dw_pcie_write/read - Move Maintainer section in a dedicated entry Change since v1: - Cleanup DT binding - Removed useless description and fixed typo, naming and indentation. - Removed nxp,phy-mode binding until we agreed on a generic binding. Default (crnss) mode is used for now. Generic binding wil be discussed in a separate patch. - Removed max-link-speed and num-lanes which are coming from snps,dw-pcie-common.yaml. They are needed only if to restrict from the the default hw config. - Added unevaluatedProperties: false - Keep Phys in host node until dw support Root Port node. - Removed nxp-s32g-pcie-phy-submode.h until there is a generic clock and spectrum binding. - Rename files to start with pcie-s32g instead of pci-s32g - Cleanup pcie-s32-reg.h and use dw_pcie_find_capability() - cleanup and rename in s32g-pcie.c in addtion to remove useless check or duplicate code. - dw_pcie_suspend/resume_noirq() doesn't woork, need to set child device to reach lowest state. - Added L: imx@lists.linux.dev in MAINTAINERS Vincent Guittot (4): dt-bindings: PCI: s32g: Add NXP PCIe controller PCI: dw: Add more registers and bitfield definition PCI: s32g: Add initial PCIe support (RC) MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver .../bindings/pci/nxp,s32g-pcie.yaml | 130 ++++++ MAINTAINERS | 9 + drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware.h | 8 + .../pci/controller/dwc/pcie-nxp-s32g-regs.h | 27 ++ drivers/pci/controller/dwc/pcie-nxp-s32g.c | 435 ++++++++++++++++++ 7 files changed, 620 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-nxp-s32g-regs.h create mode 100644 drivers/pci/controller/dwc/pcie-nxp-s32g.c -- 2.43.0