From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C68C82D9493 for ; Mon, 10 Nov 2025 17:33:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762796022; cv=none; b=ROx6JY4heEIUArv3V8DAXb+zBVAIWUSvZjOm+yKGztx5/2yMaJBblYhhop6Q13czKlEGd/7JaFDNRddqIQ9U59X5HJA9gw2TFxMdchr+54cWSBIxyjaQsQPvvbUMRKmF/IUnM62psiOdo6ZeUA2TTmUUE+z8kiFCOVqtnCTcnz8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1762796022; c=relaxed/simple; bh=VwXqjqb0vlwdIay3FsUmamgWNpL8wpFbJjWxzHFn1II=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cXx+N5AlLwjBEnVa9Xvxq8NkZ8SeITyTKqbEFsaiggvDZiomTi7AJ1xBESAXrqFiWI9sXl2+NFn7brrjgKv3WeHE4lsVxmtD9ByMT6QC/tdpSRqTZK2ghKgvYrimCQTRN3sk5sHuX9WZaruecWihqIQRi+vNlJsYCfZHqNjXtao= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JhA4EfbX; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JhA4EfbX" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-4775ae77516so39289025e9.1 for ; Mon, 10 Nov 2025 09:33:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1762796017; x=1763400817; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7sHMOBUaDG1Wui3cyeff4HsBqo1sgWu6v9dYZ/ORpKI=; b=JhA4EfbXTf9abdSiI+V6pCyRrMr6CWyFePgvp73X10+h8HfUJI/PFP//a1EWNCbX5o 9IzISxq3CEMPmy55baTMok7GD6snldJHOWUey8X1k+M64sAx2JCKL3D2qZtZGn4klvbU i7/DsmQXcltWhM4oTkuz15WUYaMIXNIRkqa271oSzXuuo1cRUTb2e8E4NLEn7I5kMF7c Zu8LEc9dAP65JN7LZcfzNQZSsisgI7rFyPNgx7v2WVlbnBvTgukVw2vUo4vUTrwaz6Os EXMtTRk/qgTvOTM2Q6tR480rx+dBewIqCmJv2Muh5zOpq7qlIWRTDzr3CWuA1/+w1xNt /wQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1762796017; x=1763400817; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7sHMOBUaDG1Wui3cyeff4HsBqo1sgWu6v9dYZ/ORpKI=; b=oO3YfA2+N0sxjcOdeB75nhF9cJEOMZL5zKkS+hmjLpd9nf9bKy+TtKaRhdB5lQTYIX zyIQrGC/+RHUe0b+23AoOYrpqmgGeS5AMYfUoHVSEkYMjRzuaABzYkIC/wpChcbwlMcd 7tUDjbO//OkGLGpvFDIsteXNHissTVcgRRRSFynPZf1gdxO6BVOkN4KIypvmN4C/oNs4 tfYeZlgxh1LmePTKGphOpKKWr355tOuD1G+oqtOsQVzD3YHNBnqmAev/PAlkcDUE7Lcf 8NOVjw0i7sMDd34nkGQ40dA15UQKPvW6YEX1bbuptlaOO4CKxG+5r4dnHGVKJ1BBRxYB R4KQ== X-Forwarded-Encrypted: i=1; AJvYcCWquRvwl7rJb7orj0GHsWwMIFDzpZZMJhTv2gBFSs2YPcoVTsIpmbkb1cyh2vTB94ieZJ+Nqk5bw+hg@vger.kernel.org X-Gm-Message-State: AOJu0YwryCpR/w1xJPPjXmiB9hQWugyLRokxgpZZ2Ynl90MVDcwU3I6B H0tr0kpw7DS4I7+FtvhyFq63FpeSKCoKreVGTuLyFlbUhy9z/EiYJ/jDWR21T2Q2jng= X-Gm-Gg: ASbGncs/msXpLwj2MpnoWG0K6brDK8eqWJLQn23hDv4rU5fUuSxAGq2fO5MGCuqqxR7 cr8niJMLN24J671Z+7r4TIiMJdPIBYs3VxhSc0w1fGQGusiilrPkymwZLAHVu09IbNKlpOCndoA 4QkY+vqNJuDd0LsgAubJHpblhpfhKLM8mkqycF3vJO1rvcjtbBGL8aYQxuoRCuQknEA1guT7nrY VMI+1ooPodTGvFIlgUJsCAE0VLR0pFxsX2sjNMH1b/4Ovf9qFSiREdq02o4ZnnNyCv+aXi78VEL ygAJrNIce31RlghAxGjRs8ACYh5782IbXbwEg2iGEjrDYeaqF0yhAg33njXb/rqnKnIbg7+jZLP gWwFRcYRfoUptw8I27H5TIvzswt+cX0lU1w7blF4WKFXeRPlwEEk0KlPnrJYvZOS3HM0DkcuKPh Zi09awdt+i X-Google-Smtp-Source: AGHT+IFFes5RpqIkwRV81cjLZLjmcQ90Ib1gecuHLTiUtJRRieBtbR+NqpbH88IgcfUI1Bw2hVKcTw== X-Received: by 2002:a05:600c:474c:b0:475:da13:256b with SMTP id 5b1f17b1804b1-4777329777amr79682445e9.38.1762796017253; Mon, 10 Nov 2025 09:33:37 -0800 (PST) Received: from vingu-cube.. ([2a01:e0a:f:6020:d5ec:666a:8d59:87fa]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47774df2d80sm140111375e9.14.2025.11.10.09.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Nov 2025 09:33:36 -0800 (PST) From: Vincent Guittot To: chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com, s32@nxp.com, bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com, ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com, Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev Cc: cassel@kernel.org Subject: [PATCH 1/4 v4] dt-bindings: PCI: s32g: Add NXP PCIe controller Date: Mon, 10 Nov 2025 18:33:31 +0100 Message-ID: <20251110173334.234303-2-vincent.guittot@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251110173334.234303-1-vincent.guittot@linaro.org> References: <20251110173334.234303-1-vincent.guittot@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Describe the PCIe host controller available on the S32G platforms. Co-developed-by: Ionut Vicovan Signed-off-by: Ionut Vicovan Co-developed-by: Bogdan-Gabriel Roman Signed-off-by: Bogdan-Gabriel Roman Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Co-developed-by: Ciprian Marian Costea Signed-off-by: Ciprian Marian Costea Co-developed-by: Bogdan Hamciuc Signed-off-by: Bogdan Hamciuc Signed-off-by: Vincent Guittot --- .../bindings/pci/nxp,s32g-pcie.yaml | 130 ++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml new file mode 100644 index 000000000000..6077c251c2cd --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nxp,s32g-pcie.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nxp,s32g-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2xxx/S32G3xxx PCIe Root Complex controller + +maintainers: + - Bogdan Hamciuc + - Ionut Vicovan + +description: + This PCIe controller is based on the Synopsys DesignWare PCIe IP. + The S32G SoC family has two PCIe controllers, which can be configured as + either Root Complex or Endpoint. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-pcie + - items: + - const: nxp,s32g3-pcie + - const: nxp,s32g2-pcie + + reg: + maxItems: 6 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: ctrl + - const: config + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: msi + - const: dma + minItems: 1 + + pcie@0: + description: + Describe the S32G Root Port. + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + required: + - reg + - phys + + unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - ranges + - pcie@0 + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@40400000 { + compatible = "nxp,s32g3-pcie", + "nxp,s32g2-pcie"; + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */ + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */ + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */ + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */ + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */ + <0x5f 0xffffe000 0x0 0x00002000>; /* config space */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config"; + dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = + <0x81000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>, + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>, + <0x82000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>; + + bus-range = <0x0 0xff>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + + pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + + device_type = "pci"; + phys = <&serdes0 PHY_TYPE_PCIE 0 0>; + }; + }; + }; -- 2.43.0