[PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Michal Wilczynski]

This series enables the display subsystem on the StarFive JH7110 SoC.
This hardware has a complex set of dependencies that this series aims to
solve.

The dom_vout (Video Output) block is a wrapper containing the display
controller (dc8200), the clock generator (voutcrg), and the HDMI IP, all
of which are managed by a single power domain (PD_VOUT).

More importantly, the HDMI IP is a monolithic block (controller and PHY
in one register space) that has a circular dependency with voutcrg:
1. The HDMI Controller needs clocks (like sysclk, mclk) from voutcrg to
   function.
2. The voutcrg (for its pixel MUXes) needs the variable pixel clock,
   which is generated by the HDMI PHY.

This series breaks this dependency loop by modeling the hardware
correctly:
1. A new vout-subsystem wrapper driver is added. It manages the shared
   PD_VOUT power domain and top level bus clocks. It uses
   of_platform_populate() to ensure its children (hdmi_mfd, voutcrg,
   dc8200) are probed only after power is on.
2. The monolithic hdmi node is refactored into an MFD. A new hdmi-mfd
   parent driver is added, which maps the shared register space and
   creates a regmap.
3. The MFD populates two children:
   - hdmi-phy: A new PHY driver that binds to the MFD. Its only
     dependency is the xin24m reference clock. It acts as the clock
     provider for the variable pixel clock (hdmi_pclk).
   - hdmi-controller: A new DRM bridge driver. It consumes clocks from
     voutcrg and the hdmi_pclk/PHY from its sibling hdmi-phy driver.
4. The generic inno-hdmi bridge library is refactored to accept a regmap
   from a parent MFD, making this model possible.

This MFD split breaks the circular dependency, as the kernel's deferred
probe can now find a correct, linear probe order: hdmi-phy (probes
first) -> voutcrg (probes second) -> hdmi-controller (probes third).

This series provides all the necessary dt-bindings, the new drivers, the
modification to inno-hdmi, and the final device tree changes to enable
the display.

Series depends on patchsets that are not merged yet:
 - dc8200 driver [1]
 - th1520 reset (dependency of dc8200 series) [2]
 - inno-hdmi bridge [3]

Testing:
I've tested on my monitor using `modetest` for following modes:
  #0 2560x1440 59.95 2560 2608 2640 2720 1440 1443 1448 1481 241500
     flags: phsync, nvsync; type: preferred, driver [DOESN"T WORK]
  #1 2048x1080 60.00 2048 2096 2128 2208 1080 1083 1093 1111 147180
     flags: phsync, nvsync; type: driver    [DOESN"T WORK]
  #2 2048x1080 24.00 2048 2096 2128 2208 1080 1083 1093 1099 58230
     flags: phsync, nvsync; type: driver     [DOESN'T WORK]
  #3 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500
     flags: phsync, pvsync; type: driver    [WORKS]
  #4 1920x1080 59.94 1920 2008 2052 2200 1080 1084 1089 1125 148352
     flags: phsync, pvsync; type: driver    [WORKS]
  #5 1920x1080 50.00 1920 2448 2492 2640 1080 1084 1089 1125 148500
     flags: phsync, pvsync; type: driver    [WORKS]
  #6 1600x1200 60.00 1600 1664 1856 2160 1200 1201 1204 1250 162000
     flags: phsync, pvsync; type: driver    [WORKS]
  #7 1280x1024 75.02 1280 1296 1440 1688 1024 1025 1028 1066 135000
     flags: phsync, pvsync; type: driver    [WORKS]
  #8 1280x1024 60.02 1280 1328 1440 1688 1024 1025 1028 1066 108000
     flags: phsync, pvsync; type: driver    [WORKS]
  #9 1152x864 75.00 1152 1216 1344 1600 864 865 868 900 108000 flags:
     phsync, pvsync; type: driver   [WORKS]
  #10 1280x720 60.00 1280 1390 1430 1650 720 725 730 750 74250 flags:
      phsync, pvsync; type: driver   [WORKS]
  #11 1280x720 59.94 1280 1390 1430 1650 720 725 730 750 74176 flags:
      phsync, pvsync; type: driver   [WORKS]
  #12 1280x720 50.00 1280 1720 1760 1980 720 725 730 750 74250 flags:
      phsync, pvsync; type: driver   [WORKS]
  #13 1024x768 75.03 1024 1040 1136 1312 768 769 772 800 78750 flags:
      phsync, pvsync; type: driver   [WORKS]
  #14 1024x768 60.00 1024 1048 1184 1344 768 771 777 806 65000 flags:
      nhsync, nvsync; type: driver   [WORKS]
  #15 800x600 75.00 800 816 896 1056 600 601 604 625 49500 flags:
      phsync, pvsync; type: driver  [WORKS]
  #16 800x600 60.32 800 840 968 1056 600 601 605 628 40000 flags:
      phsync, pvsync; type: driver  [WORKS]
  #17 720x576 50.00 720 732 796 864 576 581 586 625 27000 flags: nhsync,
      nvsync; type: driver   [WORKS]
  #18 720x480 60.00 720 736 798 858 480 489 495 525 27027 flags: nhsync,
      nvsync; type: driver   [WORKS]
  #19 720x480 59.94 720 736 798 858 480 489 495 525 27000 flags: nhsync,
      nvsync; type: driver   [WORKS]
  #20 640x480 75.00 640 656 720 840 480 481 484 500 31500 flags: nhsync,
      nvsync; type: driver   [WORKS]
  #21 640x480 60.00 640 656 752 800 480 490 492 525 25200 flags: nhsync,
      nvsync; type: driver   [WORKS]
  #22 640x480 59.94 640 656 752 800 480 490 492 525 25175 flags: nhsync,
      nvsync; type: driver   [WORKS]
  #23 720x400 70.08 720 738 846 900 400 412 414 449 28320 flags: nhsync,
      pvsync; type: driver   [DOESN'T WORK]

I believe this is a PHY tuning issue that can be fixed in the new
phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
I plan to continue debugging these modes and will submit follow up fixes
as needed.

The core architectural plumbing is sound and ready for review.

Notes:
- The JH7110 does not have a centralized MAINTAINERS entry like the
  TH1520, and driver maintainership seems fragmented. I have therefore
  added a MAINTAINERS entry for the display subsystem and am willing to
  help with its maintenance.
- I am aware that the new phy-jh7110-inno-hdmi.c driver (patch 12) is a
  near duplicate of the existing phy-rockchip-inno-hdmi.c. This
  duplication is intentional and temporary for this RFC series.  My goal
  is to first get feedback on the overall architecture (the vout-subsystem
  wrapper, the hdmi-mfd split, and the dual-function PHY/CLK driver).

  If this architectural approach is acceptable, I will rework the PHY
  driver for a formal v1 submission. This will involve refactoring the
  common logic from the Rockchip PHY into a generic core driver that both
  the Rockchip and this new StarFive PHY driver will use. 

Many thanks to the Icenowy Zheng who developed a dc8200 driver, as well
as helped me understand how the SoC and the display pipeline works.

[1] - https://lore.kernel.org/all/20250921083446.790374-1-uwu@icenowy.me/
[2] - https://lore.kernel.org/all/20251014131032.49616-1-ziyao@disroot.org/
[3] - https://lore.kernel.org/all/20251016083843.76675-1-andyshrk@163.com/

---
Michal Wilczynski (13):
      dt-bindings: soc: starfive: Add vout-subsystem IP block
      dt-bindings: clock: jh7110: Make power-domain optional
      dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy
      dt-bindings: display: bridge: Add starfive,jh7110-hdmi-controller
      dt-bindings: mfd: Add starfive,jh7110-hdmi-mfd
      drm: bridge: inno_hdmi: Refactor to support regmap and probe
      drm: bridge: inno_hdmi: Add .disable platform operation
      soc: starfive: Add jh7110-vout-subsystem driver
      soc: starfive: Add jh7110-hdmi-mfd driver
      clk: starfive: voutcrg: Update the voutcrg
      drm: bridge: starfive: Add hdmi-controller driver
      phy: starfive: Add jh7110-inno-hdmi-phy driver
      riscv: dts: starfive: jh7110: Update DT for display subsystem

 .../bindings/clock/starfive,jh7110-voutcrg.yaml    |   1 -
 .../starfive,jh7110-inno-hdmi-controller.yaml      | 123 ++++
 .../bindings/mfd/starfive,jh7110-hdmi-mfd.yaml     |  93 +++
 .../phy/starfive,jh7110-inno-hdmi-phy.yaml         |  65 ++
 .../starfive/starfive,jh7110-vout-subsystem.yaml   | 156 +++++
 MAINTAINERS                                        |  12 +
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi    | 119 +++-
 arch/riscv/boot/dts/starfive/jh7110.dtsi           | 111 ++-
 drivers/clk/starfive/clk-starfive-jh7110-vout.c    |  20 +-
 drivers/gpu/drm/bridge/Kconfig                     |  11 +
 drivers/gpu/drm/bridge/Makefile                    |   1 +
 drivers/gpu/drm/bridge/inno-hdmi.c                 | 103 ++-
 drivers/gpu/drm/bridge/jh7110-inno-hdmi.c          | 190 +++++
 drivers/phy/starfive/Kconfig                       |  19 +
 drivers/phy/starfive/Makefile                      |   1 +
 drivers/phy/starfive/phy-jh7110-inno-hdmi.c        | 762 +++++++++++++++++++++
 drivers/soc/Kconfig                                |   1 +
 drivers/soc/Makefile                               |   1 +
 drivers/soc/starfive/Kconfig                       |  42 ++
 drivers/soc/starfive/Makefile                      |   3 +
 drivers/soc/starfive/jh7110-hdmi-mfd.c             |  67 ++
 drivers/soc/starfive/jh7110-vout-subsystem.c       | 117 ++++
 include/drm/bridge/inno_hdmi.h                     |  26 +-
 23 files changed, 1974 insertions(+), 70 deletions(-)
---
base-commit: 0124ee3e78e4adb40db91280f3e468373e48928e
change-id: 20251031-jh7110-clean-send-7d2242118026
prerequisite-message-id: <20251014131032.49616-1-ziyao@disroot.org>
prerequisite-patch-id: eece7563aeac9481fcfbfe431944006a5106820a
prerequisite-patch-id: 24ed71d6319e801eb0155e577e078bfbf9253d30
prerequisite-patch-id: 2d301a1dcaf58d01a78c0aac618a2754639898ba
prerequisite-patch-id: 216741772e16b2ce583edd515bc8fba5d6470dc1
prerequisite-patch-id: 9d34dd523d55d473a6de065142f3a7498f9e8db5
prerequisite-message-id: <20251016083843.76675-1-andyshrk@163.com>
prerequisite-patch-id: 63253dcea8b1bfbde34e453562ac81e9868148d1
prerequisite-patch-id: adc84c1e4a7d682989d857b5c112845e699037c6
prerequisite-message-id: <20250921083446.790374-1-uwu@icenowy.me>
prerequisite-patch-id: 3d309e1448fd7debfbc014acbddf0dfef9205100
prerequisite-patch-id: 8307dd02eb848faa843468b8c2242e8cb9c39347
prerequisite-patch-id: 46e851ad42f8ec46284423c666f0ec44bd947005
prerequisite-patch-id: 1621e926bea2ff1d4ed54df7812a83b8462ba322
prerequisite-patch-id: c06c3b7fdded45495ba6b14c4f03fdab7c30aec3
prerequisite-patch-id: ae59787188ca928a4832dfe268ccfeb87252e6dd
prerequisite-patch-id: 10d8aaec692a647dc1e0e5d6c73c3969df30d78f
prerequisite-patch-id: c483ea581aac29d035a0b84124685e17510b4cf5

Best regards,
-- 
Michal Wilczynski <m.wilczynski@samsung.com>

[PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Michal Wilczynski]

Add the dt-binding documentation for the StarFive JH7110 Video Output
(VOUT) subsystem.

This node acts as a parent for all devices within the VOUT power domain,
including the DC8200 display controller, the VOUTCRG clock generator,
and the HDMI MFD block. Its driver is responsible for managing the
shared power domain and top-level bus clocks for these children.

It is a bit similar to the display subsystem qcom,sdm845-mdss DT node.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 .../starfive/starfive,jh7110-vout-subsystem.yaml   | 156 +++++++++++++++++++++
 MAINTAINERS                                        |   5 +
 2 files changed, 161 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..4ad9423ea139a537b4cfea26b0ed4ed263aa14a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsystem.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 VOUT (Video Output) Subsystem
+
+maintainers:
+  - Michal Wilczynski <m.wilczynski@samsung.com>
+
+description:
+  The JH7110 video output subsystem is an IP block that contains
+  the display controller (DC8200), HDMI controller/PHY, and VOUT
+  clock generator (VOUTCRG).
+
+properties:
+  compatible:
+    const: starfive,jh7110-vout-subsystem
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  ranges: true
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+patternProperties:
+  "^display@[0-9a-f]+$":
+    type: object
+    description: Verisilicon DC8200 Display Controller node.
+
+  "^hdmi@[0-9a-f]+$":
+    type: object
+    description: StarFive HDMI MFD (PHY + Controller) node.
+
+  "^clock-controller@[0-9a-f]+$":
+    type: object
+    description: StarFive VOUT Clock Generator (VOUTCRG) node.
+
+  "^syscon@[0-9a-f]+$":
+    type: object
+    description: StarFive VOUT Syscon node.
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - clocks
+  - resets
+  - ranges
+  - '#address-cells'
+  - '#size-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/power/starfive,jh7110-pmu.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        vout_subsystem: display-subsystem@29400000 {
+            compatible = "starfive,jh7110-vout-subsystem";
+            reg = <0x0 0x29400000 0x0 0x200000>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges;
+
+            power-domains = <&pwrc JH7110_PD_VOUT>;
+            clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
+            resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
+
+            dc8200: display@29400000 {
+                compatible = "verisilicon,dc";
+                reg = <0x0 0x29400000 0x0 0x2800>;
+                interrupts = <95>;
+                clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
+                         <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
+                         <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
+                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
+                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
+                clock-names = "core", "axi", "ahb", "pix0", "pix1";
+                resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
+                         <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
+                         <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
+                reset-names = "axi", "ahb", "core";
+            };
+
+            hdmi_mfd: hdmi@29590000 {
+                compatible = "starfive,jh7110-hdmi-mfd";
+                reg = <0x0 0x29590000 0x0 0x4000>;
+                interrupts = <99>;
+
+                hdmi_phy: phy {
+                    compatible = "starfive,jh7110-inno-hdmi-phy";
+                    clocks = <&xin24m>;
+                    clock-names = "refoclk";
+                    #clock-cells = <0>;
+                    clock-output-names = "hdmi_pclk";
+                    #phy-cells = <0>;
+                };
+
+                hdmi_controller: controller {
+                    compatible = "starfive,jh7110-inno-hdmi-controller";
+                    interrupts = <99>;
+                    clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+                             <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+                             <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
+                             <&hdmi_phy>;
+                    clock-names = "sys", "mclk", "bclk", "pclk";
+                    resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+                    reset-names = "hdmi_tx";
+                    phys = <&hdmi_phy>;
+                    phy-names = "hdmi-phy";
+                };
+            };
+
+            voutcrg: clock-controller@295c0000 {
+                compatible = "starfive,jh7110-voutcrg";
+                reg = <0x0 0x295c0000 0x0 0x10000>;
+                clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+                         <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+                         <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+                         <&hdmi_phy>;
+                clock-names = "vout_src", "vout_top_ahb",
+                              "vout_top_axi", "vout_top_hdmitx0_mclk",
+                              "i2stx0_bclk", "hdmitx0_pixelclk";
+                resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+                reset-names = "vout_top";
+                #clock-cells = <1>;
+                #reset-cells = <1>;
+            };
+        };
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 348caaaa929a519bc0ec5c0c7b587468ef7532d5..99434e54dc39494153677a6ca359d70f2ba2ddb3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24044,6 +24044,11 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
 F:	drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
 
+STARFIVE JH7110 DISPLAY SUBSYSTEM
+M:	Michal Wilczynski <m.wilczynski@samsung.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
+
 STARFIVE JH7110 DPHY RX DRIVER
 M:	Jack Zhu <jack.zhu@starfivetech.com>
 M:	Changhuang Liang <changhuang.liang@starfivetech.com>

-- 
2.34.1

Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 7768 bytes --]

On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski wrote:
> Add the dt-binding documentation for the StarFive JH7110 Video Output
> (VOUT) subsystem.
> 
> This node acts as a parent for all devices within the VOUT power domain,
> including the DC8200 display controller, the VOUTCRG clock generator,
> and the HDMI MFD block. Its driver is responsible for managing the
> shared power domain and top-level bus clocks for these children.
> 
> It is a bit similar to the display subsystem qcom,sdm845-mdss DT node.
> 
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
>  .../starfive/starfive,jh7110-vout-subsystem.yaml   | 156 +++++++++++++++++++++
>  MAINTAINERS                                        |   5 +
>  2 files changed, 161 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..4ad9423ea139a537b4cfea26b0ed4ed263aa14a1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> @@ -0,0 +1,156 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsystem.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 VOUT (Video Output) Subsystem
> +
> +maintainers:
> +  - Michal Wilczynski <m.wilczynski@samsung.com>
> +
> +description:
> +  The JH7110 video output subsystem is an IP block that contains
> +  the display controller (DC8200), HDMI controller/PHY, and VOUT
> +  clock generator (VOUTCRG).
> +
> +properties:
> +  compatible:
> +    const: starfive,jh7110-vout-subsystem
> +
> +  reg:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  ranges: true
> +
> +  '#address-cells':
> +    const: 2
> +
> +  '#size-cells':
> +    const: 2
> +
> +patternProperties:
> +  "^display@[0-9a-f]+$":

Personally I'd like to see these being regular properties, since there's
exactly one possible setup for this.

> +    type: object
> +    description: Verisilicon DC8200 Display Controller node.

Can you add the relevant references here instead of allowing any object?

Cheers,
Conor.

> +
> +  "^hdmi@[0-9a-f]+$":
> +    type: object
> +    description: StarFive HDMI MFD (PHY + Controller) node.
> +
> +  "^clock-controller@[0-9a-f]+$":
> +    type: object
> +    description: StarFive VOUT Clock Generator (VOUTCRG) node.
> +
> +  "^syscon@[0-9a-f]+$":
> +    type: object
> +    description: StarFive VOUT Syscon node.
> +
> +required:
> +  - compatible
> +  - reg
> +  - power-domains
> +  - clocks
> +  - resets
> +  - ranges
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
> +    #include <dt-bindings/power/starfive,jh7110-pmu.h>
> +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        vout_subsystem: display-subsystem@29400000 {
> +            compatible = "starfive,jh7110-vout-subsystem";
> +            reg = <0x0 0x29400000 0x0 0x200000>;
> +            #address-cells = <2>;
> +            #size-cells = <2>;
> +            ranges;
> +
> +            power-domains = <&pwrc JH7110_PD_VOUT>;
> +            clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
> +            resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
> +
> +            dc8200: display@29400000 {
> +                compatible = "verisilicon,dc";
> +                reg = <0x0 0x29400000 0x0 0x2800>;
> +                interrupts = <95>;
> +                clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
> +                         <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
> +                         <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
> +                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
> +                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
> +                clock-names = "core", "axi", "ahb", "pix0", "pix1";
> +                resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
> +                         <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
> +                         <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
> +                reset-names = "axi", "ahb", "core";
> +            };
> +
> +            hdmi_mfd: hdmi@29590000 {
> +                compatible = "starfive,jh7110-hdmi-mfd";
> +                reg = <0x0 0x29590000 0x0 0x4000>;
> +                interrupts = <99>;
> +
> +                hdmi_phy: phy {
> +                    compatible = "starfive,jh7110-inno-hdmi-phy";
> +                    clocks = <&xin24m>;
> +                    clock-names = "refoclk";
> +                    #clock-cells = <0>;
> +                    clock-output-names = "hdmi_pclk";
> +                    #phy-cells = <0>;
> +                };
> +
> +                hdmi_controller: controller {
> +                    compatible = "starfive,jh7110-inno-hdmi-controller";
> +                    interrupts = <99>;
> +                    clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
> +                             <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
> +                             <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
> +                             <&hdmi_phy>;
> +                    clock-names = "sys", "mclk", "bclk", "pclk";
> +                    resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
> +                    reset-names = "hdmi_tx";
> +                    phys = <&hdmi_phy>;
> +                    phy-names = "hdmi-phy";
> +                };
> +            };
> +
> +            voutcrg: clock-controller@295c0000 {
> +                compatible = "starfive,jh7110-voutcrg";
> +                reg = <0x0 0x295c0000 0x0 0x10000>;
> +                clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
> +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
> +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> +                         <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> +                         <&hdmi_phy>;
> +                clock-names = "vout_src", "vout_top_ahb",
> +                              "vout_top_axi", "vout_top_hdmitx0_mclk",
> +                              "i2stx0_bclk", "hdmitx0_pixelclk";
> +                resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
> +                reset-names = "vout_top";
> +                #clock-cells = <1>;
> +                #reset-cells = <1>;
> +            };
> +        };
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 348caaaa929a519bc0ec5c0c7b587468ef7532d5..99434e54dc39494153677a6ca359d70f2ba2ddb3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24044,6 +24044,11 @@ S:	Maintained
>  F:	Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
>  F:	drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
>  
> +STARFIVE JH7110 DISPLAY SUBSYSTEM
> +M:	Michal Wilczynski <m.wilczynski@samsung.com>
> +S:	Maintained
> +F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> +
>  STARFIVE JH7110 DPHY RX DRIVER
>  M:	Jack Zhu <jack.zhu@starfivetech.com>
>  M:	Changhuang Liang <changhuang.liang@starfivetech.com>
> 
> -- 
> 2.34.1
> 

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Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Conor Dooley]

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On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski wrote:
> > Add the dt-binding documentation for the StarFive JH7110 Video Output
> > (VOUT) subsystem.
> > 
> > This node acts as a parent for all devices within the VOUT power domain,
> > including the DC8200 display controller, the VOUTCRG clock generator,
> > and the HDMI MFD block. Its driver is responsible for managing the
> > shared power domain and top-level bus clocks for these children.
> > 
> > It is a bit similar to the display subsystem qcom,sdm845-mdss DT node.
> > 
> > Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> > ---
> >  .../starfive/starfive,jh7110-vout-subsystem.yaml   | 156 +++++++++++++++++++++
> >  MAINTAINERS                                        |   5 +
> >  2 files changed, 161 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> > new file mode 100644
> > index 0000000000000000000000000000000000000000..4ad9423ea139a537b4cfea26b0ed4ed263aa14a1
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> > @@ -0,0 +1,156 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsystem.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH7110 VOUT (Video Output) Subsystem
> > +
> > +maintainers:
> > +  - Michal Wilczynski <m.wilczynski@samsung.com>
> > +
> > +description:
> > +  The JH7110 video output subsystem is an IP block that contains
> > +  the display controller (DC8200), HDMI controller/PHY, and VOUT
> > +  clock generator (VOUTCRG).
> > +
> > +properties:
> > +  compatible:
> > +    const: starfive,jh7110-vout-subsystem
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    maxItems: 1
> > +
> > +  ranges: true
> > +
> > +  '#address-cells':
> > +    const: 2
> > +
> > +  '#size-cells':
> > +    const: 2
> > +
> > +patternProperties:
> > +  "^display@[0-9a-f]+$":
> 
> Personally I'd like to see these being regular properties, since there's
> exactly one possible setup for this.
> 
> > +    type: object
> > +    description: Verisilicon DC8200 Display Controller node.
> 
> Can you add the relevant references here instead of allowing any object?

I don't think that if you did, this would pass the binding checks,
because there's no "verisilicon,dc" binding. I think I saw one in
progress, but without the soc-specific compatible that I am going to
require here - if for no reason other than making sure that the clocks
etc are provided correctly for this device.

> 
> Cheers,
> Conor.
> 
> > +
> > +  "^hdmi@[0-9a-f]+$":
> > +    type: object
> > +    description: StarFive HDMI MFD (PHY + Controller) node.
> > +
> > +  "^clock-controller@[0-9a-f]+$":
> > +    type: object
> > +    description: StarFive VOUT Clock Generator (VOUTCRG) node.
> > +
> > +  "^syscon@[0-9a-f]+$":
> > +    type: object
> > +    description: StarFive VOUT Syscon node.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - power-domains
> > +  - clocks
> > +  - resets
> > +  - ranges
> > +  - '#address-cells'
> > +  - '#size-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
> > +    #include <dt-bindings/power/starfive,jh7110-pmu.h>
> > +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
> > +
> > +    soc {
> > +        #address-cells = <2>;
> > +        #size-cells = <2>;
> > +
> > +        vout_subsystem: display-subsystem@29400000 {
> > +            compatible = "starfive,jh7110-vout-subsystem";
> > +            reg = <0x0 0x29400000 0x0 0x200000>;
> > +            #address-cells = <2>;
> > +            #size-cells = <2>;
> > +            ranges;
> > +
> > +            power-domains = <&pwrc JH7110_PD_VOUT>;
> > +            clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
> > +            resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
> > +
> > +            dc8200: display@29400000 {
> > +                compatible = "verisilicon,dc";
> > +                reg = <0x0 0x29400000 0x0 0x2800>;
> > +                interrupts = <95>;
> > +                clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
> > +                         <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
> > +                         <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
> > +                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
> > +                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
> > +                clock-names = "core", "axi", "ahb", "pix0", "pix1";
> > +                resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
> > +                         <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
> > +                         <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
> > +                reset-names = "axi", "ahb", "core";
> > +            };
> > +
> > +            hdmi_mfd: hdmi@29590000 {
> > +                compatible = "starfive,jh7110-hdmi-mfd";
> > +                reg = <0x0 0x29590000 0x0 0x4000>;
> > +                interrupts = <99>;
> > +
> > +                hdmi_phy: phy {
> > +                    compatible = "starfive,jh7110-inno-hdmi-phy";
> > +                    clocks = <&xin24m>;
> > +                    clock-names = "refoclk";
> > +                    #clock-cells = <0>;
> > +                    clock-output-names = "hdmi_pclk";
> > +                    #phy-cells = <0>;
> > +                };
> > +
> > +                hdmi_controller: controller {
> > +                    compatible = "starfive,jh7110-inno-hdmi-controller";
> > +                    interrupts = <99>;
> > +                    clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
> > +                             <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
> > +                             <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
> > +                             <&hdmi_phy>;
> > +                    clock-names = "sys", "mclk", "bclk", "pclk";
> > +                    resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
> > +                    reset-names = "hdmi_tx";
> > +                    phys = <&hdmi_phy>;
> > +                    phy-names = "hdmi-phy";
> > +                };
> > +            };
> > +
> > +            voutcrg: clock-controller@295c0000 {
> > +                compatible = "starfive,jh7110-voutcrg";
> > +                reg = <0x0 0x295c0000 0x0 0x10000>;
> > +                clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> > +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
> > +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
> > +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> > +                         <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> > +                         <&hdmi_phy>;
> > +                clock-names = "vout_src", "vout_top_ahb",
> > +                              "vout_top_axi", "vout_top_hdmitx0_mclk",
> > +                              "i2stx0_bclk", "hdmitx0_pixelclk";
> > +                resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
> > +                reset-names = "vout_top";
> > +                #clock-cells = <1>;
> > +                #reset-cells = <1>;
> > +            };
> > +        };
> > +    };
> > +
> > +...
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 348caaaa929a519bc0ec5c0c7b587468ef7532d5..99434e54dc39494153677a6ca359d70f2ba2ddb3 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -24044,6 +24044,11 @@ S:	Maintained
> >  F:	Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
> >  F:	drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
> >  
> > +STARFIVE JH7110 DISPLAY SUBSYSTEM
> > +M:	Michal Wilczynski <m.wilczynski@samsung.com>
> > +S:	Maintained
> > +F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> > +
> >  STARFIVE JH7110 DPHY RX DRIVER
> >  M:	Jack Zhu <jack.zhu@starfivetech.com>
> >  M:	Changhuang Liang <changhuang.liang@starfivetech.com>
> > 
> > -- 
> > 2.34.1
> > 



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Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Icenowy Zheng]

在 2025-11-11星期二的 18:36 +0000，Conor Dooley写道：
> On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski wrote:
> > > Add the dt-binding documentation for the StarFive JH7110 Video
> > > Output
> > > (VOUT) subsystem.
> > > 
> > > This node acts as a parent for all devices within the VOUT power
> > > domain,
> > > including the DC8200 display controller, the VOUTCRG clock
> > > generator,
> > > and the HDMI MFD block. Its driver is responsible for managing
> > > the
> > > shared power domain and top-level bus clocks for these children.
> > > 
> > > It is a bit similar to the display subsystem qcom,sdm845-mdss DT
> > > node.
> > > 
> > > Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> > > ---
> > >  .../starfive/starfive,jh7110-vout-subsystem.yaml   | 156
> > > +++++++++++++++++++++
> > >  MAINTAINERS                                        |   5 +
> > >  2 files changed, 161 insertions(+)
> > > 
> > > diff --git
> > > a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-
> > > vout-subsystem.yaml
> > > b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-
> > > vout-subsystem.yaml
> > > new file mode 100644
> > > index
> > > 0000000000000000000000000000000000000000..4ad9423ea139a537b4cfea2
> > > 6b0ed4ed263aa14a1
> > > --- /dev/null
> > > +++
> > > b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-
> > > vout-subsystem.yaml
> > > @@ -0,0 +1,156 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > http://devicetree.org/schemas/soc/starfive/starfive,jh7110-vout-subsystem.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: StarFive JH7110 VOUT (Video Output) Subsystem
> > > +
> > > +maintainers:
> > > +  - Michal Wilczynski <m.wilczynski@samsung.com>
> > > +
> > > +description:
> > > +  The JH7110 video output subsystem is an IP block that contains
> > > +  the display controller (DC8200), HDMI controller/PHY, and VOUT
> > > +  clock generator (VOUTCRG).
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: starfive,jh7110-vout-subsystem
> > > +
> > > +  reg:
> > > +    maxItems: 1
> > > +
> > > +  power-domains:
> > > +    maxItems: 1
> > > +
> > > +  clocks:
> > > +    maxItems: 1
> > > +
> > > +  resets:
> > > +    maxItems: 1
> > > +
> > > +  ranges: true
> > > +
> > > +  '#address-cells':
> > > +    const: 2
> > > +
> > > +  '#size-cells':
> > > +    const: 2
> > > +
> > > +patternProperties:
> > > +  "^display@[0-9a-f]+$":
> > 
> > Personally I'd like to see these being regular properties, since
> > there's
> > exactly one possible setup for this.
> > 
> > > +    type: object
> > > +    description: Verisilicon DC8200 Display Controller node.
> > 
> > Can you add the relevant references here instead of allowing any
> > object?
> 
> I don't think that if you did, this would pass the binding checks,
> because there's no "verisilicon,dc" binding. I think I saw one in
> progress, but without the soc-specific compatible that I am going to
> require here - if for no reason other than making sure that the
> clocks
> etc are provided correctly for this device.

Well I didn't specify any soc-specific compatible because that IP has
its own identification registers.

> 
> > 
> > Cheers,
> > Conor.
> > 
> > > +
> > > +  "^hdmi@[0-9a-f]+$":
> > > +    type: object
> > > +    description: StarFive HDMI MFD (PHY + Controller) node.
> > > +
> > > +  "^clock-controller@[0-9a-f]+$":
> > > +    type: object
> > > +    description: StarFive VOUT Clock Generator (VOUTCRG) node.
> > > +
> > > +  "^syscon@[0-9a-f]+$":
> > > +    type: object
> > > +    description: StarFive VOUT Syscon node.
> > > +
> > > +required:
> > > +  - compatible
> > > +  - reg
> > > +  - power-domains
> > > +  - clocks
> > > +  - resets
> > > +  - ranges
> > > +  - '#address-cells'
> > > +  - '#size-cells'
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > +  - |
> > > +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
> > > +    #include <dt-bindings/power/starfive,jh7110-pmu.h>
> > > +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
> > > +
> > > +    soc {
> > > +        #address-cells = <2>;
> > > +        #size-cells = <2>;
> > > +
> > > +        vout_subsystem: display-subsystem@29400000 {
> > > +            compatible = "starfive,jh7110-vout-subsystem";
> > > +            reg = <0x0 0x29400000 0x0 0x200000>;
> > > +            #address-cells = <2>;
> > > +            #size-cells = <2>;
> > > +            ranges;
> > > +
> > > +            power-domains = <&pwrc JH7110_PD_VOUT>;
> > > +            clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
> > > +            resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
> > > +
> > > +            dc8200: display@29400000 {
> > > +                compatible = "verisilicon,dc";
> > > +                reg = <0x0 0x29400000 0x0 0x2800>;
> > > +                interrupts = <95>;
> > > +                clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
> > > +                         <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
> > > +                         <&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
> > > +                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
> > > +                         <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
> > > +                clock-names = "core", "axi", "ahb", "pix0",
> > > "pix1";
> > > +                resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
> > > +                         <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
> > > +                         <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
> > > +                reset-names = "axi", "ahb", "core";
> > > +            };
> > > +
> > > +            hdmi_mfd: hdmi@29590000 {
> > > +                compatible = "starfive,jh7110-hdmi-mfd";
> > > +                reg = <0x0 0x29590000 0x0 0x4000>;
> > > +                interrupts = <99>;
> > > +
> > > +                hdmi_phy: phy {
> > > +                    compatible = "starfive,jh7110-inno-hdmi-
> > > phy";
> > > +                    clocks = <&xin24m>;
> > > +                    clock-names = "refoclk";
> > > +                    #clock-cells = <0>;
> > > +                    clock-output-names = "hdmi_pclk";
> > > +                    #phy-cells = <0>;
> > > +                };
> > > +
> > > +                hdmi_controller: controller {
> > > +                    compatible = "starfive,jh7110-inno-hdmi-
> > > controller";
> > > +                    interrupts = <99>;
> > > +                    clocks = <&voutcrg
> > > JH7110_VOUTCLK_HDMI_TX_SYS>,
> > > +                             <&voutcrg
> > > JH7110_VOUTCLK_HDMI_TX_MCLK>,
> > > +                             <&voutcrg
> > > JH7110_VOUTCLK_HDMI_TX_BCLK>,
> > > +                             <&hdmi_phy>;
> > > +                    clock-names = "sys", "mclk", "bclk", "pclk";
> > > +                    resets = <&voutcrg
> > > JH7110_VOUTRST_HDMI_TX_HDMI>;
> > > +                    reset-names = "hdmi_tx";
> > > +                    phys = <&hdmi_phy>;
> > > +                    phy-names = "hdmi-phy";
> > > +                };
> > > +            };
> > > +
> > > +            voutcrg: clock-controller@295c0000 {
> > > +                compatible = "starfive,jh7110-voutcrg";
> > > +                reg = <0x0 0x295c0000 0x0 0x10000>;
> > > +                clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> > > +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
> > > +                         <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
> > > +                         <&syscrg
> > > JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> > > +                         <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> > > +                         <&hdmi_phy>;
> > > +                clock-names = "vout_src", "vout_top_ahb",
> > > +                              "vout_top_axi",
> > > "vout_top_hdmitx0_mclk",
> > > +                              "i2stx0_bclk", "hdmitx0_pixelclk";
> > > +                resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
> > > +                reset-names = "vout_top";
> > > +                #clock-cells = <1>;
> > > +                #reset-cells = <1>;
> > > +            };
> > > +        };
> > > +    };
> > > +
> > > +...
> > > diff --git a/MAINTAINERS b/MAINTAINERS
> > > index
> > > 348caaaa929a519bc0ec5c0c7b587468ef7532d5..99434e54dc39494153677a6
> > > ca359d70f2ba2ddb3 100644
> > > --- a/MAINTAINERS
> > > +++ b/MAINTAINERS
> > > @@ -24044,6 +24044,11 @@ S:     Maintained
> > >  F:     Documentation/devicetree/bindings/net/starfive,jh7110-
> > > dwmac.yaml
> > >  F:     drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
> > >  
> > > +STARFIVE JH7110 DISPLAY SUBSYSTEM
> > > +M:     Michal Wilczynski <m.wilczynski@samsung.com>
> > > +S:     Maintained
> > > +F:     Documentation/devicetree/bindings/soc/starfive/starfive,j
> > > h7110-vout-subsystem.yaml
> > > +
> > >  STARFIVE JH7110 DPHY RX DRIVER
> > >  M:     Jack Zhu <jack.zhu@starfivetech.com>
> > >  M:     Changhuang Liang <changhuang.liang@starfivetech.com>
> > > 
> > > -- 
> > > 2.34.1
> > > 
> 
> 

Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Conor Dooley]

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On Wed, Nov 12, 2025 at 02:34:39PM +0800, Icenowy Zheng wrote:
> 在 2025-11-11星期二的 18:36 +0000，Conor Dooley写道：
> > On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> > > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski wrote:
> > > > Add the dt-binding documentation for the StarFive JH7110 Video

> > > > +patternProperties:
> > > > +  "^display@[0-9a-f]+$":
> > > 
> > > Personally I'd like to see these being regular properties, since
> > > there's
> > > exactly one possible setup for this.
> > > 
> > > > +    type: object
> > > > +    description: Verisilicon DC8200 Display Controller node.
> > > 
> > > Can you add the relevant references here instead of allowing any
> > > object?
> > 
> > I don't think that if you did, this would pass the binding checks,
> > because there's no "verisilicon,dc" binding. I think I saw one in
> > progress, but without the soc-specific compatible that I am going to
> > require here - if for no reason other than making sure that the
> > clocks
> > etc are provided correctly for this device.
> 
> Well I didn't specify any soc-specific compatible because that IP has
> its own identification registers.

I still require one because I want to make sure that clocks etc are
handled correctly. You can ignore it in the driver if you wish, but when
the next user comes along with one more or less clock, I want the
jh7110 one to be forced to use the correct configuration.

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Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Icenowy Zheng]

在 2025-11-12星期三的 18:36 +0000，Conor Dooley写道：
> On Wed, Nov 12, 2025 at 02:34:39PM +0800, Icenowy Zheng wrote:
> > 在 2025-11-11星期二的 18:36 +0000，Conor Dooley写道：
> > > On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> > > > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski
> > > > wrote:
> > > > > Add the dt-binding documentation for the StarFive JH7110
> > > > > Video
> 
> > > > > +patternProperties:
> > > > > +  "^display@[0-9a-f]+$":
> > > > 
> > > > Personally I'd like to see these being regular properties,
> > > > since
> > > > there's
> > > > exactly one possible setup for this.
> > > > 
> > > > > +    type: object
> > > > > +    description: Verisilicon DC8200 Display Controller node.
> > > > 
> > > > Can you add the relevant references here instead of allowing
> > > > any
> > > > object?
> > > 
> > > I don't think that if you did, this would pass the binding
> > > checks,
> > > because there's no "verisilicon,dc" binding. I think I saw one in
> > > progress, but without the soc-specific compatible that I am going
> > > to
> > > require here - if for no reason other than making sure that the
> > > clocks
> > > etc are provided correctly for this device.
> > 
> > Well I didn't specify any soc-specific compatible because that IP
> > has
> > its own identification registers.
> 
> I still require one because I want to make sure that clocks etc are
> handled correctly. You can ignore it in the driver if you wish, but
> when
> the next user comes along with one more or less clock, I want the
> jh7110 one to be forced to use the correct configuration.

I don't think for those generic IPs requiring a SoC-specific compatible
is a good idea.

In addition, `vivante,gc` requires no SoC-specific or even model-
number-specific compatible strings too, and `verisilicon,dc` is from
the same IP vendor [1] and features the same set of identification
registers (see also all GC_ prefixed identification registers in [2]).

[1]
https://www.design-reuse.com/news/202527446-verisilicon-completes-acquisition-of-vivante/
[2]
https://github.com/milkv-megrez/rockos-u-boot/blob/c9221cf2fa77d39c0b241ab4b030c708e7ebe279/drivers/video/eswin/eswin_dc_reg.h

Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Conor Dooley]

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On Thu, Nov 13, 2025 at 08:48:33AM +0800, Icenowy Zheng wrote:
> 在 2025-11-12星期三的 18:36 +0000，Conor Dooley写道：
> > On Wed, Nov 12, 2025 at 02:34:39PM +0800, Icenowy Zheng wrote:
> > > 在 2025-11-11星期二的 18:36 +0000，Conor Dooley写道：
> > > > On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> > > > > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski
> > > > > wrote:
> > > > > > Add the dt-binding documentation for the StarFive JH7110
> > > > > > Video
> > 
> > > > > > +patternProperties:
> > > > > > +  "^display@[0-9a-f]+$":
> > > > > 
> > > > > Personally I'd like to see these being regular properties,
> > > > > since
> > > > > there's
> > > > > exactly one possible setup for this.
> > > > > 
> > > > > > +    type: object
> > > > > > +    description: Verisilicon DC8200 Display Controller node.
> > > > > 
> > > > > Can you add the relevant references here instead of allowing
> > > > > any
> > > > > object?
> > > > 
> > > > I don't think that if you did, this would pass the binding
> > > > checks,
> > > > because there's no "verisilicon,dc" binding. I think I saw one in
> > > > progress, but without the soc-specific compatible that I am going
> > > > to
> > > > require here - if for no reason other than making sure that the
> > > > clocks
> > > > etc are provided correctly for this device.
> > > 
> > > Well I didn't specify any soc-specific compatible because that IP
> > > has
> > > its own identification registers.
> > 
> > I still require one because I want to make sure that clocks etc are
> > handled correctly. You can ignore it in the driver if you wish, but
> > when
> > the next user comes along with one more or less clock, I want the
> > jh7110 one to be forced to use the correct configuration.
> 
> I don't think for those generic IPs requiring a SoC-specific compatible
> is a good idea.

I disagree. If things are complex enough to end up with different
numbers of clocks or power-domains etc on different platforms (which I
believe GPUs are) then I want one for validation purposes on platforms I
care about. What you do in the driver is up to you.

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Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block

[Icenowy Zheng]

在 2025-11-13星期四的 19:44 +0000，Conor Dooley写道：
> On Thu, Nov 13, 2025 at 08:48:33AM +0800, Icenowy Zheng wrote:
> > 在 2025-11-12星期三的 18:36 +0000，Conor Dooley写道：
> > > On Wed, Nov 12, 2025 at 02:34:39PM +0800, Icenowy Zheng wrote:
> > > > 在 2025-11-11星期二的 18:36 +0000，Conor Dooley写道：
> > > > > On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote:
> > > > > > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski
> > > > > > wrote:
> > > > > > > Add the dt-binding documentation for the StarFive JH7110
> > > > > > > Video
> > > 
> > > > > > > +patternProperties:
> > > > > > > +  "^display@[0-9a-f]+$":
> > > > > > 
> > > > > > Personally I'd like to see these being regular properties,
> > > > > > since
> > > > > > there's
> > > > > > exactly one possible setup for this.
> > > > > > 
> > > > > > > +    type: object
> > > > > > > +    description: Verisilicon DC8200 Display Controller
> > > > > > > node.
> > > > > > 
> > > > > > Can you add the relevant references here instead of
> > > > > > allowing
> > > > > > any
> > > > > > object?
> > > > > 
> > > > > I don't think that if you did, this would pass the binding
> > > > > checks,
> > > > > because there's no "verisilicon,dc" binding. I think I saw
> > > > > one in
> > > > > progress, but without the soc-specific compatible that I am
> > > > > going
> > > > > to
> > > > > require here - if for no reason other than making sure that
> > > > > the
> > > > > clocks
> > > > > etc are provided correctly for this device.
> > > > 
> > > > Well I didn't specify any soc-specific compatible because that
> > > > IP
> > > > has
> > > > its own identification registers.
> > > 
> > > I still require one because I want to make sure that clocks etc
> > > are
> > > handled correctly. You can ignore it in the driver if you wish,
> > > but
> > > when
> > > the next user comes along with one more or less clock, I want the
> > > jh7110 one to be forced to use the correct configuration.
> > 
> > I don't think for those generic IPs requiring a SoC-specific
> > compatible
> > is a good idea.
> 
> I disagree. If things are complex enough to end up with different
> numbers of clocks or power-domains etc on different platforms (which
> I
> believe GPUs are) then I want one for validation purposes on
> platforms I
> care about. What you do in the driver is up to you.

Well I think Vivante GPUs do have such case -- a "shader" clock that is
only present when 3D support is here. But that binding still contains
only "vivante,gc" and the maintainer of etnaviv rejects extra
compatible strings.

In addition, as the addition of SoC-specific compatible string and the
real DT are usually written by the same person at the same time, I
don't think this introduces any more validation (because when the
author gets things wrong they will just make it wrong at the two
places).

[PATCH RFC 02/13] dt-bindings: clock: jh7110: Make power-domain optional

[Michal Wilczynski]

The voutcrg (Video Output Clock Generator) hardware resides within
the PD_VOUT power domain. In the new display subsystem model,
this power domain is managed by the top-level 'vout-subsystem'
parent driver.

Because the parent driver now handles power management, the voutcrg
node in the device tree no longer needs a 'power-domains' property.
This patch updates the voutcrg binding to reflect this by removing
'power-domains' from the list of required properties.

This fixes a dtbs_check warning that would be triggered by the
updated device tree.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
index af77bd8c86b12e667b79ffbaeae5f8a82e6d3f37..deff69037e5072002e06aa5a899f4488b7264f47 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
@@ -61,7 +61,6 @@ required:
   - resets
   - '#clock-cells'
   - '#reset-cells'
-  - power-domains
 
 additionalProperties: false
 

-- 
2.34.1

Re: [PATCH RFC 02/13] dt-bindings: clock: jh7110: Make power-domain optional

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1674 bytes --]

On Sat, Nov 08, 2025 at 02:04:36AM +0100, Michal Wilczynski wrote:
> The voutcrg (Video Output Clock Generator) hardware resides within
> the PD_VOUT power domain. In the new display subsystem model,
> this power domain is managed by the top-level 'vout-subsystem'
> parent driver.
> 
> Because the parent driver now handles power management, the voutcrg
> node in the device tree no longer needs a 'power-domains' property.
> This patch updates the voutcrg binding to reflect this by removing
> 'power-domains' from the list of required properties.

I don't like how driver-centred your commit message is, but I think you
can just explain this by saying that the appropriate place for this
power domain is in the node that uses it, not some other supplier to the
vout subsystem.

> 
> This fixes a dtbs_check warning that would be triggered by the
> updated device tree.
> 
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
>  Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
> index af77bd8c86b12e667b79ffbaeae5f8a82e6d3f37..deff69037e5072002e06aa5a899f4488b7264f47 100644
> --- a/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
> @@ -61,7 +61,6 @@ required:
>    - resets
>    - '#clock-cells'
>    - '#reset-cells'
> -  - power-domains
>  
>  additionalProperties: false
>  
> 
> -- 
> 2.34.1
> 

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[PATCH RFC 03/13] dt-bindings: phy: Add starfive,jh7110-inno-hdmi-phy

[Michal Wilczynski]

Add the dt-binding for the StarFive JH7110 Innosilicon HDMI PHY.

This device is a child of the starfive,jh7110-hdmi-mfd node. It
functions as both a PHY provider for the controller and as a clock
provider for the variable pixel clock (hdmi_pclk), which it generates
from its refoclk.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 .../phy/starfive,jh7110-inno-hdmi-phy.yaml         | 65 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 66 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..a737ba767d4aa7c6cba197dc0314bdbb163930c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Innosilicon INNO HDMI PHY
+
+maintainers:
+  - Michal Wilczynski <m.wilczynski@samsung.com>
+
+description:
+  The PHY portion of the StarFive JH7110 INNO HDMI IP.
+
+properties:
+  compatible:
+    const: starfive,jh7110-inno-hdmi-phy
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: refoclk
+
+  '#clock-cells':
+    const: 0
+
+  clock-output-names:
+    const: hdmi_pclk
+
+  '#phy-cells':
+    const: 0
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - clock-output-names
+  - '#phy-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        hdmi_mfd: hdmi@29590000 {
+            compatible = "starfive,jh7110-hdmi-mfd";
+            reg = <0x29590000 0x4000>;
+
+            hdmi_phy: phy {
+                compatible = "starfive,jh7110-inno-hdmi-phy";
+                clocks = <&xin24m>;
+                clock-names = "refoclk";
+                #clock-cells = <0>;
+                clock-output-names = "hdmi_pclk";
+                #phy-cells = <0>;
+            };
+        };
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 99434e54dc39494153677a6ca359d70f2ba2ddb3..a75ba7a44ee84db6a75b91c1a0867a37db2ebcdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24047,6 +24047,7 @@ F:	drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
 STARFIVE JH7110 DISPLAY SUBSYSTEM
 M:	Michal Wilczynski <m.wilczynski@samsung.com>
 S:	Maintained
+F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
 F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
 
 STARFIVE JH7110 DPHY RX DRIVER

-- 
2.34.1

[PATCH RFC 04/13] dt-bindings: display: bridge: Add starfive,jh7110-hdmi-controller

[Michal Wilczynski]

Add the dt-binding for the StarFive JH7110 Innosilicon HDMI controller
(DRM bridge).

This device is the second child of the starfive,jh7110-hdmi-mfd node. It
consumes register access clocks (sys, mclk, bclk) from the voutcrg and
both the pixel clock (pclk) and the PHY from its hdmi_phy sibling.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 .../starfive,jh7110-inno-hdmi-controller.yaml      | 123 +++++++++++++++++++++
 MAINTAINERS                                        |   1 +
 2 files changed, 124 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..3707c9dbff9c9fdc0ed7db4720a6dd8eabeeb774
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Innosilicon HDMI Controller
+
+maintainers:
+  - Michal Wilczynski <m.wilczynski@samsung.com>
+
+description:
+  The controller portion of the StarFive JH7110 INNO HDMI IP.
+
+properties:
+  compatible:
+    const: starfive,jh7110-inno-hdmi-controller
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: System clock for register access
+      - description: Module clock
+      - description: Bus clock
+      - description: Pixel clock from PHY
+
+  clock-names:
+    items:
+      - const: sys
+      - const: mclk
+      - const: bclk
+      - const: pclk
+
+  resets:
+    maxItems: 1
+
+  reset-names:
+    const: hdmi_tx
+
+  phys:
+    maxItems: 1
+
+  phy-names:
+    const: hdmi-phy
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/ports
+    description:
+      A graph node with one input port and one output port.
+
+required:
+  - compatible
+  - interrupts
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - phys
+  - phy-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        hdmi_mfd: hdmi@29590000 {
+            compatible = "starfive,jh7110-hdmi-mfd";
+            reg = <0x29590000 0x4000>;
+
+            hdmi_phy: phy {
+                compatible = "starfive,jh7110-inno-hdmi-phy";
+                clocks = <&xin24m>;
+                clock-names = "refoclk";
+                #clock-cells = <0>;
+                clock-output-names = "hdmi_pclk";
+                #phy-cells = <0>;
+            };
+
+            hdmi_controller: controller {
+                compatible = "starfive,jh7110-inno-hdmi-controller";
+                interrupts = <99>;
+                clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+                         <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+                         <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
+                         <&hdmi_phy>;
+                clock-names = "sys", "mclk", "bclk", "pclk";
+                resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+                reset-names = "hdmi_tx";
+                phys = <&hdmi_phy>;
+                phy-names = "hdmi-phy";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+                        hdmi_in: endpoint {
+                            remote-endpoint = <&dpu_out_dpi0>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+                        hdmi_out: endpoint {
+                            remote-endpoint = <&hdmi_con_in>;
+                        };
+                    };
+                };
+            };
+        };
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index a75ba7a44ee84db6a75b91c1a0867a37db2ebcdb..66fab45bbee8c1a5f73d09bb470d28029b8c6139 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24047,6 +24047,7 @@ F:	drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
 STARFIVE JH7110 DISPLAY SUBSYSTEM
 M:	Michal Wilczynski <m.wilczynski@samsung.com>
 S:	Maintained
+F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
 F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
 F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
 

-- 
2.34.1

Re: [PATCH RFC 04/13] dt-bindings: display: bridge: Add starfive,jh7110-hdmi-controller

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 5611 bytes --]

On Sat, Nov 08, 2025 at 02:04:38AM +0100, Michal Wilczynski wrote:
> Add the dt-binding for the StarFive JH7110 Innosilicon HDMI controller
> (DRM bridge).
> 
> This device is the second child of the starfive,jh7110-hdmi-mfd node. It
> consumes register access clocks (sys, mclk, bclk) from the voutcrg and
> both the pixel clock (pclk) and the PHY from its hdmi_phy sibling.
> 
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
>  .../starfive,jh7110-inno-hdmi-controller.yaml      | 123 +++++++++++++++++++++
>  MAINTAINERS                                        |   1 +
>  2 files changed, 124 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..3707c9dbff9c9fdc0ed7db4720a6dd8eabeeb774
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
> @@ -0,0 +1,123 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Innosilicon HDMI Controller
> +
> +maintainers:
> +  - Michal Wilczynski <m.wilczynski@samsung.com>
> +
> +description:
> +  The controller portion of the StarFive JH7110 INNO HDMI IP.
> +
> +properties:
> +  compatible:
> +    const: starfive,jh7110-inno-hdmi-controller
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: System clock for register access
> +      - description: Module clock
> +      - description: Bus clock
> +      - description: Pixel clock from PHY
> +
> +  clock-names:
> +    items:
> +      - const: sys
> +      - const: mclk
> +      - const: bclk
> +      - const: pclk
> +
> +  resets:
> +    maxItems: 1
> +
> +  reset-names:
> +    const: hdmi_tx
> +
> +  phys:
> +    maxItems: 1
> +
> +  phy-names:
> +    const: hdmi-phy
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/ports
> +    description:
> +      A graph node with one input port and one output port.
> +
> +required:
> +  - compatible
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - resets
> +  - reset-names
> +  - phys
> +  - phy-names
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
> +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +    soc {
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        hdmi_mfd: hdmi@29590000 {
> +            compatible = "starfive,jh7110-hdmi-mfd";
> +            reg = <0x29590000 0x4000>;
> +
> +            hdmi_phy: phy {
> +                compatible = "starfive,jh7110-inno-hdmi-phy";
> +                clocks = <&xin24m>;
> +                clock-names = "refoclk";
> +                #clock-cells = <0>;
> +                clock-output-names = "hdmi_pclk";
> +                #phy-cells = <0>;
> +            };
> +
> +            hdmi_controller: controller {

If this stuff doesn't make sense to have an example of without the phy,
then just have an example in the parent and drop it from both child
bindings. Or just drop the parent node and phy, and let the binding
checking tools "invent" a fake phy for checking purposes.

> +                compatible = "starfive,jh7110-inno-hdmi-controller";
> +                interrupts = <99>;
> +                clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
> +                         <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
> +                         <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
> +                         <&hdmi_phy>;
> +                clock-names = "sys", "mclk", "bclk", "pclk";
> +                resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
> +                reset-names = "hdmi_tx";
> +                phys = <&hdmi_phy>;
> +                phy-names = "hdmi-phy";
> +
> +                ports {
> +                    #address-cells = <1>;
> +                    #size-cells = <0>;
> +
> +                    port@0 {
> +                        reg = <0>;
> +                        hdmi_in: endpoint {
> +                            remote-endpoint = <&dpu_out_dpi0>;
> +                        };
> +                    };
> +
> +                    port@1 {
> +                        reg = <1>;
> +                        hdmi_out: endpoint {
> +                            remote-endpoint = <&hdmi_con_in>;
> +                        };
> +                    };
> +                };
> +            };
> +        };
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a75ba7a44ee84db6a75b91c1a0867a37db2ebcdb..66fab45bbee8c1a5f73d09bb470d28029b8c6139 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24047,6 +24047,7 @@ F:	drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
>  STARFIVE JH7110 DISPLAY SUBSYSTEM
>  M:	Michal Wilczynski <m.wilczynski@samsung.com>
>  S:	Maintained
> +F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
>  F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
>  F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
>  
> 
> -- 
> 2.34.1
> 

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[PATCH RFC 05/13] dt-bindings: mfd: Add starfive,jh7110-hdmi-mfd

[Michal Wilczynski]

Add the dt-binding for the StarFive JH7110 HDMI MFD (Multi-Function
Device).

The JH7110 HDMI IP is a monolithic block containing both the digital
controller and analog PHY in a single register space. This binding
defines the MFD parent device, which holds the shared register map and
populates its two children: the PHY and the controller. This is
necessary to resolve a circular clock dependency between the HDMI block
and the VOUT clock generator.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 .../bindings/mfd/starfive,jh7110-hdmi-mfd.yaml     | 93 ++++++++++++++++++++++
 MAINTAINERS                                        |  1 +
 2 files changed, 94 insertions(+)

diff --git a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..2cbfb2b975083240575a0567b06e6cafd542cf9b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/starfive,jh7110-hdmi-mfd.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 HDMI MFD (Controller+PHY)
+
+maintainers:
+  - Michal Wilczynski <m.wilczynski@samsung.com>
+
+description:
+  The StarFive JH7110 HDMI block is a monolithic IP containing both
+  the digital controller logic and the analog PHY logic in a single
+  register space.
+
+properties:
+  compatible:
+    const: starfive,jh7110-hdmi-mfd
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+
+patternProperties:
+  "^phy(@[0-9a-f]+)?$":
+    $ref: ../phy/starfive,jh7110-inno-hdmi-phy.yaml#
+  "^controller(@[0-9a-f]+)?$":
+    $ref: ../display/bridge/starfive,jh7110-inno-hdmi-controller.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive,jh7110-crg.h>
+    #include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+    soc {
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        hdmi_mfd: hdmi@29590000 {
+            compatible = "starfive,jh7110-hdmi-mfd";
+            reg = <0x29590000 0x4000>;
+
+            hdmi_phy: phy {
+                compatible = "starfive,jh7110-inno-hdmi-phy";
+                clocks = <&xin24m>;
+                clock-names = "refoclk";
+                #clock-cells = <0>;
+                clock-output-names = "hdmi_pclk";
+                #phy-cells = <0>;
+            };
+
+            hdmi_controller: controller {
+                compatible = "starfive,jh7110-inno-hdmi-controller";
+                interrupts = <99>;
+                clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+                        <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+                        <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
+                        <&hdmi_phy>;
+                clock-names = "sys", "mclk", "bclk", "pclk";
+                resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+                reset-names = "hdmi_tx";
+                phys = <&hdmi_phy>;
+                phy-names = "hdmi-phy";
+
+                ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+
+                    port@0 {
+                        reg = <0>;
+                        hdmi_in: endpoint {
+                            remote-endpoint = <&dpu_out_dpi0>;
+                        };
+                    };
+
+                    port@1 {
+                        reg = <1>;
+                        hdmi_out: endpoint {
+                            remote-endpoint = <&hdmi_con_in>;
+                        };
+                    };
+                };
+            };
+        };
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 66fab45bbee8c1a5f73d09bb470d28029b8c6139..052876c6538f980f75ff64e78b6ebea460307904 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24048,6 +24048,7 @@ STARFIVE JH7110 DISPLAY SUBSYSTEM
 M:	Michal Wilczynski <m.wilczynski@samsung.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
+F:	Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
 F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
 F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
 

-- 
2.34.1

Re: [PATCH RFC 05/13] dt-bindings: mfd: Add starfive,jh7110-hdmi-mfd

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 5276 bytes --]

On Sat, Nov 08, 2025 at 02:04:39AM +0100, Michal Wilczynski wrote:
> Add the dt-binding for the StarFive JH7110 HDMI MFD (Multi-Function
> Device).
> 
> The JH7110 HDMI IP is a monolithic block containing both the digital
> controller and analog PHY in a single register space. This binding
> defines the MFD parent device, which holds the shared register map and
> populates its two children: the PHY and the controller. This is
> necessary to resolve a circular clock dependency between the HDMI block
> and the VOUT clock generator.
> 
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
>  .../bindings/mfd/starfive,jh7110-hdmi-mfd.yaml     | 93 ++++++++++++++++++++++
>  MAINTAINERS                                        |  1 +
>  2 files changed, 94 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..2cbfb2b975083240575a0567b06e6cafd542cf9b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/starfive,jh7110-hdmi-mfd.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 HDMI MFD (Controller+PHY)
> +
> +maintainers:
> +  - Michal Wilczynski <m.wilczynski@samsung.com>
> +
> +description:
> +  The StarFive JH7110 HDMI block is a monolithic IP containing both
> +  the digital controller logic and the analog PHY logic in a single
> +  register space.
> +
> +properties:
> +  compatible:
> +    const: starfive,jh7110-hdmi-mfd

Drop "mfd" from this please, maybe using "subsystem" is a more suitable
alternative?

> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +
> +patternProperties:
> +  "^phy(@[0-9a-f]+)?$":
> +    $ref: ../phy/starfive,jh7110-inno-hdmi-phy.yaml#
> +  "^controller(@[0-9a-f]+)?$":
> +    $ref: ../display/bridge/starfive,jh7110-inno-hdmi-controller.yaml#

Can you make these absolute references please?

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
> +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +    soc {
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +
> +        hdmi_mfd: hdmi@29590000 {

And drop any unused labels from here.
I definitely thing you could do away with the same example being in
three different places. Maybe one full one here, and two partials in
each of the children?

> +            compatible = "starfive,jh7110-hdmi-mfd";
> +            reg = <0x29590000 0x4000>;
> +
> +            hdmi_phy: phy {
> +                compatible = "starfive,jh7110-inno-hdmi-phy";
> +                clocks = <&xin24m>;
> +                clock-names = "refoclk";
> +                #clock-cells = <0>;
> +                clock-output-names = "hdmi_pclk";
> +                #phy-cells = <0>;
> +            };
> +
> +            hdmi_controller: controller {
> +                compatible = "starfive,jh7110-inno-hdmi-controller";
> +                interrupts = <99>;
> +                clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
> +                        <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
> +                        <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
> +                        <&hdmi_phy>;
> +                clock-names = "sys", "mclk", "bclk", "pclk";
> +                resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
> +                reset-names = "hdmi_tx";
> +                phys = <&hdmi_phy>;
> +                phy-names = "hdmi-phy";
> +
> +                ports {
> +                    #address-cells = <1>;
> +                    #size-cells = <0>;
> +
> +                    port@0 {
> +                        reg = <0>;
> +                        hdmi_in: endpoint {
> +                            remote-endpoint = <&dpu_out_dpi0>;
> +                        };
> +                    };
> +
> +                    port@1 {
> +                        reg = <1>;
> +                        hdmi_out: endpoint {
> +                            remote-endpoint = <&hdmi_con_in>;
> +                        };
> +                    };
> +                };
> +            };
> +        };
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 66fab45bbee8c1a5f73d09bb470d28029b8c6139..052876c6538f980f75ff64e78b6ebea460307904 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24048,6 +24048,7 @@ STARFIVE JH7110 DISPLAY SUBSYSTEM
>  M:	Michal Wilczynski <m.wilczynski@samsung.com>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml
> +F:	Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
>  F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
>  F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
>  
> 
> -- 
> 2.34.1
> 

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[PATCH RFC 06/13] drm: bridge: inno_hdmi: Refactor to support regmap and probe

[Michal Wilczynski]

Refactor the Innosilicon HDMI bridge driver into a library
to support being called by MFD (Multi-Function Device) drivers.
This is necessary for platforms like the StarFive JH7110, where
the HDMI controller and PHY are part of a monolithic MFD block.

This patch makes the following changes:
- The core probing logic is moved into a new exported function,
  inno_hdmi_probe().
- A corresponding exported inno_hdmi_remove() is added.
- The existing inno_hdmi_bind() function is updated to use the
  new inno_hdmi_probe() helper.
- The driver now supports retrieving a shared regmap from a parent
  device, falling back to ioremap if one is not found.
- The struct inno_hdmi definition is moved to a public header
  (include/drm/bridge/inno_hdmi.h) to be accessible by other
  drivers.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 drivers/gpu/drm/bridge/inno-hdmi.c | 99 +++++++++++++++++++++++++++-----------
 include/drm/bridge/inno_hdmi.h     | 25 +++++++++-
 2 files changed, 96 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/inno-hdmi.c
index e46ee4d85044f18407aaa624b4e3dd1a6c5af5cb..9a2370ed2f208caf3dafb4a4d8884516d489263c 100644
--- a/drivers/gpu/drm/bridge/inno-hdmi.c
+++ b/drivers/gpu/drm/bridge/inno-hdmi.c
@@ -395,12 +395,6 @@ enum inno_hdmi_dev_type {
 	RK3128_HDMI,
 };
 
-struct inno_hdmi_phy_config {
-	unsigned long pixelclock;
-	u8 pre_emphasis;
-	u8 voltage_level_control;
-};
-
 struct inno_hdmi_variant {
 	enum inno_hdmi_dev_type dev_type;
 	struct inno_hdmi_phy_config *phy_configs;
@@ -417,19 +411,6 @@ struct inno_hdmi_i2c {
 	struct completion cmp;
 };
 
-struct inno_hdmi {
-	struct device *dev;
-	struct drm_bridge bridge;
-	struct clk *pclk;
-	struct clk *refclk;
-	void __iomem *regs;
-	struct regmap *grf;
-
-	struct inno_hdmi_i2c *i2c;
-	struct i2c_adapter *ddc;
-	const struct inno_hdmi_plat_data *plat_data;
-};
-
 enum {
 	CSC_RGB_0_255_TO_ITU601_16_235_8BIT,
 	CSC_RGB_0_255_TO_ITU709_16_235_8BIT,
@@ -496,11 +477,23 @@ static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi,
 
 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset)
 {
+	u32 val;
+
+	if (hdmi->regmap) {
+		regmap_read(hdmi->regmap, offset * 4, &val);
+		return val;
+	}
+
 	return readl_relaxed(hdmi->regs + (offset) * 0x04);
 }
 
 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val)
 {
+	if (hdmi->regmap) {
+		regmap_write(hdmi->regmap, offset * 4, val);
+		return;
+	}
+
 	writel_relaxed(val, hdmi->regs + (offset) * 0x04);
 }
 
@@ -1082,11 +1075,24 @@ static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi)
 	return adap;
 }
 
-struct inno_hdmi *inno_hdmi_bind(struct device *dev,
-				 struct drm_encoder *encoder,
-				 const struct inno_hdmi_plat_data *plat_data)
+/**
+ * inno_hdmi_probe - Internal helper to perform common setup
+ * @pdev: platform device
+ * @plat_data: SoC-specific platform data
+ *
+ * This function handles all the common hardware setup: allocating the main
+ * struct, mapping registers, getting clocks, initializing the hardware,
+ * setting up the IRQ, and initializing the DDC adapter and bridge struct.
+ * It returns a pointer to the inno_hdmi struct on success, or an ERR_PTR
+ * on failure.
+ *
+ * This function is used by modern, decoupled MFD/glue drivers. It registers
+ * the bridge but does not attach it.
+ */
+struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev,
+					 const struct inno_hdmi_plat_data *plat_data)
 {
-	struct platform_device *pdev = to_platform_device(dev);
+	struct device *dev = &pdev->dev;
 	struct inno_hdmi *hdmi;
 	int irq;
 	int ret;
@@ -1103,9 +1109,21 @@ struct inno_hdmi *inno_hdmi_bind(struct device *dev,
 	hdmi->dev = dev;
 	hdmi->plat_data = plat_data;
 
-	hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(hdmi->regs))
-		return ERR_CAST(hdmi->regs);
+	/*
+	 * MFD Support: Check if parent provides a regmap.
+	 * If so, use it. Otherwise, fall back to ioremap.
+	 */
+	if (dev->parent)
+		hdmi->regmap = dev_get_regmap(dev->parent, NULL);
+
+	if (hdmi->regmap) {
+		dev_info(dev, "Using MFD regmap for registers\n");
+	} else {
+		dev_info(dev, "Falling back to ioremap for registers\n");
+		hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
+		if (IS_ERR(hdmi->regs))
+			return ERR_CAST(hdmi->regs);
+	}
 
 	hdmi->pclk = devm_clk_get_enabled(hdmi->dev, "pclk");
 	if (IS_ERR(hdmi->pclk)) {
@@ -1149,7 +1167,34 @@ struct inno_hdmi *inno_hdmi_bind(struct device *dev,
 	if (ret)
 		return ERR_PTR(ret);
 
-	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+	return hdmi;
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_probe);
+
+/**
+ * inno_hdmi_remove - Remove a bridge created by inno_hdmi_probe
+ * @hdmi: The inno_hdmi instance to remove
+ */
+void inno_hdmi_remove(struct inno_hdmi *hdmi)
+{
+	drm_bridge_remove(&hdmi->bridge);
+}
+EXPORT_SYMBOL_GPL(inno_hdmi_remove);
+
+struct inno_hdmi *inno_hdmi_bind(struct device *dev,
+				 struct drm_encoder *encoder,
+				 const struct inno_hdmi_plat_data *plat_data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct inno_hdmi *hdmi;
+	int ret;
+
+	hdmi = inno_hdmi_probe(pdev, plat_data);
+	if (IS_ERR(hdmi))
+		return hdmi;
+
+	ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL,
+				DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 	if (ret)
 		return ERR_PTR(ret);
 
diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h
index 8b39655212e247d9ca7b1f220f970df1fb6afe13..019680622324197e046a1c606ec25aabe95537b4 100644
--- a/include/drm/bridge/inno_hdmi.h
+++ b/include/drm/bridge/inno_hdmi.h
@@ -6,10 +6,13 @@
 #ifndef __INNO_HDMI__
 #define __INNO_HDMI__
 
+#include <drm/drm_bridge.h>
+
 struct device;
 struct drm_encoder;
 struct drm_display_mode;
-struct inno_hdmi;
+struct i2c_adapter;
+struct inno_hdmi_i2c;
 
 struct inno_hdmi_plat_ops {
 	void (*enable)(struct device *pdev, struct drm_display_mode *mode);
@@ -27,7 +30,27 @@ struct inno_hdmi_plat_data {
 	struct inno_hdmi_phy_config *default_phy_config;
 };
 
+struct inno_hdmi {
+	struct device *dev;
+	struct drm_bridge bridge;
+	struct clk *pclk;
+	struct clk *refclk;
+	void __iomem *regs;
+	struct regmap *regmap;
+	struct regmap *grf;
+
+	struct i2c_adapter *ddc;
+	struct inno_hdmi_i2c *i2c;
+	const struct inno_hdmi_plat_data *plat_data;
+};
+
 struct inno_hdmi *inno_hdmi_bind(struct device *pdev,
 				 struct drm_encoder *encoder,
 				 const struct inno_hdmi_plat_data *plat_data);
+
+struct inno_hdmi *inno_hdmi_probe(struct platform_device *pdev,
+				 const struct inno_hdmi_plat_data *plat_data);
+
+void inno_hdmi_remove(struct inno_hdmi *hdmi);
+
 #endif /* __INNO_HDMI__ */

-- 
2.34.1

[PATCH RFC 07/13] drm: bridge: inno_hdmi: Add .disable platform operation

[Michal Wilczynski]

The Innosilicon HDMI driver supports platform-specific behavior through
the `inno_hdmi_plat_ops`. While it provides an `.enable` hook for
platform-specific power up sequences (like enabling PHYs), it lacks a
corresponding hook for power down.

This patch adds a new `.disable` op to the `inno_hdmi_plat_ops` struct
and calls it at the beginning of `inno_hdmi_bridge_atomic_disable()`.

This allows platform specific drivers, such as the StarFive JH7110,
to implement their own power down sequence (e.g., calling
phy_power_off() and clk_disable_unprepare()).

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 drivers/gpu/drm/bridge/inno-hdmi.c | 4 ++++
 include/drm/bridge/inno_hdmi.h     | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/bridge/inno-hdmi.c b/drivers/gpu/drm/bridge/inno-hdmi.c
index 9a2370ed2f208caf3dafb4a4d8884516d489263c..37ed7169bfce755cc5bddca16c78d4f112ea33e6 100644
--- a/drivers/gpu/drm/bridge/inno-hdmi.c
+++ b/drivers/gpu/drm/bridge/inno-hdmi.c
@@ -887,6 +887,10 @@ static void inno_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
 					    struct drm_atomic_state *state)
 {
 	struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge);
+	const struct inno_hdmi_plat_ops *plat_ops = hdmi->plat_data->ops;
+
+	if (plat_ops && plat_ops->disable)
+		plat_ops->disable(hdmi->dev);
 
 	inno_hdmi_standby(hdmi);
 }
diff --git a/include/drm/bridge/inno_hdmi.h b/include/drm/bridge/inno_hdmi.h
index 019680622324197e046a1c606ec25aabe95537b4..ca554c525fd6bf63a4a8b9721e967bc473492f0a 100644
--- a/include/drm/bridge/inno_hdmi.h
+++ b/include/drm/bridge/inno_hdmi.h
@@ -16,6 +16,7 @@ struct inno_hdmi_i2c;
 
 struct inno_hdmi_plat_ops {
 	void (*enable)(struct device *pdev, struct drm_display_mode *mode);
+	void (*disable)(struct device *pdev);
 };
 
 struct inno_hdmi_phy_config {

-- 
2.34.1

[PATCH RFC 08/13] soc: starfive: Add jh7110-vout-subsystem driver

[Michal Wilczynski]

Add the wrapper driver for the StarFive JH7110 VOUT subsystem.

This driver is responsible for managing the shared resources for all
video output devices. It enables the PD_VOUT power domain, enables the
top-level NoC bus clock, and deasserts the main bus reset.

Once these resources are active, it calls of_platform_populate() to
create and probe the child devices (DC8200, VOUTCRG, HDMI MFD) that
reside within this subsystem.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 MAINTAINERS                                  |   1 +
 drivers/soc/Kconfig                          |   1 +
 drivers/soc/Makefile                         |   1 +
 drivers/soc/starfive/Kconfig                 |  25 ++++++
 drivers/soc/starfive/Makefile                |   2 +
 drivers/soc/starfive/jh7110-vout-subsystem.c | 117 +++++++++++++++++++++++++++
 6 files changed, 147 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 052876c6538f980f75ff64e78b6ebea460307904..74e562a6b57ac9f776c4be2d6f0977c62bc03d46 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24051,6 +24051,7 @@ F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-co
 F:	Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
 F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
 F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
+F:	drivers/soc/starfive/jh7110-vout-subsystem.c
 
 STARFIVE JH7110 DPHY RX DRIVER
 M:	Jack Zhu <jack.zhu@starfivetech.com>
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index a2d65adffb8052c0ac5a6b60bf33fa9c644701bb..b3b01fc38139d98076c14f626a42ae3b7ef7c5d6 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig"
 source "drivers/soc/rockchip/Kconfig"
 source "drivers/soc/samsung/Kconfig"
 source "drivers/soc/sophgo/Kconfig"
+source "drivers/soc/starfive/Kconfig"
 source "drivers/soc/sunxi/Kconfig"
 source "drivers/soc/tegra/Kconfig"
 source "drivers/soc/ti/Kconfig"
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index c9e689080ceb759384f690c2b65a82b3cb451c74..009f85ff891a15e0455f92c5d5a4059d8b1fcd3f 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -30,6 +30,7 @@ obj-y				+= renesas/
 obj-y				+= rockchip/
 obj-$(CONFIG_SOC_SAMSUNG)	+= samsung/
 obj-y				+= sophgo/
+obj-y				+= starfive/
 obj-y				+= sunxi/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
 obj-y				+= ti/
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
new file mode 100644
index 0000000000000000000000000000000000000000..47e82aaaa7e0af9d5c718166601c59c1ca683d3a
--- /dev/null
+++ b/drivers/soc/starfive/Kconfig
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Starfive SoC drivers
+#
+
+if ARCH_STARFIVE || COMPILE_TEST
+menu "Starfive SoC drivers"
+
+config SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM
+	tristate "StarFive JH7110 VOUT Subsystem Manager"
+	help
+	  Enable this option to support the VOUT (Video Output) subsystem on
+	  the StarFive JH7110 SoC.
+
+	  This driver acts as a parent wrapper for all display related
+	  hardware blocks (DC8200, VOUTCRG, HDMI MFD). Its primary
+	  responsibility is to manage the shared PD_VOUT power domain,
+	  enabling power, clocks, and resets for the entire subsystem
+	  before the individual child drivers are probed.
+
+	  This is essential for the display hardware to be detected and
+	  to function correctly.
+
+endmenu
+endif
diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..17081cd67635b02f495230b117c9acb691ef33ba
--- /dev/null
+++ b/drivers/soc/starfive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM) += jh7110-vout-subsystem.o
diff --git a/drivers/soc/starfive/jh7110-vout-subsystem.c b/drivers/soc/starfive/jh7110-vout-subsystem.c
new file mode 100644
index 0000000000000000000000000000000000000000..a67fd1cbac6b97c0c78c5dff444450579beca91d
--- /dev/null
+++ b/drivers/soc/starfive/jh7110-vout-subsystem.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * Author: Michal Wilczynski <m.wilczynski@samsung.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+static void devm_clk_disable_unprepare(void *data)
+{
+	struct clk *clk = data;
+
+	clk_disable_unprepare(clk);
+}
+
+static void devm_reset_control_assert(void *data)
+{
+	struct reset_control *rst = data;
+
+	reset_control_assert(rst);
+}
+
+static int jh7110_vout_subsystem_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct clk *bus_clk;
+	struct reset_control *bus_rst;
+	int ret;
+
+	bus_clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(bus_clk))
+		return dev_err_probe(dev, PTR_ERR(bus_clk), "Failed to get bus clock\n");
+
+	bus_rst = devm_reset_control_get_exclusive(dev, NULL);
+	if (IS_ERR(bus_rst))
+		return dev_err_probe(dev, PTR_ERR(bus_rst), "Failed to get bus reset\n");
+
+	pm_runtime_enable(dev);
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0) {
+		dev_err(dev, "Failed to enable power domain: %d\n", ret);
+		pm_runtime_disable(dev);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(bus_clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable bus clock: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	ret = devm_add_action_or_reset(dev, devm_clk_disable_unprepare, bus_clk);
+	if (ret) {
+		dev_err(dev, "Failed to register clk disable action: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	ret = reset_control_deassert(bus_rst);
+	if (ret) {
+		dev_err(dev, "Failed to deassert bus reset: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	ret = devm_add_action_or_reset(dev, devm_reset_control_assert, bus_rst);
+	if (ret) {
+		dev_err(dev, "Failed to register reset assert action: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	dev_info(dev, "VOUT subsystem bus interface is powered on\n");
+
+	ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
+	if (ret) {
+		dev_err(dev, "Failed to populate child devices: %d\n", ret);
+		goto err_pm_put;
+	}
+
+	return 0;
+
+err_pm_put:
+	pm_runtime_put_sync(dev);
+	pm_runtime_disable(dev);
+	return ret;
+}
+
+static void jh7110_vout_subsystem_remove(struct platform_device *pdev)
+{
+	of_platform_depopulate(&pdev->dev);
+
+	pm_runtime_put_sync(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+}
+
+static const struct of_device_id vout_subsystem_of_match[] = {
+	{ .compatible = "starfive,jh7110-vout-subsystem", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, vout_subsystem_of_match);
+
+static struct platform_driver jh7110_vout_subsystem_driver = {
+	.probe = jh7110_vout_subsystem_probe,
+	.remove = jh7110_vout_subsystem_remove,
+	.driver = {
+		.name = "jh7110-vout-subsystem",
+		.of_match_table = vout_subsystem_of_match,
+	},
+};
+module_platform_driver(jh7110_vout_subsystem_driver);
+
+MODULE_AUTHOR("Michal Wilczynski <m.wilczynski@samsung.com>");
+MODULE_DESCRIPTION("StarFive JH7110 VOUT Subsystem Manager");
+MODULE_LICENSE("GPL");

-- 
2.34.1

Re: [PATCH RFC 08/13] soc: starfive: Add jh7110-vout-subsystem driver

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2067 bytes --]

On Sat, Nov 08, 2025 at 02:04:42AM +0100, Michal Wilczynski wrote:
> Add the wrapper driver for the StarFive JH7110 VOUT subsystem.
> 
> This driver is responsible for managing the shared resources for all
> video output devices. It enables the PD_VOUT power domain, enables the
> top-level NoC bus clock, and deasserts the main bus reset.
> 
> Once these resources are active, it calls of_platform_populate() to
> create and probe the child devices (DC8200, VOUTCRG, HDMI MFD) that
> reside within this subsystem.
> 
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
>  MAINTAINERS                                  |   1 +
>  drivers/soc/Kconfig                          |   1 +
>  drivers/soc/Makefile                         |   1 +
>  drivers/soc/starfive/Kconfig                 |  25 ++++++
>  drivers/soc/starfive/Makefile                |   2 +
>  drivers/soc/starfive/jh7110-vout-subsystem.c | 117 +++++++++++++++++++++++++++
>  6 files changed, 147 insertions(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 052876c6538f980f75ff64e78b6ebea460307904..74e562a6b57ac9f776c4be2d6f0977c62bc03d46 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -24051,6 +24051,7 @@ F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-co
>  F:	Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
>  F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
>  F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
> +F:	drivers/soc/starfive/jh7110-vout-subsystem.c

The parent directory that you've created here for the driver (or created
in a different patch) should probably be added to the "RISC-V MISC SOC
SUPPORT" entry, along with the binding directory. Otherwise I'm probably
not going to see the patches for the former (Emil maintains the
plarform, but for $reasons I'm the one who applies patches and sends the
PRs to Arnd). Think it used to be there, but got removed when the last
(only?) driver was moved out.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

[PATCH RFC 09/13] soc: starfive: Add jh7110-hdmi-mfd driver

[Michal Wilczynski]

Add the MFD parent driver for the monolithic JH7110 HDMI IP block.

This driver binds to the starfive,jh7110-hdmi-mfd node. Its sole
responsibility is to map the entire shared register block, create a
regmap with the correct configuration, and then call
devm_of_platform_populate() to create its hdmi_phy and hdmi_controller
child devices.

The child drivers will retrieve the shared regmap from this parent
driver.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 MAINTAINERS                            |  1 +
 drivers/soc/starfive/Kconfig           | 17 +++++++++
 drivers/soc/starfive/Makefile          |  1 +
 drivers/soc/starfive/jh7110-hdmi-mfd.c | 67 ++++++++++++++++++++++++++++++++++
 4 files changed, 86 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 74e562a6b57ac9f776c4be2d6f0977c62bc03d46..f1867018ee92fb754689934f6d238f9c9f185161 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24051,6 +24051,7 @@ F:	Documentation/devicetree/bindings/display/bridge/starfive,jh7110-inno-hdmi-co
 F:	Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-mfd.yaml
 F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
 F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
+F:	drivers/soc/starfive/jh7110-hdmi-mfd.c
 F:	drivers/soc/starfive/jh7110-vout-subsystem.c
 
 STARFIVE JH7110 DPHY RX DRIVER
diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig
index 47e82aaaa7e0af9d5c718166601c59c1ca683d3a..e0232988050bd250529e373243f5ae1851b26135 100644
--- a/drivers/soc/starfive/Kconfig
+++ b/drivers/soc/starfive/Kconfig
@@ -21,5 +21,22 @@ config SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM
 	  This is essential for the display hardware to be detected and
 	  to function correctly.
 
+config SOC_STARFIVE_JH7110_HDMI_MFD
+    tristate "StarFive JH7110 HDMI MFD Driver"
+    depends on OF
+    help
+	  This option enables the MFD (Multi-Function Device) parent driver
+	  for the monolithic StarFive JH7110 HDMI peripheral.
+
+	  The JH7110 HDMI IP block contains both the digital controller
+	  (DRM bridge) and the analog PHY (clock/phy provider) logic within
+	  a single shared register space.
+
+	  This MFD driver acts as a wrapper. Its only job is to map the
+	  shared registers and create separate logical child devices
+	  for the "PHY" and the "controller". This is required to
+	  correctly manage resources and break a circular clock dependency
+	  between the PHY and the VOUT clock generator at probe time.
+
 endmenu
 endif
diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile
index 17081cd67635b02f495230b117c9acb691ef33ba..15a4e8ca358f2bfe3ed0d00fea948edac4ccbd75 100644
--- a/drivers/soc/starfive/Makefile
+++ b/drivers/soc/starfive/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
 obj-$(CONFIG_SOC_STARFIVE_JH7110_VOUT_SUBSYSTEM) += jh7110-vout-subsystem.o
+obj-$(CONFIG_SOC_STARFIVE_JH7110_HDMI_MFD) += jh7110-hdmi-mfd.o
diff --git a/drivers/soc/starfive/jh7110-hdmi-mfd.c b/drivers/soc/starfive/jh7110-hdmi-mfd.c
new file mode 100644
index 0000000000000000000000000000000000000000..73f1d58b280d3efb770c2dcf1ac934e7a6a51c64
--- /dev/null
+++ b/drivers/soc/starfive/jh7110-hdmi-mfd.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MFD Driver for StarFive JH7110 HDMI
+ *
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * Author: Michal Wilczynski <m.wilczynski@samsung.com>
+ *
+ * This driver binds to the monolithic HDMI block and creates separate
+ * logical platform devices for the HDMI Controller (bridge) and the
+ * HDMI PHY (clock/phy provider), allowing them to share a single regmap
+ * and breaking the probing circular dependency.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+static const struct regmap_config starfive_hdmi_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 8,
+	.max_register = 0x4000,
+};
+
+static int starfive_hdmi_mfd_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	void __iomem *regs;
+	struct regmap *regmap;
+	int ret;
+
+	regs = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(regs))
+		return PTR_ERR(regs);
+
+	regmap = devm_regmap_init_mmio(dev, regs,
+				       &starfive_hdmi_regmap_config);
+	if (IS_ERR(regmap))
+		return dev_err_probe(dev, PTR_ERR(regmap),
+				     "Failed to init shared regmap\n");
+
+	ret = devm_of_platform_populate(dev);
+	if (ret)
+		dev_err(dev, "Failed to populate child devices: %d\n", ret);
+
+	return ret;
+}
+
+static const struct of_device_id starfive_hdmi_mfd_of_match[] = {
+	{ .compatible = "starfive,jh7110-hdmi-mfd", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, starfive_hdmi_mfd_of_match);
+
+static struct platform_driver starfive_hdmi_mfd_driver = {
+	.probe = starfive_hdmi_mfd_probe,
+	.driver = {
+		.name = "starfive-hdmi-mfd",
+		.of_match_table = starfive_hdmi_mfd_of_match,
+	},
+};
+module_platform_driver(starfive_hdmi_mfd_driver);
+
+MODULE_AUTHOR("Michal Wilczynski <m.wilczynski@samsung.com>");
+MODULE_DESCRIPTION("StarFive JH7110 HDMI MFD Driver");
+MODULE_LICENSE("GPL");

-- 
2.34.1

[PATCH RFC 10/13] clk: starfive: voutcrg: Update the voutcrg

[Michal Wilczynski]

Update the voutcrg driver to support the new MFD HDMI model. The
hdmitx0_pixelclk is now supplied by the starfive-inno-hdmi-phy driver.

This patch updates the MUX definitions for dc8200_pix0 and dc8200_pix1
to add the CLK_SET_RATE_PARENT flag. This allows the dc8200 driver to
set the pixel clock rate, which will be correctly propagated to the
parent.

Remove the pm_runtime calls, as power management is now handled by the
vout-subsystem parent wrapper.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 drivers/clk/starfive/clk-starfive-jh7110-vout.c | 20 ++------------------
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
index bad20d5d794a72f071b4d547b7304786a8ba9afa..6175f94ff4113088696ba1dfbe5080609733fb76 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -9,7 +9,6 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
 #include <linux/reset.h>
 
 #include <dt-bindings/clock/starfive,jh7110-crg.h>
@@ -40,10 +39,10 @@ static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
 	JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
 	JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
 	JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
-	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
+	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", CLK_SET_RATE_PARENT, 2,
 		    JH7110_VOUTCLK_DC8200_PIX,
 		    JH7110_VOUTCLK_HDMITX0_PIXELCLK),
-	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
+	JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", CLK_SET_RATE_PARENT, 2,
 		    JH7110_VOUTCLK_DC8200_PIX,
 		    JH7110_VOUTCLK_HDMITX0_PIXELCLK),
 	/* LCD */
@@ -133,12 +132,6 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
 		return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
 	dev_set_drvdata(priv->dev, top);
 
-	/* enable power domain and clocks */
-	pm_runtime_enable(priv->dev);
-	ret = pm_runtime_resume_and_get(priv->dev);
-	if (ret < 0)
-		return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
-
 	ret = jh7110_vout_top_rst_init(priv);
 	if (ret)
 		goto err_exit;
@@ -194,17 +187,9 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
 	return 0;
 
 err_exit:
-	pm_runtime_put_sync(priv->dev);
-	pm_runtime_disable(priv->dev);
 	return ret;
 }
 
-static void jh7110_voutcrg_remove(struct platform_device *pdev)
-{
-	pm_runtime_put_sync(&pdev->dev);
-	pm_runtime_disable(&pdev->dev);
-}
-
 static const struct of_device_id jh7110_voutcrg_match[] = {
 	{ .compatible = "starfive,jh7110-voutcrg" },
 	{ /* sentinel */ }
@@ -213,7 +198,6 @@ MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
 
 static struct platform_driver jh7110_voutcrg_driver = {
 	.probe = jh7110_voutcrg_probe,
-	.remove = jh7110_voutcrg_remove,
 	.driver = {
 		.name = "clk-starfive-jh7110-vout",
 		.of_match_table = jh7110_voutcrg_match,

-- 
2.34.1

[PATCH RFC 11/13] drm: bridge: starfive: Add hdmi-controller driver

[Michal Wilczynski]

Add the HDMI controller (bridge) driver for the StarFive JH7110.

This driver binds to the starfive,jh7110-inno-hdmi-controller MFD child.
It gets its shared regmap from the MFD parent and its clocks (sys, mclk,
bclk) from voutcrg. It consumes the pclk (pixel clock) and PHY from its
hdmi_phy sibling.

The driver calls the generic inno_hdmi_probe function and passes the
shared regmap to it, registering as a DRM bridge. The .enable hook is
responsible for setting the PHY's pixel clock rate via clk_set_rate()
and powering on the PHY via phy_power_on().

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 MAINTAINERS                               |   1 +
 drivers/gpu/drm/bridge/Kconfig            |  11 ++
 drivers/gpu/drm/bridge/Makefile           |   1 +
 drivers/gpu/drm/bridge/jh7110-inno-hdmi.c | 190 ++++++++++++++++++++++++++++++
 4 files changed, 203 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index f1867018ee92fb754689934f6d238f9c9f185161..5984b83e55aeadb59c25a6e8f01057fb9d982d81 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24053,6 +24053,7 @@ F:	Documentation/devicetree/bindings/phy/starfive,jh7110-inno-hdmi-phy.yaml
 F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem.yaml
 F:	drivers/soc/starfive/jh7110-hdmi-mfd.c
 F:	drivers/soc/starfive/jh7110-vout-subsystem.c
+F:	drivers/gpu/drm/bridge/jh7110-inno-hdmi.c
 
 STARFIVE JH7110 DPHY RX DRIVER
 M:	Jack Zhu <jack.zhu@starfivetech.com>
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index a5b8df9655ba70c6d653183780089258946b0e5a..2bf97ec0096ed093ed078b48300d9aa12088c486 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -323,6 +323,17 @@ config DRM_SIMPLE_BRIDGE
 	  Support for non-programmable DRM bridges, such as ADI ADV7123, TI
 	  THS8134 and THS8135 or passive resistor ladder DACs.
 
+config DRM_STARFIVE_JH7110_INNO_HDMI
+	tristate "Starfive JH7110 Innosilicon HDMI bridge"
+	depends on OF
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	select DRM_INNO_HDMI
+	help
+	  Enable support for the StarFive JH7110 specific implementation
+	  of the Innosilicon HDMI controller.
+	  This driver acts as a glue layer between the JH7110 HDMI MFD
+	  parent driver and the generic Innosilicon HDMI bridge driver.
+
 config DRM_THINE_THC63LVD1024
 	tristate "Thine THC63LVD1024 LVDS decoder bridge"
 	depends on OF
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 4bc2236c8ae9169ac998e9d0448badff457cabaa..b2f5835ec05bcbb4367499d1cebb5403d7b9f247 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o
 obj-$(CONFIG_DRM_SII902X) += sii902x.o
 obj-$(CONFIG_DRM_SII9234) += sii9234.o
 obj-$(CONFIG_DRM_SIMPLE_BRIDGE) += simple-bridge.o
+obj-$(CONFIG_DRM_STARFIVE_JH7110_INNO_HDMI) += jh7110-inno-hdmi.o
 obj-$(CONFIG_DRM_THEAD_TH1520_DW_HDMI) += th1520-dw-hdmi.o
 obj-$(CONFIG_DRM_THINE_THC63LVD1024) += thc63lvd1024.o
 obj-$(CONFIG_DRM_TOSHIBA_TC358762) += tc358762.o
diff --git a/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c b/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c
new file mode 100644
index 0000000000000000000000000000000000000000..8d3e1c3e736b801882b1b057199fc341142bba52
--- /dev/null
+++ b/drivers/gpu/drm/bridge/jh7110-inno-hdmi.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) StarFive Technology Co., Ltd.
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * Author: Michal Wilczynski <m.wilczynski@samsung.com>
+ *
+ * HDMI Controller (bridge) driver for StarFive JH7110 MFD.
+ */
+
+#include <linux/clk.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#include <drm/bridge/inno_hdmi.h>
+
+enum stf_hdmi_ctrl_clocks { CLK_SYS = 0, CLK_M, CLK_B, CLK_PCLK, CLK_CTRL_NUM };
+
+struct stf_inno_hdmi_controller {
+	struct inno_hdmi *inno;
+	struct device *dev;
+	struct clk_bulk_data clks[CLK_CTRL_NUM];
+	struct reset_control *tx_rst;
+	struct phy *phy;
+};
+
+static void inno_hdmi_starfive_enable(struct device *dev,
+				      struct drm_display_mode *mode)
+{
+	struct stf_inno_hdmi_controller *ctrl = dev_get_drvdata(dev);
+	int ret;
+
+	/*
+	 * 1. Set the pixel clock rate. This calls the PHY driver's .set_rate op.
+	 */
+	ret = clk_set_rate(ctrl->clks[CLK_PCLK].clk, mode->clock * 1000);
+	if (ret) {
+		dev_err(dev, "Failed to set pclk rate %d: %d\n",
+			mode->clock * 1000, ret);
+		return;
+	}
+
+	/*
+	 * 2. Enable the pixel clock. This calls the PHY driver's .prepare op.
+	 */
+	ret = clk_prepare_enable(ctrl->clks[CLK_PCLK].clk);
+	if (ret) {
+		dev_err(dev, "Failed to enable pclk: %d\n", ret);
+		return;
+	}
+
+	/*
+	 * 3. Power on the PHY. This calls the PHY driver's .power_on op,
+	 * which configures the Post-PLL and analog blocks.
+	 */
+	ret = phy_power_on(ctrl->phy);
+	if (ret) {
+		dev_err(dev, "Failed to power on PHY: %d\n", ret);
+		clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk);
+		return;
+	}
+}
+
+static void inno_hdmi_starfive_disable(struct device *dev)
+{
+	struct stf_inno_hdmi_controller *ctrl = dev_get_drvdata(dev);
+
+	phy_power_off(ctrl->phy);
+	clk_disable_unprepare(ctrl->clks[CLK_PCLK].clk);
+}
+
+static int starfive_inno_hdmi_controller_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device *parent = dev->parent;
+	struct stf_inno_hdmi_controller *ctrl;
+	const struct inno_hdmi_plat_data *plat_data;
+	struct regmap *mfd_regmap;
+	int ret;
+
+	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
+	if (!ctrl)
+		return -ENOMEM;
+
+	ctrl->dev = dev;
+	platform_set_drvdata(pdev, ctrl);
+
+	/* Get the shared regmap from the MFD parent */
+	mfd_regmap = dev_get_regmap(parent, NULL);
+	if (!mfd_regmap) {
+		dev_err(dev, "Failed to get parent regmap\n");
+		return -ENODEV;
+	}
+
+	ctrl->phy = devm_phy_get(dev, "hdmi-phy");
+	if (IS_ERR(ctrl->phy))
+		return dev_err_probe(dev, PTR_ERR(ctrl->phy), "Failed to get PHY\n");
+
+	ctrl->tx_rst = devm_reset_control_get_exclusive(dev, "hdmi_tx");
+	if (IS_ERR(ctrl->tx_rst))
+		return dev_err_probe(dev, PTR_ERR(ctrl->tx_rst), "failed to get tx reset\n");
+
+	/* Populate the clock names this controller *consumes* */
+	ctrl->clks[CLK_SYS].id = "sys";
+	ctrl->clks[CLK_M].id = "mclk";
+	ctrl->clks[CLK_B].id = "bclk";
+	ctrl->clks[CLK_PCLK].id = "pclk"; /* Pixel clock *from* PHY */
+
+	ret = devm_clk_bulk_get(dev, CLK_CTRL_NUM, ctrl->clks);
+	if (ret)
+		return dev_err_probe(dev, ret, "Unable to get controller clocks\n");
+
+	/* pclk is enabled on demand during modeset */
+	ret = clk_bulk_prepare_enable(CLK_CTRL_NUM - 1, ctrl->clks);
+	if (ret)
+		return ret;
+
+	ret = reset_control_deassert(ctrl->tx_rst);
+	if (ret) {
+		clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks);
+		return ret;
+	}
+
+	plat_data = of_device_get_match_data(dev);
+
+	/* Hand off to the generic library to create the bridge. */
+	ctrl->inno = inno_hdmi_probe(pdev, plat_data);
+	if (IS_ERR(ctrl->inno)) {
+		reset_control_assert(ctrl->tx_rst);
+		clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks);
+		return PTR_ERR(ctrl->inno);
+	}
+
+	return 0;
+}
+
+static void starfive_inno_hdmi_controller_remove(struct platform_device *pdev)
+{
+	struct stf_inno_hdmi_controller *ctrl = platform_get_drvdata(pdev);
+
+	inno_hdmi_remove(ctrl->inno);
+
+	reset_control_assert(ctrl->tx_rst);
+	clk_bulk_disable_unprepare(CLK_CTRL_NUM - 1, ctrl->clks);
+}
+
+/*
+ * This table is now only used for the generic .mode_valid check.
+ * The real validation happens in the PHY driver's .round_rate.
+ */
+static struct inno_hdmi_phy_config stf_hdmi_phy_configs[] = {
+	{ 297000000, 0x00, 0x00 },
+	{ ~0UL, 0x00, 0x00 }, /* Sentinel */
+};
+
+static const struct inno_hdmi_plat_ops stf_inno_hdmi_plat_ops = {
+	.enable = inno_hdmi_starfive_enable,
+	.disable = inno_hdmi_starfive_disable,
+};
+
+static const struct inno_hdmi_plat_data stf_inno_hdmi_plat_data = {
+	.ops = &stf_inno_hdmi_plat_ops,
+	.phy_configs = stf_hdmi_phy_configs,
+	.default_phy_config = &stf_hdmi_phy_configs[0],
+};
+
+static const struct of_device_id starfive_hdmi_controller_dt_ids[] = {
+	{ .compatible = "starfive,jh7110-inno-hdmi-controller",
+	  .data = &stf_inno_hdmi_plat_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, starfive_hdmi_controller_dt_ids);
+
+struct platform_driver starfive_inno_hdmi_controller_driver = {
+	.probe = starfive_inno_hdmi_controller_probe,
+	.remove = starfive_inno_hdmi_controller_remove,
+	.driver = {
+		.name = "starfive-inno-hdmi-controller",
+		.of_match_table = starfive_hdmi_controller_dt_ids,
+	},
+};
+module_platform_driver(starfive_inno_hdmi_controller_driver);
+
+MODULE_AUTHOR("Michal Wilczynski <m.wilczynski@samsung.com>");
+MODULE_DESCRIPTION("StarFive INNO HDMI Controller Driver");
+MODULE_LICENSE("GPL");

-- 
2.34.1

[PATCH RFC 12/13] phy: starfive: Add jh7110-inno-hdmi-phy driver

[Michal Wilczynski]

[WARNING: This is mostly a duplicate of Rockchip RK3328 PHY driver, I
would like properly refactor common parts, maybe to some inno-phy
library, not 100% sure how this would look like so would happy to take
advice]

Add the HDMI PHY driver for the StarFive JH7110.

This driver binds to the starfive,jh7110-inno-hdmi-phy MFD child and
gets its regmap from the parent. It has no dependencies on voutcrg, only
on its refoclk (xin24m), which breaks the probe-time circular
dependency.

This driver provides two main functions:
 - Clock Provider: It registers clk_ops to provide the variable pixel
   clock (hdmi_pclk). The .set_rate operation configures the Pre-PLL
   registers (0x1a0+) based on the requested rate.

 - PHY Provider: It registers phy_ops for the controller. The .power_on
   op configures and enables the Post-PLL and other analog blocks (BIAS,
   LDO, Serializer, etc.).

The register level logic is based on the Rockchip RK3328 PHY driver, as
they share the same Innosilicon IP, but is adapted for the JH7110's
0x100 register offset.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 MAINTAINERS                                 |   1 +
 drivers/phy/starfive/Kconfig                |  19 +
 drivers/phy/starfive/Makefile               |   1 +
 drivers/phy/starfive/phy-jh7110-inno-hdmi.c | 762 ++++++++++++++++++++++++++++
 4 files changed, 783 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5984b83e55aeadb59c25a6e8f01057fb9d982d81..765b155574b2a0649f2df6b89a17eaf111d912bf 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -24054,6 +24054,7 @@ F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-vout-subsystem
 F:	drivers/soc/starfive/jh7110-hdmi-mfd.c
 F:	drivers/soc/starfive/jh7110-vout-subsystem.c
 F:	drivers/gpu/drm/bridge/jh7110-inno-hdmi.c
+F:	drivers/phy/starfive/phy-jh7110-inno-hdmi.c
 
 STARFIVE JH7110 DPHY RX DRIVER
 M:	Jack Zhu <jack.zhu@starfivetech.com>
diff --git a/drivers/phy/starfive/Kconfig b/drivers/phy/starfive/Kconfig
index d0cdd7cb4a13de22ff643c89a79d99cce57284d7..9f0c330c1dd52f38a51ff9e211340ecdf091fce1 100644
--- a/drivers/phy/starfive/Kconfig
+++ b/drivers/phy/starfive/Kconfig
@@ -25,6 +25,25 @@ config PHY_STARFIVE_JH7110_DPHY_TX
 	  system. If M is selected, the module will be called
 	  phy-jh7110-dphy-tx.ko.
 
+config PHY_STARFIVE_JH7110_INNO_HDMI
+	tristate "Starfive JH7110 INNO HDMI PHY"
+	depends on COMMON_CLK
+	select GENERIC_PHY
+	help
+	  This option enables the driver for the analog HDMI PHY (Physical
+	  Layer) on the StarFive JH7110 SoC.
+
+	  This driver binds to a child node of the 'starfive,jh7110-hdmi-mfd'
+	  parent driver and gets its register map from that parent.
+
+	  It is responsible for two main functions:
+	  1. PHY Provider: It provides standard PHY operations (.power_on,
+	     .power_off) for the HDMI controller (bridge) driver. This
+	     involves configuring the Post-PLL and analog TMDS blocks.
+	  2. Clock Provider: It registers as a clock provider to supply the
+	     variable pixel clock (hdmi_pclk) to the HDMI controller and
+	     the VOUT subsystem, which it generates using the Pre-PLL.
+
 config PHY_STARFIVE_JH7110_PCIE
 	tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
 	depends on HAS_IOMEM
diff --git a/drivers/phy/starfive/Makefile b/drivers/phy/starfive/Makefile
index eedc4a6fec156320c99ac0a0da609083b6a6a695..e7b13f00880b500f933f21b6037384d5c6884e3e 100644
--- a/drivers/phy/starfive/Makefile
+++ b/drivers/phy/starfive/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX)	+= phy-jh7110-dphy-rx.o
 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX)	+= phy-jh7110-dphy-tx.o
+obj-$(CONFIG_PHY_STARFIVE_JH7110_INNO_HDMI)	+= phy-jh7110-inno-hdmi.o
 obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE)		+= phy-jh7110-pcie.o
 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB)		+= phy-jh7110-usb.o
diff --git a/drivers/phy/starfive/phy-jh7110-inno-hdmi.c b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c
new file mode 100644
index 0000000000000000000000000000000000000000..a74893cbcfad245ec325b1e399bd8ded829376fa
--- /dev/null
+++ b/drivers/phy/starfive/phy-jh7110-inno-hdmi.c
@@ -0,0 +1,762 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2025 Samsung Electronics Co., Ltd.
+ * Author: Michal Wilczynski <m.wilczynski@samsung.com>
+ *
+ * This driver handles the PHY portion of the StarFive Innosilicon HDMI IP,
+ * which is part of a monolithic MFD block. It provides the variable pixel
+ * clock (from the Pre-PLL) and the PHY operations (for the Post-PLL/analog).
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/math64.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/phy/phy.h>
+#include <linux/slab.h>
+
+#define UPDATE(x, h, l)		(((x) << (l)) & GENMASK((h), (l)))
+
+/*
+ * StarFive (JH7110) Innosilicon HDMI PHY Register Definitions
+ */
+
+/* REG: 0x1a0 */
+#define STF_INNO_PRE_PLL_CONTROL		0x1a0
+#define STF_INNO_PRE_PLL_POWER_DOWN		BIT(0)
+#define STF_INNO_PCLK_VCO_DIV_5_MASK		BIT(1)
+#define STF_INNO_PCLK_VCO_DIV_5(x)		UPDATE(x, 1, 1)
+
+/* REG: 0x1a1 */
+#define STF_INNO_PRE_PLL_DIV_1		0x1a1
+#define STF_INNO_PRE_PLL_PRE_DIV_MASK		GENMASK(5, 0)
+#define STF_INNO_PRE_PLL_PRE_DIV(x)		UPDATE(x, 5, 0)
+
+/* REG: 0x1a2 */
+#define STF_INNO_PRE_PLL_DIV_2		0x1a2
+#define STF_INNO_SPREAD_SPECTRUM_MOD_DOWN	BIT(7)
+#define STF_INNO_SPREAD_SPECTRUM_MOD_DISABLE	BIT(6)
+#define STF_INNO_PRE_PLL_FRAC_DIV_DISABLE	FIELD_PREP(GENMASK(5, 4), 3)
+#define STF_INNO_PRE_PLL_FB_DIV_11_8_MASK	GENMASK(3, 0)
+#define STF_INNO_PRE_PLL_FB_DIV_11_8(x)	FIELD_PREP(STF_INNO_PRE_PLL_FB_DIV_11_8_MASK, (x) >> 8)
+
+/* REG: 0x1a3 */
+#define STF_INNO_PRE_PLL_DIV_3		0x1a3
+#define STF_INNO_PRE_PLL_FB_DIV_7_0(x)		FIELD_PREP(GENMASK(7, 0), x)
+
+/* REG: 0x1a4 -- TMDSCLK Divs, needed by set_rate */
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV		0x1a4
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV_C_MASK	GENMASK(1, 0)
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV_C(x)	UPDATE(x, 1, 0)
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV_B_MASK	GENMASK(3, 2)
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV_B(x)	UPDATE(x, 3, 2)
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV_A_MASK	GENMASK(5, 4)
+#define STF_INNO_PRE_PLL_TMDSCLK_DIV_A(x)	UPDATE(x, 5, 4)
+
+/* REG: 0x1a5 */
+#define STF_INNO_PCLK_DIV_AB_REG		0x1a5
+#define STF_INNO_PCLK_DIV_B_SHIFT		5
+#define STF_INNO_PCLK_DIV_B_MASK		GENMASK(6, 5)
+#define STF_INNO_PCLK_DIV_B(x)		UPDATE(x, 6, 5)
+#define STF_INNO_PCLK_DIV_A_MASK		GENMASK(4, 0)
+#define STF_INNO_PCLK_DIV_A(x)		UPDATE(x, 4, 0)
+
+/* REG: 0x1a6 */
+#define STF_INNO_PCLK_DIV_CD_REG		0x1a6
+#define STF_INNO_PCLK_DIV_C_SHIFT		5
+#define STF_INNO_PCLK_DIV_C_MASK		GENMASK(6, 5)
+#define STF_INNO_PCLK_DIV_C(x)		UPDATE(x, 6, 5)
+#define STF_INNO_PCLK_DIV_D_MASK		GENMASK(4, 0)
+#define STF_INNO_PCLK_DIV_D(x)		UPDATE(x, 4, 0)
+
+/* REG: 0x1a9 */
+#define STF_INNO_PRE_PLL_LOCK_STATUS		0x1a9
+#define STF_INNO_PRE_PLL_LOCK		BIT(0)
+
+/* REG: 0x1aa */
+#define STF_INNO_POST_PLL_DIV_1		0x1aa
+#define STF_INNO_POST_PLL_POST_DIV_ENABLE	GENMASK(3, 2)
+#define STF_INNO_POST_PLL_REFCLK_SEL_TMDS	BIT(1)
+#define STF_INNO_POST_PLL_POWER_DOWN		BIT(0)
+
+/* REG: 0x1ab */
+#define STF_INNO_POST_PLL_DIV_2		0x1ab
+#define STF_INNO_POST_PLL_PRE_DIV(x)		FIELD_PREP(GENMASK(5, 0), x)
+#define STF_INNO_POST_PLL_FB_DIV_8(x)		UPDATE((x) >> 8, 7, 7)
+
+/* REG: 0x1ac */
+#define STF_INNO_POST_PLL_DIV_3		0x1ac
+#define STF_INNO_POST_PLL_FB_DIV_7_0(x)	UPDATE(x, 7, 0)
+
+/* REG: 0x1ad */
+#define STF_INNO_POST_PLL_DIV_4		0x1ad
+#define STF_INNO_POST_PLL_POST_DIV_MASK	GENMASK(1, 0)
+
+/* REG: 0x1af */
+#define STF_INNO_POST_PLL_LOCK_STATUS		0x1af
+#define STF_INNO_POST_PLL_LOCK		BIT(0)
+
+/* REG: 0x1b0 */
+#define STF_INNO_BIAS_CONTROL			0x1b0
+#define STF_INNO_BIAS_ENABLE			BIT(2)
+
+/* REG: 0x1b2 */
+#define STF_INNO_TMDS_CONTROL			0x1b2
+#define STF_INNO_TMDS_CLK_DRIVER_EN		BIT(3)
+#define STF_INNO_TMDS_D2_DRIVER_EN		BIT(2)
+#define STF_INNO_TMDS_D1_DRIVER_EN		BIT(1)
+#define STF_INNO_TMDS_D0_DRIVER_EN		BIT(0)
+#define STF_INNO_TMDS_DRIVER_ENABLE		(STF_INNO_TMDS_CLK_DRIVER_EN | \
+						 STF_INNO_TMDS_D2_DRIVER_EN | \
+						 STF_INNO_TMDS_D1_DRIVER_EN | \
+						 STF_INNO_TMDS_D0_DRIVER_EN)
+
+/* REG: 0x1b4 */
+#define STF_INNO_LDO_CONTROL			0x1b4
+#define STF_INNO_LDO_ENABLE			(BIT(2) | BIT(1) | BIT(0))
+
+/* REG: 0x1be */
+#define STF_INNO_SERIALIER_CONTROL		0x1be
+#define STF_INNO_SERIALIER_ENABLE		(BIT(6) | BIT(5) | BIT(4) | BIT(0))
+
+/* REG: 0x1cc */
+#define STF_INNO_RX_CONTROL			0x1cc
+#define STF_INNO_RX_ENABLE			(BIT(3) | BIT(2) | BIT(1) | BIT(0))
+
+/* REG: 0x1d1 */
+#define STF_INNO_PRE_PLL_FRAC_DIV_H		0x1d1
+#define STF_INNO_PRE_PLL_FRAC_DIV_23_16(x)	UPDATE((x) >> 16, 7, 0)
+/* REG: 0x1d2 */
+#define STF_INNO_PRE_PLL_FRAC_DIV_M		0x1d2
+#define STF_INNO_PRE_PLL_FRAC_DIV_15_8(x)	UPDATE((x) >> 8, 7, 0)
+/* REG: 0x1d3 */
+#define STF_INNO_PRE_PLL_FRAC_DIV_L		0x1d3
+#define STF_INNO_PRE_PLL_FRAC_DIV_7_0(x)	UPDATE(x, 7, 0)
+
+/*
+ * These tables are copied from the monolithic driver.
+ * They match the Rockchip PHY driver tables.
+ */
+struct pre_pll_config {
+	unsigned long pixclock;
+	unsigned long tmdsclock;
+	u8 prediv;
+	u16 fbdiv;
+	u8 tmds_div_a;
+	u8 tmds_div_b;
+	u8 tmds_div_c;
+	u8 pclk_div_a;
+	u8 pclk_div_b;
+	u8 pclk_div_c;
+	u8 pclk_div_d;
+	u8 vco_div_5_en;
+	u32 fracdiv;
+};
+
+struct post_pll_config {
+	unsigned long tmdsclock;
+	u8 prediv;
+	u16 fbdiv;
+	u8 postdiv;
+	u8 post_div_en;
+	u8 version;
+};
+
+static const struct pre_pll_config pre_pll_cfg_table[] = {
+	{ 25175000, 25175000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0xF55555 },
+	{ 25200000, 25200000, 1, 100, 2, 3, 3, 12, 3, 3, 4, 0, 0 },
+	{ 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0 },
+	{ 27027000, 27027000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0x170A3D },
+	{ 28320000, 28320000, 1, 28, 2, 1, 1, 3, 0, 3, 4, 0, 0x51EB85 },
+	{ 30240000, 30240000, 1, 30, 2, 1, 1, 3, 0, 3, 4, 0, 0x3D70A3 },
+	{ 31500000, 31500000, 1, 31, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 33750000, 33750000, 1, 33, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF },
+	{ 36000000, 36000000, 1, 36, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 40000000, 40000000, 1, 80, 2, 2, 2, 12, 2, 2, 2, 0, 0 },
+	{ 46970000, 46970000, 1, 46, 2, 1, 1, 3, 0, 3, 4, 0, 0xF851EB },
+	{ 49500000, 49500000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 49000000, 49000000, 1, 49, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 50000000, 50000000, 1, 50, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 54000000, 54000000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 54054000, 54054000, 1, 54, 2, 1, 1, 3, 0, 3, 4, 0, 0x0DD2F1 },
+	{ 57284000, 57284000, 1, 57, 2, 1, 1, 3, 0, 3, 4, 0, 0x48B439 },
+	{ 58230000, 58230000, 1, 58, 2, 1, 1, 3, 0, 3, 4, 0, 0x3AE147 },
+	{ 59341000, 59341000, 1, 59, 2, 1, 1, 3, 0, 3, 4, 0, 0x574BC6 },
+	{ 59400000, 59400000, 1, 99, 3, 1, 1, 1, 3, 3, 4, 0, 0 },
+	{ 65000000, 65000000, 1, 130, 2, 2, 2, 12, 0, 2, 2, 0, 0 },
+	{ 68250000, 68250000, 1, 68, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF },
+	{ 71000000, 71000000, 1, 71, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 74176000, 74176000, 1, 98, 1, 2, 2, 1, 2, 3, 4, 0, 0xE6AE6B },
+	{ 74250000, 74250000, 1, 99, 1, 2, 2, 1, 2, 3, 4, 0, 0 },
+	{ 75000000, 75000000, 1, 75, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 78750000, 78750000, 1, 78, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF },
+	{ 79500000, 79500000, 1, 79, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 83500000, 83500000, 2, 167, 2, 1, 1, 1, 0, 0, 6, 0, 0 },
+	{ 83500000, 104375000, 1, 104, 2, 1, 1, 1, 1, 0, 5, 0, 0x600000 },
+	{ 85500000, 85500000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 85750000, 85750000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF },
+	{ 85800000, 85800000, 1, 85, 2, 1, 1, 3, 0, 3, 4, 0, 0xCCCCCC },
+	{ 88750000, 88750000, 1, 88, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF },
+	{ 89910000, 89910000, 1, 89, 2, 1, 1, 3, 0, 3, 4, 0, 0xE8F5C1 },
+	{ 90000000, 90000000, 1, 90, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 101000000, 101000000, 1, 101, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 102250000, 102250000, 1, 102, 2, 1, 1, 3, 0, 3, 4, 0, 0x3FFFFF },
+	{ 106500000, 106500000, 1, 106, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 108000000, 108000000, 1, 90, 3, 0, 0, 5, 0, 2, 2, 0, 0 },
+	{ 119000000, 119000000, 1, 119, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 131481000, 131481000, 1, 131, 2, 1, 1, 3, 0, 3, 4, 0, 0x7B22D1 },
+	{ 135000000, 135000000, 1, 135, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 136750000, 136750000, 1, 136, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF },
+	{ 147180000, 147180000, 1, 147, 2, 1, 1, 3, 0, 3, 4, 0, 0x2E147A },
+	{ 148352000, 148352000, 1, 98, 1, 1, 1, 1, 2, 2, 2, 0, 0xE6AE6B },
+	{ 148500000, 148500000, 1, 99, 1, 1, 1, 1, 2, 2, 2, 0, 0 },
+	{ 154000000, 154000000, 1, 154, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 156000000, 156000000, 1, 156, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 157000000, 157000000, 1, 157, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 162000000, 162000000, 1, 162, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 174250000, 174250000, 1, 145, 3, 0, 0, 5, 0, 2, 2, 0, 0x355555 },
+	{ 174500000, 174500000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 174570000, 174570000, 1, 174, 2, 1, 1, 3, 0, 3, 4, 0, 0x91EB84 },
+	{ 175500000, 175500000, 1, 175, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 185590000, 185590000, 1, 185, 2, 1, 1, 3, 0, 3, 4, 0, 0x970A3C },
+	{ 187000000, 187000000, 1, 187, 2, 1, 1, 3, 0, 3, 4, 0, 0 },
+	{ 241500000, 241500000, 1, 161, 1, 1, 1, 4, 0, 2, 2, 0, 0 },
+	{ 241700000, 241700000, 1, 241, 2, 1, 1, 3, 0, 3, 4, 0, 0xB33332 },
+	{ 262750000, 262750000, 1, 262, 2, 1, 1, 3, 0, 3, 4, 0, 0xCFFFFF },
+	{ 296500000, 296500000, 1, 296, 2, 1, 1, 3, 0, 3, 4, 0, 0x7FFFFF },
+	{ 296703000, 296703000, 1, 98, 0, 1, 1, 1, 0, 2, 2, 0, 0xE6AE6B },
+	{ 297000000, 297000000, 1, 99, 0, 1, 1, 1, 0, 2, 2, 0, 0 },
+	{ 594000000, 594000000, 1, 99, 0, 2, 0, 1, 0, 1, 1, 0, 0 },
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+};
+
+static const struct post_pll_config post_pll_cfg_table[] = {
+	{ 25200000, 1, 80, 13, 3, 1 },
+	{ 27000000, 1, 40, 11, 3, 1 },
+	{ 27027000, 1, 40, 11, 3, 1 },
+	{ 33750000, 1, 40, 11, 3, 1 },
+	{ 49000000, 1, 20, 1, 3, 3 },
+	{ 65000000, 1, 20, 1, 3, 3 },
+	{ 74250000, 1, 20, 1, 3, 3 },
+	{ 88750000, 1, 20, 1, 3, 3 },
+	{ 108000000, 1, 20, 1, 3, 3 },
+	{ 148500000, 1, 20, 1, 3, 3 },
+	{ 162000000, 1, 20, 1, 3, 3 },
+	{ 174250000, 1, 20, 1, 3, 3 },
+	{ 187000000, 1, 20, 1, 3, 3 },
+	{ 241700000, 1, 20, 1, 3, 3 },
+	{ 297000000, 4, 20, 0, 0, 3 },
+	{ 594000000, 4, 20, 0, 0, 0 }, /* postpll_postdiv_en = 0 */
+	{ /* sentinel */ }
+};
+
+struct starfive_hdmi_phy {
+	struct device *dev;
+	struct regmap *regmap;
+	struct phy *phy;
+	struct clk *refoclk;
+
+	struct clk_hw hw;
+	struct clk *phyclk;
+	unsigned long pixclock;
+	unsigned long tmdsclock;
+
+	const struct pre_pll_config *pre_cfg;
+	const struct post_pll_config *post_cfg;
+};
+
+static inline void inno_write(struct starfive_hdmi_phy *inno, u32 reg, u8 val)
+{
+	regmap_write(inno->regmap, reg * 4, val);
+}
+
+static inline u8 inno_read(struct starfive_hdmi_phy *inno, u32 reg)
+{
+	u32 val;
+
+	regmap_read(inno->regmap, reg * 4, &val);
+	return val;
+}
+
+static inline void inno_update_bits(struct starfive_hdmi_phy *inno, u16 reg,
+				    u8 mask, u8 val)
+{
+	regmap_update_bits(inno->regmap, reg * 4, mask, val);
+}
+
+#define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
+	regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
+				 sleep_us, timeout_us)
+
+static const
+struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct starfive_hdmi_phy *inno,
+						     unsigned long rate)
+{
+	const struct pre_pll_config *cfg = pre_pll_cfg_table;
+
+	/* Round rate to nearest 1000Hz for matching */
+	rate = DIV_ROUND_CLOSEST(rate, 1000) * 1000;
+
+	for (; cfg->pixclock != 0; cfg++)
+		if (cfg->pixclock == rate)
+			break;
+
+	if (cfg->pixclock == 0)
+		return ERR_PTR(-EINVAL);
+
+	return cfg;
+}
+
+static inline struct starfive_hdmi_phy *to_starfive_hdmi_phy(struct clk_hw *hw)
+{
+	return container_of(hw, struct starfive_hdmi_phy, hw);
+}
+
+static int starfive_hdmi_phy_clk_prepare(struct clk_hw *hw)
+{
+	struct starfive_hdmi_phy *inno = to_starfive_hdmi_phy(hw);
+	u32 val;
+	int ret;
+
+	/* Ensure Pre-PLL is powered up */
+	inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL,
+			 STF_INNO_PRE_PLL_POWER_DOWN, 0);
+
+	/* Wait for Pre-PLL lock if not already locked */
+	val = inno_read(inno, STF_INNO_PRE_PLL_LOCK_STATUS);
+	if (val & STF_INNO_PRE_PLL_LOCK_STATUS)
+		return 0; /* Already locked */
+
+	ret = inno_poll(inno, STF_INNO_PRE_PLL_LOCK_STATUS, val,
+			val & STF_INNO_PRE_PLL_LOCK_STATUS, 1000, 100000);
+	if (ret < 0) {
+		dev_err(inno->dev, "Timeout waiting for pre-PLL lock\n");
+		inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL,
+				 STF_INNO_PRE_PLL_POWER_DOWN,
+				 STF_INNO_PRE_PLL_POWER_DOWN);
+		return ret;
+	}
+	return 0;
+}
+
+static void starfive_hdmi_phy_clk_unprepare(struct clk_hw *hw)
+{
+	struct starfive_hdmi_phy *inno = to_starfive_hdmi_phy(hw);
+
+	/* Power down Pre-PLL */
+	inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL,
+			 STF_INNO_PRE_PLL_POWER_DOWN,
+			 STF_INNO_PRE_PLL_POWER_DOWN);
+	inno->pixclock = 0; /* Invalidate cached rate */
+}
+
+static int starfive_hdmi_phy_clk_is_prepared(struct clk_hw *hw)
+{
+	struct starfive_hdmi_phy *inno = to_starfive_hdmi_phy(hw);
+	u8 status;
+
+	status = inno_read(inno, STF_INNO_PRE_PLL_CONTROL);
+	if (status & STF_INNO_PRE_PLL_POWER_DOWN)
+		return 0;
+
+	return !!(inno_read(inno, STF_INNO_PRE_PLL_LOCK_STATUS) &
+		  STF_INNO_PRE_PLL_LOCK_STATUS);
+}
+
+static unsigned long starfive_hdmi_phy_clk_recalc_rate(struct clk_hw *hw,
+						       unsigned long parent_rate)
+{
+	struct starfive_hdmi_phy *inno = to_starfive_hdmi_phy(hw);
+	unsigned long frac;
+	u8 nd, no_a, no_b, no_d;
+	u64 vco;
+	u16 nf;
+
+	if (!starfive_hdmi_phy_clk_is_prepared(hw))
+		return inno->pixclock;
+
+	nd = inno_read(inno, STF_INNO_PRE_PLL_DIV_1) & STF_INNO_PRE_PLL_PRE_DIV_MASK;
+	nf = ((inno_read(inno, STF_INNO_PRE_PLL_DIV_2) & STF_INNO_PRE_PLL_FB_DIV_11_8_MASK) << 8);
+	nf |= inno_read(inno, STF_INNO_PRE_PLL_DIV_3);
+	vco = parent_rate * nf;
+
+	if (!(inno_read(inno, STF_INNO_PRE_PLL_DIV_2) & STF_INNO_PRE_PLL_FRAC_DIV_DISABLE)) {
+		frac = inno_read(inno, STF_INNO_PRE_PLL_FRAC_DIV_L) |
+		       (inno_read(inno, STF_INNO_PRE_PLL_FRAC_DIV_M) << 8) |
+		       (inno_read(inno, STF_INNO_PRE_PLL_FRAC_DIV_H) << 16);
+		vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
+	}
+
+	if (inno_read(inno, STF_INNO_PRE_PLL_CONTROL) & STF_INNO_PCLK_VCO_DIV_5_MASK) {
+		do_div(vco, nd * 5);
+	} else {
+		no_a = inno_read(inno, STF_INNO_PCLK_DIV_AB_REG) & STF_INNO_PCLK_DIV_A_MASK;
+		no_b = inno_read(inno, STF_INNO_PCLK_DIV_AB_REG) & STF_INNO_PCLK_DIV_B_MASK;
+		no_b >>= STF_INNO_PCLK_DIV_B_SHIFT;
+		no_b += 2;
+		no_d = inno_read(inno, STF_INNO_PCLK_DIV_CD_REG) & STF_INNO_PCLK_DIV_D_MASK;
+
+		do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
+	}
+
+	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
+
+	dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
+		__func__, inno->pixclock, vco);
+
+	return inno->pixclock;
+}
+
+static long starfive_hdmi_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+					     unsigned long *parent_rate)
+{
+	const struct pre_pll_config *cfg = pre_pll_cfg_table;
+
+	rate = (rate / 1000) * 1000;
+
+	for (; cfg->pixclock != 0; cfg++)
+		if (cfg->pixclock == rate)
+			break;
+
+	if (cfg->pixclock == 0)
+		return -EINVAL;
+
+	return cfg->pixclock;
+}
+
+static int starfive_hdmi_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+					  unsigned long parent_rate)
+{
+	struct starfive_hdmi_phy *inno = to_starfive_hdmi_phy(hw);
+	const struct pre_pll_config *cfg;
+	unsigned long tmdsclock;
+	u32 val;
+
+	/*
+	 * Find the config entry for the requested pixclock (rate).
+	 * This cfg entry also contains the required tmdsclock.
+	 */
+	cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
+	if (IS_ERR(cfg))
+		return PTR_ERR(cfg);
+
+	tmdsclock = cfg->tmdsclock;
+
+	dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
+		__func__, rate, tmdsclock);
+
+	if (inno->pixclock == rate && inno->tmdsclock == tmdsclock)
+		return 0;
+
+	inno->pre_cfg = cfg;
+
+	inno_update_bits(inno, STF_INNO_BIAS_CONTROL,
+			 STF_INNO_BIAS_ENABLE, STF_INNO_BIAS_ENABLE);
+	inno_write(inno, STF_INNO_RX_CONTROL, STF_INNO_RX_ENABLE);
+
+	/* Power down Pre-PLL before re-configuring */
+	inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL,
+			 STF_INNO_PRE_PLL_POWER_DOWN,
+			 STF_INNO_PRE_PLL_POWER_DOWN);
+
+	/* Configure pre-pll */
+	inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL,
+			 STF_INNO_PCLK_VCO_DIV_5_MASK,
+			 STF_INNO_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
+	inno_write(inno, STF_INNO_PRE_PLL_DIV_1,
+		   STF_INNO_PRE_PLL_PRE_DIV(cfg->prediv));
+
+	val = STF_INNO_SPREAD_SPECTRUM_MOD_DISABLE;
+	if (!cfg->fracdiv)
+		val |= STF_INNO_PRE_PLL_FRAC_DIV_DISABLE;
+
+	inno_write(inno, STF_INNO_PRE_PLL_DIV_2,
+		   STF_INNO_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
+	inno_write(inno, STF_INNO_PRE_PLL_DIV_3,
+		   STF_INNO_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
+
+	/* Write PCLK dividers */
+	inno_write(inno, STF_INNO_PCLK_DIV_AB_REG,
+		   STF_INNO_PCLK_DIV_A(cfg->pclk_div_a) |
+		   STF_INNO_PCLK_DIV_B(cfg->pclk_div_b));
+	inno_write(inno, STF_INNO_PCLK_DIV_CD_REG,
+		   STF_INNO_PCLK_DIV_C(cfg->pclk_div_c) |
+		   STF_INNO_PCLK_DIV_D(cfg->pclk_div_d));
+
+	/* Write TMDSCLK dividers */
+	inno_write(inno, STF_INNO_PRE_PLL_TMDSCLK_DIV,
+		   STF_INNO_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
+		   STF_INNO_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
+		   STF_INNO_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
+
+	/* Write fractional divider registers */
+	inno_write(inno, STF_INNO_PRE_PLL_FRAC_DIV_L,
+		   STF_INNO_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
+	inno_write(inno, STF_INNO_PRE_PLL_FRAC_DIV_M,
+		   STF_INNO_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
+	inno_write(inno, STF_INNO_PRE_PLL_FRAC_DIV_H,
+		   STF_INNO_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
+
+	/* Power up Pre-PLL */
+	inno_update_bits(inno, STF_INNO_PRE_PLL_CONTROL,
+			 STF_INNO_PRE_PLL_POWER_DOWN, 0);
+
+	inno->pixclock = rate;
+	inno->tmdsclock = tmdsclock;
+
+	return 0;
+}
+
+static const struct clk_ops starfive_hdmi_phy_clk_ops = {
+	.prepare = starfive_hdmi_phy_clk_prepare,
+	.unprepare = starfive_hdmi_phy_clk_unprepare,
+	.is_prepared = starfive_hdmi_phy_clk_is_prepared,
+	.recalc_rate = starfive_hdmi_phy_clk_recalc_rate,
+	.round_rate = starfive_hdmi_phy_clk_round_rate,
+	.set_rate = starfive_hdmi_phy_clk_set_rate,
+};
+
+static int starfive_hdmi_phy_power_on(struct phy *phy)
+{
+	struct starfive_hdmi_phy *inno = phy_get_drvdata(phy);
+	const struct post_pll_config *cfg = post_pll_cfg_table;
+	unsigned long tmdsclock = inno->tmdsclock;
+	u8 reg_1ad_value;
+	u8 reg_1aa_value;
+
+	u32 v;
+	int ret;
+
+	if (!tmdsclock) {
+		dev_err(inno->dev, "TMDS clock is zero (pixclock not set?)\n");
+		return -EINVAL;
+	}
+
+	/* Find Post-PLL config */
+	for (; cfg->tmdsclock != 0; cfg++)
+		if (tmdsclock <= cfg->tmdsclock)
+			break;
+
+	if (cfg->tmdsclock == 0) {
+		dev_err(inno->dev, "Failed to find Post-PLL config\n");
+		return -EINVAL;
+	}
+	inno->post_cfg = cfg;
+
+	dev_dbg(inno->dev, "Inno HDMI PHY Power On: pixclk %lu, tmdsclk %lu\n",
+		inno->pixclock, tmdsclock);
+
+	reg_1ad_value = cfg->post_div_en ? cfg->postdiv : 0x00;
+	reg_1aa_value = cfg->post_div_en ? 0x0e : 0x02;
+
+	/*
+	 * Pre-PLL is already prepared and running at inno->pixclock
+	 * via the clk_set_rate and prepare calls from the controller/bridge.
+	 * Now, configure and enable the Post-PLL and TMDS outputs.
+	 */
+
+	inno_write(inno, STF_INNO_POST_PLL_DIV_2,
+		   STF_INNO_POST_PLL_PRE_DIV(cfg->prediv));
+	inno_write(inno, STF_INNO_POST_PLL_DIV_3, cfg->fbdiv & 0xff);
+	inno_write(inno, STF_INNO_POST_PLL_DIV_4, reg_1ad_value);
+
+	/* Power up Post-PLL */
+	inno_write(inno, STF_INNO_POST_PLL_DIV_1, reg_1aa_value);
+
+	/* Wait for post PLL lock */
+	ret = inno_poll(inno, STF_INNO_POST_PLL_LOCK_STATUS, v,
+			v & STF_INNO_POST_PLL_LOCK_STATUS, 1000, 100000);
+	if (ret) {
+		dev_err(inno->dev, "Post-PLL locking failed\n");
+		return ret;
+	}
+
+	inno_write(inno, STF_INNO_LDO_CONTROL, STF_INNO_LDO_ENABLE);
+	inno_write(inno, STF_INNO_SERIALIER_CONTROL,
+		   STF_INNO_SERIALIER_ENABLE);
+	inno_write(inno, STF_INNO_TMDS_CONTROL, 0x8f);
+
+	return 0;
+}
+
+static int starfive_hdmi_phy_power_off(struct phy *phy)
+{
+	struct starfive_hdmi_phy *inno = phy_get_drvdata(phy);
+
+	dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
+
+	inno_write(inno, STF_INNO_TMDS_CONTROL, 0x00);
+	inno_write(inno, STF_INNO_SERIALIER_CONTROL, 0x00);
+	inno_write(inno, STF_INNO_LDO_CONTROL, 0x00);
+	inno_update_bits(inno, STF_INNO_BIAS_CONTROL,
+			 STF_INNO_BIAS_ENABLE, 0x00);
+	inno_write(inno, STF_INNO_RX_CONTROL, 0x00);
+
+	/* Power down Post-PLL */
+	inno_update_bits(inno, STF_INNO_POST_PLL_DIV_1,
+			 STF_INNO_POST_PLL_POWER_DOWN,
+			 STF_INNO_POST_PLL_POWER_DOWN);
+
+	/*
+	 * Pre-PLL (our clock) is powered down by the
+	 * clock framework via .unprepare (clk_disable_unprepare)
+	 */
+	clk_disable_unprepare(inno->phyclk);
+
+	inno->tmdsclock = 0;
+	inno->pixclock = 0;
+
+	return 0;
+}
+
+static int starfive_hdmi_phy_init(struct phy *phy)
+{
+	return 0;
+}
+
+static const struct phy_ops starfive_hdmi_phy_ops = {
+	.owner = THIS_MODULE,
+	.init = starfive_hdmi_phy_init,
+	.power_on = starfive_hdmi_phy_power_on,
+	.power_off = starfive_hdmi_phy_power_off,
+};
+
+static int starfive_hdmi_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device *parent = dev->parent;
+	struct starfive_hdmi_phy *inno;
+	struct phy_provider *phy_provider;
+	struct regmap *mfd_regmap;
+	struct clk_init_data init = {};
+	const char *refoclk_name;
+	int ret;
+
+	inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
+	if (!inno)
+		return -ENOMEM;
+
+	inno->dev = dev;
+
+	/* Get the regmap from the MFD parent device */
+	mfd_regmap = dev_get_regmap(parent, NULL);
+	if (!mfd_regmap) {
+		dev_err(dev, "Failed to get parent regmap\n");
+		return -ENODEV;
+	}
+	inno->regmap = mfd_regmap;
+
+	/* Get the input reference clock */
+	inno->refoclk = devm_clk_get(inno->dev, "refoclk");
+	if (IS_ERR(inno->refoclk)) {
+		ret = PTR_ERR(inno->refoclk);
+		dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
+			ret);
+		return ret;
+	}
+
+	/* We must prepare/enable refoclk here so .set_rate/.recalc_rate work */
+	ret = clk_prepare_enable(inno->refoclk);
+	if (ret) {
+		dev_err(dev, "Failed to enable refoclk: %d\n", ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, inno);
+
+	/* Initialize and register the clock provider */
+	refoclk_name = __clk_get_name(inno->refoclk);
+	init.parent_names = &refoclk_name;
+	init.num_parents = 1;
+	init.flags = 0;
+	init.name = "hdmi_pclk";
+	init.ops = &starfive_hdmi_phy_clk_ops;
+
+	of_property_read_string(dev->of_node, "clock-output-names", &init.name);
+
+	inno->hw.init = &init;
+	inno->phyclk = devm_clk_register(dev, &inno->hw);
+	if (IS_ERR(inno->phyclk)) {
+		ret = PTR_ERR(inno->phyclk);
+		dev_err(dev, "Failed to register clock provider: %d\n", ret);
+		goto err_disable_refoclk;
+	}
+
+	ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, inno->phyclk);
+	if (ret) {
+		dev_err(dev, "Failed to add clock provider: %d\n", ret);
+		goto err_disable_refoclk;
+	}
+
+	ret = clk_set_rate(inno->phyclk, 297000000);
+	if (ret) {
+		dev_err(dev, "Failed to set default rate: %d\n", ret);
+		goto err_disable_refoclk;
+	}
+
+	/* Create and register the PHY provider */
+	inno->phy = devm_phy_create(inno->dev, NULL, &starfive_hdmi_phy_ops);
+	if (IS_ERR(inno->phy)) {
+		ret = PTR_ERR(inno->phy);
+		dev_err(inno->dev, "failed to create HDMI PHY: %d\n", ret);
+		goto err_del_clk_provider;
+	}
+
+	phy_set_drvdata(inno->phy, inno);
+
+	/* Run PHY init */
+	ret = starfive_hdmi_phy_init(inno->phy);
+	if (ret)
+		goto err_del_clk_provider;
+
+	phy_provider = devm_of_phy_provider_register(inno->dev,
+						     of_phy_simple_xlate);
+	ret = PTR_ERR_OR_ZERO(phy_provider);
+	if (ret)
+		goto err_del_clk_provider;
+
+	return 0;
+
+err_del_clk_provider:
+	of_clk_del_provider(dev->of_node);
+err_disable_refoclk:
+	clk_disable_unprepare(inno->refoclk);
+	return ret;
+}
+
+static void starfive_hdmi_phy_remove(struct platform_device *pdev)
+{
+	struct starfive_hdmi_phy *inno = platform_get_drvdata(pdev);
+
+	of_clk_del_provider(pdev->dev.of_node);
+	clk_disable_unprepare(inno->refoclk);
+}
+
+static const struct of_device_id starfive_hdmi_phy_of_match[] = {
+	{ .compatible = "starfive,jh7110-inno-hdmi-phy", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, starfive_hdmi_phy_of_match);
+
+static struct platform_driver starfive_hdmi_phy_driver = {
+	.probe = starfive_hdmi_phy_probe,
+	.remove = starfive_hdmi_phy_remove,
+	.driver = {
+		.name = "starfive-inno-hdmi-phy",
+		.of_match_table = starfive_hdmi_phy_of_match,
+	},
+};
+module_platform_driver(starfive_hdmi_phy_driver);
+
+MODULE_AUTHOR("Michal Wilczynski <m.wilczynski@samsung.com>");
+MODULE_DESCRIPTION("StarFive JH7110 Innosilicon HDMI PHY Driver");
+MODULE_LICENSE("GPL");

-- 
2.34.1

[PATCH RFC 13/13] riscv: dts: starfive: jh7110: Update DT for display subsystem

[Michal Wilczynski]

Activate the display subsystem drivers by refactoring the device tree.

This change wraps the dc8200, hdmi, and voutcrg nodes within the new
vout_subsystem node. This ensures the PD_VOUT power domain is enabled
before the child drivers are probed.

The monolithic hdmi node is replaced with the hdmi_mfd (MFD parent)
node, containing the hdmi_phy and hdmi_controller children.

The voutcrg node is updated to consume the pixel clock from the
&hdmi_phy node instead of the old fixed-clock. The dc8200 node is also
updated to get its pixel clocks from voutcrg's MUXes.

Finally, the old, incorrect hdmitx0-pixel-clock fixed-clock node is
removed.

Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 119 +++++++++++++++++++++++-
 arch/riscv/boot/dts/starfive/jh7110.dtsi        | 111 +++++++++++++++++-----
 2 files changed, 207 insertions(+), 23 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 2eaf01775ef57d884b4d662af3caa83da2d2ad48..ce459e297261393a352061707041db453819885c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -33,6 +33,25 @@ memory@40000000 {
 		bootph-pre-ram;
 	};
 
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* vout applies for space from this CMA
+		 * Without this CMA reservation,
+		 * vout may not work properly.
+		 */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0x0 0x20000000>;
+			alignment = <0x0 0x1000>;
+			alloc-ranges = <0x0 0x70000000 0x0 0x20000000>;
+			linux,cma-default;
+		};
+	};
+
 	gpio-restart {
 		compatible = "gpio-restart";
 		gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
@@ -73,12 +92,47 @@ codec {
 			};
 		};
 	};
+
+	hdmi-connector {
+		compatible = "hdmi-connector";
+		type = "a";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
 };
 
 &cpus {
 	timebase-frequency = <4000000>;
 };
 
+&dc8200 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dpu_port0: port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dpu_out_dpi0: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&hdmi_in>;
+			};
+		};
+
+		dpu_port1: port@1 {
+			reg = <1>;
+		};
+	};
+};
+
 &dvp_clk {
 	clock-frequency = <74250000>;
 };
@@ -99,8 +153,31 @@ &gmac1_rmii_refin {
 	clock-frequency = <50000000>;
 };
 
-&hdmitx0_pixelclk {
-	clock-frequency = <297000000>;
+&hdmi_controller {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&hdmi_pins>;
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+
+			hdmi_in: endpoint {
+				remote-endpoint = <&dpu_out_dpi0>;
+			};
+		};
+
+		hdmi_out_port: port@1 {
+			reg = <1>;
+			hdmi_out_con: endpoint {
+				remote-endpoint = <&hdmi_con_in>;
+			};
+
+		};
+	};
 };
 
 &i2srx_bclk_ext {
@@ -388,6 +465,40 @@ &syscrg {
 };
 
 &sysgpio {
+	hdmi_pins: hdmi-0 {
+		hdmi-cec-pins {
+			pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
+					      GPOEN_SYS_HDMI_CEC_SDA,
+					      GPI_SYS_HDMI_CEC_SDA)>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		hdmi-hpd-pins {
+			pinmux = <GPIOMUX(15, GPOUT_HIGH,
+					      GPOEN_ENABLE,
+					      GPI_SYS_HDMI_HPD)>;
+			input-enable;
+			bias-disable; /* external pull-up */
+		};
+
+		hdmi-scl-pins {
+			pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL,
+					     GPOEN_SYS_HDMI_DDC_SCL,
+					     GPI_SYS_HDMI_DDC_SCL)>;
+			input-enable;
+			bias-pull-up;
+		};
+
+		hdmi-sda-pins {
+			pinmux = <GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA,
+					     GPOEN_SYS_HDMI_DDC_SDA,
+					     GPI_SYS_HDMI_DDC_SDA)>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
 	i2c0_pins: i2c0-0 {
 		i2c-pins {
 			pinmux = <GPIOMUX(57, GPOUT_LOW,
@@ -677,3 +788,7 @@ &U74_3 {
 &U74_4 {
 	cpu-supply = <&vdd_cpu>;
 };
+
+&voutcrg {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0ba74ef046792fd63ed6cf971fa1438609b06fb1..da670a44dcec0f3dae65a2612c24b79f3cdd7d6c 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -283,12 +283,6 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock {
 		#clock-cells = <0>;
 	};
 
-	hdmitx0_pixelclk: hdmitx0-pixel-clock {
-		compatible = "fixed-clock";
-		clock-output-names = "hdmitx0_pixelclk";
-		#clock-cells = <0>;
-	};
-
 	i2srx_bclk_ext: i2srx-bclk-ext-clock {
 		compatible = "fixed-clock";
 		clock-output-names = "i2srx_bclk_ext";
@@ -344,6 +338,14 @@ tdm_ext: tdm-ext-clock {
 		#clock-cells = <0>;
 	};
 
+	xin24m: xin24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "xin24m";
+	};
+
+
 	soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&plic>;
@@ -1203,22 +1205,89 @@ camss: isp@19840000 {
 			status = "disabled";
 		};
 
-		voutcrg: clock-controller@295c0000 {
-			compatible = "starfive,jh7110-voutcrg";
-			reg = <0x0 0x295c0000 0x0 0x10000>;
-			clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
-				 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
-				 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
-				 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
-				 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
-				 <&hdmitx0_pixelclk>;
-			clock-names = "vout_src", "vout_top_ahb",
-				      "vout_top_axi", "vout_top_hdmitx0_mclk",
-				      "i2stx0_bclk", "hdmitx0_pixelclk";
-			resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
-			#clock-cells = <1>;
-			#reset-cells = <1>;
+		vout_subsystem: display-subsystem@29400000 {
+			compatible = "starfive,jh7110-vout-subsystem";
+			reg = <0x0 0x29400000 0x0 0x200000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
 			power-domains = <&pwrc JH7110_PD_VOUT>;
+			clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
+			resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
+
+			dc8200: display@29400000 {
+				compatible = "verisilicon,dc";
+				reg = <0x0 0x29400000 0x0 0x2800>;
+				interrupts = <95>;
+
+				clocks = <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
+					<&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
+					<&voutcrg JH7110_VOUTCLK_DC8200_AHB>,
+					<&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
+					<&voutcrg JH7110_VOUTCLK_DC8200_PIX1>;
+				clock-names = "core", "axi", "ahb", "pix0", "pix1";
+
+				resets = <&voutcrg JH7110_VOUTRST_DC8200_CORE>,
+					 <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
+					 <&voutcrg JH7110_VOUTRST_DC8200_AHB>;
+				reset-names = "core", "axi", "ahb";
+			};
+
+			hdmi_mfd: hdmi@29590000 {
+				compatible = "starfive,jh7110-hdmi-mfd";
+				reg = <0x0 0x29590000 0x0 0x4000>;
+
+				hdmi_phy: phy {
+					compatible = "starfive,jh7110-inno-hdmi-phy";
+
+					clocks = <&xin24m>;
+					clock-names = "refoclk";
+
+					/* Output clock: The variable pixel clock */
+					#clock-cells = <0>;
+					clock-output-names = "hdmi_pclk";
+
+					/* PHY provider for the controller */
+					#phy-cells = <0>;
+				};
+
+				hdmi_controller: controller {
+					compatible = "starfive,jh7110-inno-hdmi-controller";
+					interrupts = <99>;
+
+					clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
+						 <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
+						 <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
+						 <&hdmi_phy>;
+					clock-names = "sys", "mclk", "bclk", "pclk";
+
+					resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
+					reset-names = "hdmi_tx";
+
+					phys = <&hdmi_phy>;
+					phy-names = "hdmi-phy";
+				};
+			};
+
+			voutcrg: clock-controller@295c0000 {
+				compatible = "starfive,jh7110-voutcrg";
+				reg = <0x0 0x295c0000 0x0 0x10000>;
+
+				clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
+					 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
+					 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
+					 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
+					 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
+					 <&hdmi_phy>;
+				clock-names = "vout_src", "vout_top_ahb",
+					      "vout_top_axi", "vout_top_hdmitx0_mclk",
+					      "i2stx0_bclk", "hdmitx0_pixelclk";
+
+				resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
+				#clock-cells = <1>;
+				#reset-cells = <1>;
+			};
 		};
 
 		pcie0: pcie@940000000 {

-- 
2.34.1

Re: [PATCH RFC 13/13] riscv: dts: starfive: jh7110: Update DT for display subsystem

[Icenowy Zheng]

在 2025-11-08星期六的 02:04 +0100，Michal Wilczynski写道：
> Activate the display subsystem drivers by refactoring the device
> tree.
> 
> This change wraps the dc8200, hdmi, and voutcrg nodes within the new
> vout_subsystem node. This ensures the PD_VOUT power domain is enabled
> before the child drivers are probed.

Well a problem exist that some display muxes exist in the vout syscon.

Maybe this should be modelled in the device tree two?

> 
> The monolithic hdmi node is replaced with the hdmi_mfd (MFD parent)
> node, containing the hdmi_phy and hdmi_controller children.
> 
> The voutcrg node is updated to consume the pixel clock from the
> &hdmi_phy node instead of the old fixed-clock. The dc8200 node is
> also
> updated to get its pixel clocks from voutcrg's MUXes.
> 
> Finally, the old, incorrect hdmitx0-pixel-clock fixed-clock node is
> removed.
> 
> Signed-off-by: Michal Wilczynski <m.wilczynski@samsung.com>
> ---
>  arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 119
> +++++++++++++++++++++++-
>  arch/riscv/boot/dts/starfive/jh7110.dtsi        | 111
> +++++++++++++++++-----
>  2 files changed, 207 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> index
> 2eaf01775ef57d884b4d662af3caa83da2d2ad48..ce459e297261393a35206170704
> 1db453819885c 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> @@ -33,6 +33,25 @@ memory@40000000 {
>                 bootph-pre-ram;
>         };
>  
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               /* vout applies for space from this CMA
> +                * Without this CMA reservation,
> +                * vout may not work properly.
> +                */
> +               linux,cma {
> +                       compatible = "shared-dma-pool";
> +                       reusable;
> +                       size = <0x0 0x20000000>;
> +                       alignment = <0x0 0x1000>;
> +                       alloc-ranges = <0x0 0x70000000 0x0
> 0x20000000>;
> +                       linux,cma-default;
> +               };
> +       };
> +
>         gpio-restart {
>                 compatible = "gpio-restart";
>                 gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> @@ -73,12 +92,47 @@ codec {
>                         };
>                 };
>         };
> +
> +       hdmi-connector {
> +               compatible = "hdmi-connector";
> +               type = "a";
> +
> +               port {
> +                       hdmi_con_in: endpoint {
> +                               remote-endpoint = <&hdmi_out_con>;
> +                       };
> +               };
> +       };
>  };
>  
>  &cpus {
>         timebase-frequency = <4000000>;
>  };
>  
> +&dc8200 {
> +       status = "okay";
> +
> +       ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               dpu_port0: port@0 {
> +                       reg = <0>;
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +
> +                       dpu_out_dpi0: endpoint@0 {
> +                               reg = <0>;
> +                               remote-endpoint = <&hdmi_in>;
> +                       };
> +               };
> +
> +               dpu_port1: port@1 {
> +                       reg = <1>;
> +               };
> +       };
> +};
> +
>  &dvp_clk {
>         clock-frequency = <74250000>;
>  };
> @@ -99,8 +153,31 @@ &gmac1_rmii_refin {
>         clock-frequency = <50000000>;
>  };
>  
> -&hdmitx0_pixelclk {
> -       clock-frequency = <297000000>;
> +&hdmi_controller {
> +       status = "okay";
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&hdmi_pins>;
> +
> +       ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               port@0 {
> +                       reg = <0>;
> +
> +                       hdmi_in: endpoint {
> +                               remote-endpoint = <&dpu_out_dpi0>;
> +                       };
> +               };
> +
> +               hdmi_out_port: port@1 {
> +                       reg = <1>;
> +                       hdmi_out_con: endpoint {
> +                               remote-endpoint = <&hdmi_con_in>;
> +                       };
> +
> +               };
> +       };
>  };
>  
>  &i2srx_bclk_ext {
> @@ -388,6 +465,40 @@ &syscrg {
>  };
>  
>  &sysgpio {
> +       hdmi_pins: hdmi-0 {
> +               hdmi-cec-pins {
> +                       pinmux = <GPIOMUX(14, GPOUT_SYS_HDMI_CEC_SDA,
> +                                             GPOEN_SYS_HDMI_CEC_SDA,
> +                                             GPI_SYS_HDMI_CEC_SDA)>;
> +                       input-enable;
> +                       bias-pull-up;
> +               };
> +
> +               hdmi-hpd-pins {
> +                       pinmux = <GPIOMUX(15, GPOUT_HIGH,
> +                                             GPOEN_ENABLE,
> +                                             GPI_SYS_HDMI_HPD)>;
> +                       input-enable;
> +                       bias-disable; /* external pull-up */
> +               };
> +
> +               hdmi-scl-pins {
> +                       pinmux = <GPIOMUX(0, GPOUT_SYS_HDMI_DDC_SCL,
> +                                            GPOEN_SYS_HDMI_DDC_SCL,
> +                                            GPI_SYS_HDMI_DDC_SCL)>;
> +                       input-enable;
> +                       bias-pull-up;
> +               };
> +
> +               hdmi-sda-pins {
> +                       pinmux = <GPIOMUX(1, GPOUT_SYS_HDMI_DDC_SDA,
> +                                            GPOEN_SYS_HDMI_DDC_SDA,
> +                                            GPI_SYS_HDMI_DDC_SDA)>;
> +                       input-enable;
> +                       bias-pull-up;
> +               };
> +       };
> +
>         i2c0_pins: i2c0-0 {
>                 i2c-pins {
>                         pinmux = <GPIOMUX(57, GPOUT_LOW,
> @@ -677,3 +788,7 @@ &U74_3 {
>  &U74_4 {
>         cpu-supply = <&vdd_cpu>;
>  };
> +
> +&voutcrg {
> +       status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index
> 0ba74ef046792fd63ed6cf971fa1438609b06fb1..da670a44dcec0f3dae65a2612c2
> 4b79f3cdd7d6c 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -283,12 +283,6 @@ gmac1_rmii_refin: gmac1-rmii-refin-clock {
>                 #clock-cells = <0>;
>         };
>  
> -       hdmitx0_pixelclk: hdmitx0-pixel-clock {
> -               compatible = "fixed-clock";
> -               clock-output-names = "hdmitx0_pixelclk";
> -               #clock-cells = <0>;
> -       };
> -
>         i2srx_bclk_ext: i2srx-bclk-ext-clock {
>                 compatible = "fixed-clock";
>                 clock-output-names = "i2srx_bclk_ext";
> @@ -344,6 +338,14 @@ tdm_ext: tdm-ext-clock {
>                 #clock-cells = <0>;
>         };
>  
> +       xin24m: xin24m {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <24000000>;
> +               clock-output-names = "xin24m";
> +       };
> +
> +
>         soc {
>                 compatible = "simple-bus";
>                 interrupt-parent = <&plic>;
> @@ -1203,22 +1205,89 @@ camss: isp@19840000 {
>                         status = "disabled";
>                 };
>  
> -               voutcrg: clock-controller@295c0000 {
> -                       compatible = "starfive,jh7110-voutcrg";
> -                       reg = <0x0 0x295c0000 0x0 0x10000>;
> -                       clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
> -                                <&syscrg
> JH7110_SYSCLK_VOUT_TOP_AHB>,
> -                                <&syscrg
> JH7110_SYSCLK_VOUT_TOP_AXI>,
> -                                <&syscrg
> JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> -                                <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
> -                                <&hdmitx0_pixelclk>;
> -                       clock-names = "vout_src", "vout_top_ahb",
> -                                     "vout_top_axi",
> "vout_top_hdmitx0_mclk",
> -                                     "i2stx0_bclk",
> "hdmitx0_pixelclk";
> -                       resets = <&syscrg
> JH7110_SYSRST_VOUT_TOP_SRC>;
> -                       #clock-cells = <1>;
> -                       #reset-cells = <1>;
> +               vout_subsystem: display-subsystem@29400000 {
> +                       compatible = "starfive,jh7110-vout-
> subsystem";
> +                       reg = <0x0 0x29400000 0x0 0x200000>;
> +                       #address-cells = <2>;
> +                       #size-cells = <2>;
> +                       ranges;
> +
>                         power-domains = <&pwrc JH7110_PD_VOUT>;
> +                       clocks = <&syscrg
> JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
> +                       resets = <&syscrg
> JH7110_SYSRST_NOC_BUS_DISP_AXI>;
> +
> +                       dc8200: display@29400000 {
> +                               compatible = "verisilicon,dc";
> +                               reg = <0x0 0x29400000 0x0 0x2800>;
> +                               interrupts = <95>;
> +
> +                               clocks = <&voutcrg
> JH7110_VOUTCLK_DC8200_CORE>,
> +                                       <&voutcrg
> JH7110_VOUTCLK_DC8200_AXI>,
> +                                       <&voutcrg
> JH7110_VOUTCLK_DC8200_AHB>,
> +                                       <&voutcrg
> JH7110_VOUTCLK_DC8200_PIX0>,
> +                                       <&voutcrg
> JH7110_VOUTCLK_DC8200_PIX1>;
> +                               clock-names = "core", "axi", "ahb",
> "pix0", "pix1";
> +
> +                               resets = <&voutcrg
> JH7110_VOUTRST_DC8200_CORE>,
> +                                        <&voutcrg
> JH7110_VOUTRST_DC8200_AXI>,
> +                                        <&voutcrg
> JH7110_VOUTRST_DC8200_AHB>;
> +                               reset-names = "core", "axi", "ahb";
> +                       };
> +
> +                       hdmi_mfd: hdmi@29590000 {
> +                               compatible = "starfive,jh7110-hdmi-
> mfd";
> +                               reg = <0x0 0x29590000 0x0 0x4000>;
> +
> +                               hdmi_phy: phy {
> +                                       compatible =
> "starfive,jh7110-inno-hdmi-phy";
> +
> +                                       clocks = <&xin24m>;
> +                                       clock-names = "refoclk";
> +
> +                                       /* Output clock: The variable
> pixel clock */
> +                                       #clock-cells = <0>;
> +                                       clock-output-names =
> "hdmi_pclk";
> +
> +                                       /* PHY provider for the
> controller */
> +                                       #phy-cells = <0>;
> +                               };
> +
> +                               hdmi_controller: controller {
> +                                       compatible =
> "starfive,jh7110-inno-hdmi-controller";
> +                                       interrupts = <99>;
> +
> +                                       clocks = <&voutcrg
> JH7110_VOUTCLK_HDMI_TX_SYS>,
> +                                                <&voutcrg
> JH7110_VOUTCLK_HDMI_TX_MCLK>,
> +                                                <&voutcrg
> JH7110_VOUTCLK_HDMI_TX_BCLK>,
> +                                                <&hdmi_phy>;
> +                                       clock-names = "sys", "mclk",
> "bclk", "pclk";
> +
> +                                       resets = <&voutcrg
> JH7110_VOUTRST_HDMI_TX_HDMI>;
> +                                       reset-names = "hdmi_tx";
> +
> +                                       phys = <&hdmi_phy>;
> +                                       phy-names = "hdmi-phy";
> +                               };
> +                       };
> +
> +                       voutcrg: clock-controller@295c0000 {
> +                               compatible = "starfive,jh7110-
> voutcrg";
> +                               reg = <0x0 0x295c0000 0x0 0x10000>;
> +
> +                               clocks = <&syscrg
> JH7110_SYSCLK_VOUT_SRC>,
> +                                        <&syscrg
> JH7110_SYSCLK_VOUT_TOP_AHB>,
> +                                        <&syscrg
> JH7110_SYSCLK_VOUT_TOP_AXI>,
> +                                        <&syscrg
> JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
> +                                        <&syscrg
> JH7110_SYSCLK_I2STX0_BCLK>,
> +                                        <&hdmi_phy>;
> +                               clock-names = "vout_src",
> "vout_top_ahb",
> +                                             "vout_top_axi",
> "vout_top_hdmitx0_mclk",
> +                                             "i2stx0_bclk",
> "hdmitx0_pixelclk";
> +
> +                               resets = <&syscrg
> JH7110_SYSRST_VOUT_TOP_SRC>;
> +                               #clock-cells = <1>;
> +                               #reset-cells = <1>;
> +                       };
>                 };
>  
>                 pcie0: pcie@940000000 {
> 

Re: [PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1219 bytes --]

On Sat, Nov 08, 2025 at 02:04:34AM +0100, Michal Wilczynski wrote:
> This series enables the display subsystem on the StarFive JH7110 SoC.
> This hardware has a complex set of dependencies that this series aims to
> solve.
> 
> I believe this is a PHY tuning issue that can be fixed in the new
> phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
> I plan to continue debugging these modes and will submit follow up fixes
> as needed.
> 
> The core architectural plumbing is sound and ready for review.
> 
> Notes:
> - The JH7110 does not have a centralized MAINTAINERS entry like the
>   TH1520, and driver maintainership seems fragmented. I have therefore
>   added a MAINTAINERS entry for the display subsystem and am willing to
>   help with its maintenance.

Yeah, bunch of different folks wrote the drivers, so lots of entries.
Pretty much all as you've done here, authors are responsible for the
individual components and Emil is the platform maintainer but
responsible for most drivers.

Do you need any feedback dt wise on the RFC, or is it too likely that
we'll both waste our breath if the DRM folks don't approve of your
approach for the rest of this series?

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Re: [PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Michal Wilczynski]

On 11/10/25 20:35, Conor Dooley wrote:
> On Sat, Nov 08, 2025 at 02:04:34AM +0100, Michal Wilczynski wrote:
>> This series enables the display subsystem on the StarFive JH7110 SoC.
>> This hardware has a complex set of dependencies that this series aims to
>> solve.
>>
>> I believe this is a PHY tuning issue that can be fixed in the new
>> phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
>> I plan to continue debugging these modes and will submit follow up fixes
>> as needed.
>>
>> The core architectural plumbing is sound and ready for review.
>>
>> Notes:
>> - The JH7110 does not have a centralized MAINTAINERS entry like the
>>   TH1520, and driver maintainership seems fragmented. I have therefore
>>   added a MAINTAINERS entry for the display subsystem and am willing to
>>   help with its maintenance.
> 
> Yeah, bunch of different folks wrote the drivers, so lots of entries.
> Pretty much all as you've done here, authors are responsible for the
> individual components and Emil is the platform maintainer but
> responsible for most drivers.
> 
> Do you need any feedback dt wise on the RFC, or is it too likely that
> we'll both waste our breath if the DRM folks don't approve of your
> approach for the rest of this series?

Hi Conor,

Thank you for your response.

That's a fair point about the risk of the DRM approach being rejected.
While I can't be certain, I'm hopeful that part is relatively
straightforward, as it primarily integrates other recently reviewed
(though not yet merged) components like the inno-hdmi bridge and dc8200
drivers.

To be honest, I was more concerned that the DT part of the series would
be more problematic. Given that, I would find it very helpful to get
your feedback on the DT aspects now, if you have the time.

Best regards,
-- 
Michal Wilczynski <m.wilczynski@samsung.com>

Re: [PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Conor Dooley]

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On Tue, Nov 11, 2025 at 04:33:28PM +0100, Michal Wilczynski wrote:
> 
> 
> On 11/10/25 20:35, Conor Dooley wrote:
> > On Sat, Nov 08, 2025 at 02:04:34AM +0100, Michal Wilczynski wrote:
> >> This series enables the display subsystem on the StarFive JH7110 SoC.
> >> This hardware has a complex set of dependencies that this series aims to
> >> solve.
> >>
> >> I believe this is a PHY tuning issue that can be fixed in the new
> >> phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
> >> I plan to continue debugging these modes and will submit follow up fixes
> >> as needed.
> >>
> >> The core architectural plumbing is sound and ready for review.
> >>
> >> Notes:
> >> - The JH7110 does not have a centralized MAINTAINERS entry like the
> >>   TH1520, and driver maintainership seems fragmented. I have therefore
> >>   added a MAINTAINERS entry for the display subsystem and am willing to
> >>   help with its maintenance.
> > 
> > Yeah, bunch of different folks wrote the drivers, so lots of entries.
> > Pretty much all as you've done here, authors are responsible for the
> > individual components and Emil is the platform maintainer but
> > responsible for most drivers.
> > 
> > Do you need any feedback dt wise on the RFC, or is it too likely that
> > we'll both waste our breath if the DRM folks don't approve of your
> > approach for the rest of this series?
> 
> Hi Conor,
> 
> Thank you for your response.
> 
> That's a fair point about the risk of the DRM approach being rejected.
> While I can't be certain, I'm hopeful that part is relatively
> straightforward, as it primarily integrates other recently reviewed
> (though not yet merged) components like the inno-hdmi bridge and dc8200
> drivers.
> 
> To be honest, I was more concerned that the DT part of the series would
> be more problematic. Given that, I would find it very helpful to get
> your feedback on the DT aspects now, if you have the time.

Right. You'll definitely want some actual DRM people to weigh in though
before making changes, I am really not familiar enough with this type of
hardware to know if the breakdown is correct.

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Re: [PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Conor Dooley]

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On Tue, Nov 11, 2025 at 06:14:48PM +0000, Conor Dooley wrote:
> On Tue, Nov 11, 2025 at 04:33:28PM +0100, Michal Wilczynski wrote:
> > 
> > 
> > On 11/10/25 20:35, Conor Dooley wrote:
> > > On Sat, Nov 08, 2025 at 02:04:34AM +0100, Michal Wilczynski wrote:
> > >> This series enables the display subsystem on the StarFive JH7110 SoC.
> > >> This hardware has a complex set of dependencies that this series aims to
> > >> solve.
> > >>
> > >> I believe this is a PHY tuning issue that can be fixed in the new
> > >> phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
> > >> I plan to continue debugging these modes and will submit follow up fixes
> > >> as needed.
> > >>
> > >> The core architectural plumbing is sound and ready for review.
> > >>
> > >> Notes:
> > >> - The JH7110 does not have a centralized MAINTAINERS entry like the
> > >>   TH1520, and driver maintainership seems fragmented. I have therefore
> > >>   added a MAINTAINERS entry for the display subsystem and am willing to
> > >>   help with its maintenance.
> > > 
> > > Yeah, bunch of different folks wrote the drivers, so lots of entries.
> > > Pretty much all as you've done here, authors are responsible for the
> > > individual components and Emil is the platform maintainer but
> > > responsible for most drivers.
> > > 
> > > Do you need any feedback dt wise on the RFC, or is it too likely that
> > > we'll both waste our breath if the DRM folks don't approve of your
> > > approach for the rest of this series?
> > 
> > Hi Conor,
> > 
> > Thank you for your response.
> > 
> > That's a fair point about the risk of the DRM approach being rejected.
> > While I can't be certain, I'm hopeful that part is relatively
> > straightforward, as it primarily integrates other recently reviewed
> > (though not yet merged) components like the inno-hdmi bridge and dc8200
> > drivers.
> > 
> > To be honest, I was more concerned that the DT part of the series would
> > be more problematic. Given that, I would find it very helpful to get
> > your feedback on the DT aspects now, if you have the time.
> 
> Right. You'll definitely want some actual DRM people to weigh in though
> before making changes, I am really not familiar enough with this type of
> hardware to know if the breakdown is correct.

It looks generally sane to me chief, but as I said I am not really
familiar enough with this sort of hardware to have a real take on it.
Sorry, you'll need to get your affirmation about how you've laid stuff
out elsewhere :/

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Re: [PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Michal Wilczynski]

On 11/11/25 19:37, Conor Dooley wrote:
> On Tue, Nov 11, 2025 at 06:14:48PM +0000, Conor Dooley wrote:
>> On Tue, Nov 11, 2025 at 04:33:28PM +0100, Michal Wilczynski wrote:
>>>
>>>
>>> On 11/10/25 20:35, Conor Dooley wrote:
>>>> On Sat, Nov 08, 2025 at 02:04:34AM +0100, Michal Wilczynski wrote:
>>>>> This series enables the display subsystem on the StarFive JH7110 SoC.
>>>>> This hardware has a complex set of dependencies that this series aims to
>>>>> solve.
>>>>>
>>>>> I believe this is a PHY tuning issue that can be fixed in the new
>>>>> phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
>>>>> I plan to continue debugging these modes and will submit follow up fixes
>>>>> as needed.
>>>>>
>>>>> The core architectural plumbing is sound and ready for review.
>>>>>
>>>>> Notes:
>>>>> - The JH7110 does not have a centralized MAINTAINERS entry like the
>>>>>   TH1520, and driver maintainership seems fragmented. I have therefore
>>>>>   added a MAINTAINERS entry for the display subsystem and am willing to
>>>>>   help with its maintenance.
>>>>
>>>> Yeah, bunch of different folks wrote the drivers, so lots of entries.
>>>> Pretty much all as you've done here, authors are responsible for the
>>>> individual components and Emil is the platform maintainer but
>>>> responsible for most drivers.
>>>>
>>>> Do you need any feedback dt wise on the RFC, or is it too likely that
>>>> we'll both waste our breath if the DRM folks don't approve of your
>>>> approach for the rest of this series?
>>>
>>> Hi Conor,
>>>
>>> Thank you for your response.
>>>
>>> That's a fair point about the risk of the DRM approach being rejected.
>>> While I can't be certain, I'm hopeful that part is relatively
>>> straightforward, as it primarily integrates other recently reviewed
>>> (though not yet merged) components like the inno-hdmi bridge and dc8200
>>> drivers.
>>>
>>> To be honest, I was more concerned that the DT part of the series would
>>> be more problematic. Given that, I would find it very helpful to get
>>> your feedback on the DT aspects now, if you have the time.
>>
>> Right. You'll definitely want some actual DRM people to weigh in though
>> before making changes, I am really not familiar enough with this type of
>> hardware to know if the breakdown is correct.
> 
> It looks generally sane to me chief, but as I said I am not really
> familiar enough with this sort of hardware to have a real take on it.
> Sorry, you'll need to get your affirmation about how you've laid stuff
> out elsewhere :/

Thanks for the look, Conor.

I appreciate the sanity check on the DT side. I'll focus on getting the
necessary feedback from the DRM maintainers regarding the architectural
breakdown before spinning a v2.

[Adding Dmitry Baryshkov and highlighting Maxime, Heiko, and Robert]

Could you folks take a brief look at the driver split in this series?

Conor has reviewed the DT bindings and they look sane to him, but we
need to verify that the architectural split between the
phy-jh7110-inno-hdmi and the DRM bridge driver is acceptable for this
Innosilicon IP.

I am particularly interested if the current handling of the PHY tuning
parameters (as described in the cover letter) fits the modern DRM
bridge/PHY paradigm, or if this should be modeled differently given the
similarities to Rockchip implementations.

Best regards,
-- 
Michal Wilczynski <m.wilczynski@samsung.com>

Re: [PATCH RFC 00/13] drm: starfive: jh7110: Enable display subsystem

[Michal Wilczynski]

On 11/13/25 15:57, Michal Wilczynski wrote:
> 
> 
> On 11/11/25 19:37, Conor Dooley wrote:
>> On Tue, Nov 11, 2025 at 06:14:48PM +0000, Conor Dooley wrote:
>>> On Tue, Nov 11, 2025 at 04:33:28PM +0100, Michal Wilczynski wrote:
>>>>
>>>>
>>>> On 11/10/25 20:35, Conor Dooley wrote:
>>>>> On Sat, Nov 08, 2025 at 02:04:34AM +0100, Michal Wilczynski wrote:
>>>>>> This series enables the display subsystem on the StarFive JH7110 SoC.
>>>>>> This hardware has a complex set of dependencies that this series aims to
>>>>>> solve.
>>>>>>
>>>>>> I believe this is a PHY tuning issue that can be fixed in the new
>>>>>> phy-jh7110-inno-hdmi.c driver without changing the overall architecture.
>>>>>> I plan to continue debugging these modes and will submit follow up fixes
>>>>>> as needed.
>>>>>>
>>>>>> The core architectural plumbing is sound and ready for review.
>>>>>>
>>>>>> Notes:
>>>>>> - The JH7110 does not have a centralized MAINTAINERS entry like the
>>>>>>   TH1520, and driver maintainership seems fragmented. I have therefore
>>>>>>   added a MAINTAINERS entry for the display subsystem and am willing to
>>>>>>   help with its maintenance.
>>>>>
>>>>> Yeah, bunch of different folks wrote the drivers, so lots of entries.
>>>>> Pretty much all as you've done here, authors are responsible for the
>>>>> individual components and Emil is the platform maintainer but
>>>>> responsible for most drivers.
>>>>>
>>>>> Do you need any feedback dt wise on the RFC, or is it too likely that
>>>>> we'll both waste our breath if the DRM folks don't approve of your
>>>>> approach for the rest of this series?
>>>>
>>>> Hi Conor,
>>>>
>>>> Thank you for your response.
>>>>
>>>> That's a fair point about the risk of the DRM approach being rejected.
>>>> While I can't be certain, I'm hopeful that part is relatively
>>>> straightforward, as it primarily integrates other recently reviewed
>>>> (though not yet merged) components like the inno-hdmi bridge and dc8200
>>>> drivers.
>>>>
>>>> To be honest, I was more concerned that the DT part of the series would
>>>> be more problematic. Given that, I would find it very helpful to get
>>>> your feedback on the DT aspects now, if you have the time.
>>>
>>> Right. You'll definitely want some actual DRM people to weigh in though
>>> before making changes, I am really not familiar enough with this type of
>>> hardware to know if the breakdown is correct.
>>
>> It looks generally sane to me chief, but as I said I am not really
>> familiar enough with this sort of hardware to have a real take on it.
>> Sorry, you'll need to get your affirmation about how you've laid stuff
>> out elsewhere :/
> 
> Thanks for the look, Conor.
> 
> I appreciate the sanity check on the DT side. I'll focus on getting the
> necessary feedback from the DRM maintainers regarding the architectural
> breakdown before spinning a v2.
> 
> [Adding Dmitry Baryshkov and highlighting Maxime, Heiko, and Robert]
> 
> Could you folks take a brief look at the driver split in this series?
> 
> Conor has reviewed the DT bindings and they look sane to him, but we
> need to verify that the architectural split between the
> phy-jh7110-inno-hdmi and the DRM bridge driver is acceptable for this
> Innosilicon IP.
> 
> I am particularly interested if the current handling of the PHY tuning
> parameters (as described in the cover letter) fits the modern DRM
> bridge/PHY paradigm, or if this should be modeled differently given the
> similarities to Rockchip implementations.
> 
> Best regards,

Hi folks,

Just a gentle ping on this series.

I am primarily waiting on architectural feedback regarding the split
between the DRM bridge and the PHY driver.

If I don't receive any objections soon, I'll assume the current
structure is acceptable and proceed with addressing the known PHY tuning
issues for v2.

Best regards,
-- 
Michal Wilczynski <m.wilczynski@samsung.com>