* [PATCH v2 0/2] Add support for Agilex3 SoCFPGA board @ 2025-11-11 6:17 niravkumarlaxmidas.rabara 2025-11-11 6:17 ` [PATCH v2 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara 2025-11-11 6:17 ` [PATCH v2 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara 0 siblings, 2 replies; 5+ messages in thread From: niravkumarlaxmidas.rabara @ 2025-11-11 6:17 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel Cc: Niravkumar L Rabara From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Agilex3 SoCFPGA development kit is a low cost and small form factor development kit similar to Agilex5 013b board. Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference being the number of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5. https://www.altera.com/products/devkit/a1jui000005pw9bmas/agilex-3-fpga-and-soc-c-series-development-kit This series includes: - The addition of the Agilex3 compatible in DT bindings. - The initial board device tree support for the Agilex3 SoCFPGA. Note: The patch 2 depends on the series: "Add iommu supports" https://lore.kernel.org/all/cover.1760486497.git.khairul.anuar.romli@altera.com/ Patch series "Add iommu supports" is applied to socfpga maintainer's tree https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git/log/?h=socfpga_dts_for_v6.19 v2 changes: - Add separate agilex3 compatible. - Use separate dtsi file for Agilex3. v1 link: https://lore.kernel.org/all/cover.1762756191.git.niravkumarlaxmidas.rabara@altera.com/ Niravkumar L Rabara (2): dt-bindings: intel: Add Agilex3 SoCFPGA board arm64: dts: socfpga: add Agilex3 board .../bindings/arm/intel,socfpga.yaml | 5 + arch/arm64/boot/dts/intel/Makefile | 1 + .../arm64/boot/dts/intel/socfpga_agilex3.dtsi | 17 +++ .../boot/dts/intel/socfpga_agilex3_socdk.dts | 126 ++++++++++++++++++ 4 files changed, 149 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-11 6:17 [PATCH v2 0/2] Add support for Agilex3 SoCFPGA board niravkumarlaxmidas.rabara @ 2025-11-11 6:17 ` niravkumarlaxmidas.rabara 2025-11-11 7:51 ` Krzysztof Kozlowski 2025-11-11 6:17 ` [PATCH v2 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara 1 sibling, 1 reply; 5+ messages in thread From: niravkumarlaxmidas.rabara @ 2025-11-11 6:17 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel Cc: Niravkumar L Rabara From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Add compatible string for Agilex3 SoCFPGA board, which shares the same architecture as Agilex5 but with two fewer CPU cores. Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> --- v2 changes: - Add separate agilex3 compatible instead of using agilex5 context. v1 link: https://lore.kernel.org/all/51ecc7f4eb7e419c00ee51fc26156e25686dfece.1762756191.git.niravkumarlaxmidas.rabara@altera.com/ Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml index cf7a91dfec8a..e5a8141dc6cb 100644 --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml @@ -21,6 +21,11 @@ properties: - intel,socfpga-agilex-n6000 - intel,socfpga-agilex-socdk - const: intel,socfpga-agilex + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 - description: Agilex5 boards items: - enum: -- 2.25.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-11 6:17 ` [PATCH v2 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara @ 2025-11-11 7:51 ` Krzysztof Kozlowski 2025-11-12 0:34 ` Niravkumar L Rabara 0 siblings, 1 reply; 5+ messages in thread From: Krzysztof Kozlowski @ 2025-11-11 7:51 UTC (permalink / raw) To: niravkumarlaxmidas.rabara Cc: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On Tue, Nov 11, 2025 at 02:17:38PM +0800, niravkumarlaxmidas.rabara@altera.com wrote: > From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> > > Add compatible string for Agilex3 SoCFPGA board, which shares the same > architecture as Agilex5 but with two fewer CPU cores. > > Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> > --- > > v2 changes: > - Add separate agilex3 compatible instead of using agilex5 context. > > v1 link: > https://lore.kernel.org/all/51ecc7f4eb7e419c00ee51fc26156e25686dfece.1762756191.git.niravkumarlaxmidas.rabara@altera.com/ > > Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml > index cf7a91dfec8a..e5a8141dc6cb 100644 > --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml > +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml > @@ -21,6 +21,11 @@ properties: > - intel,socfpga-agilex-n6000 > - intel,socfpga-agilex-socdk > - const: intel,socfpga-agilex > + - description: Agilex3 boards > + items: > + - enum: > + - intel,socfpga-agilex3-socdk > + - const: intel,socfpga-agilex3 This is confusing, where is the fallback? You said this is fully compatible with Agilex5, no? Best regards, Krzysztof ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: intel: Add Agilex3 SoCFPGA board 2025-11-11 7:51 ` Krzysztof Kozlowski @ 2025-11-12 0:34 ` Niravkumar L Rabara 0 siblings, 0 replies; 5+ messages in thread From: Niravkumar L Rabara @ 2025-11-12 0:34 UTC (permalink / raw) To: Krzysztof Kozlowski Cc: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel On 11/11/2025 3:51 pm, Krzysztof Kozlowski wrote: > On Tue, Nov 11, 2025 at 02:17:38PM +0800, niravkumarlaxmidas.rabara@altera.com wrote: >> From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >> >> Add compatible string for Agilex3 SoCFPGA board, which shares the same >> architecture as Agilex5 but with two fewer CPU cores. >> >> Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> >> --- >> >> v2 changes: >> - Add separate agilex3 compatible instead of using agilex5 context. >> >> v1 link: >> https://lore.kernel.org/all/51ecc7f4eb7e419c00ee51fc26156e25686dfece.1762756191.git.niravkumarlaxmidas.rabara@altera.com/ >> >> Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >> index cf7a91dfec8a..e5a8141dc6cb 100644 >> --- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >> +++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml >> @@ -21,6 +21,11 @@ properties: >> - intel,socfpga-agilex-n6000 >> - intel,socfpga-agilex-socdk >> - const: intel,socfpga-agilex >> + - description: Agilex3 boards >> + items: >> + - enum: >> + - intel,socfpga-agilex3-socdk >> + - const: intel,socfpga-agilex3 > > This is confusing, where is the fallback? You said this is fully > compatible with Agilex5, no? > > Best regards, > Krzysztof > Yes, I should have "const: intel,socfpga-agilex5" as well for the fallback. + - description: Agilex3 boards + items: + - enum: + - intel,socfpga-agilex3-socdk + - const: intel,socfpga-agilex3 + - const: intel,socfpga-agilex5 I will add this in v3. Thanks, Nirav ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 2/2] arm64: dts: socfpga: add Agilex3 board 2025-11-11 6:17 [PATCH v2 0/2] Add support for Agilex3 SoCFPGA board niravkumarlaxmidas.rabara 2025-11-11 6:17 ` [PATCH v2 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara @ 2025-11-11 6:17 ` niravkumarlaxmidas.rabara 1 sibling, 0 replies; 5+ messages in thread From: niravkumarlaxmidas.rabara @ 2025-11-11 6:17 UTC (permalink / raw) To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-kernel Cc: Niravkumar L Rabara From: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> Agilex3 SoCFPGA development kit is a small form factor board similar to Agilex5 013b board. Agilex3 SoCFPGA is derived from Agilex5 SoCFPGA, with the main difference of CPU cores — Agilex3 has 2 cores compared to 4 in Agilex5. Signed-off-by: Niravkumar L Rabara <niravkumarlaxmidas.rabara@altera.com> --- v2 changes: - Use separate dtsi file for agilex3 instead of using agilex5 dtsi. v1 link: https://lore.kernel.org/all/aa19e005a2aa2aab63c8fe8cbaee7f59c416690f.1762756191.git.niravkumarlaxmidas.rabara@altera.com/ arch/arm64/boot/dts/intel/Makefile | 1 + .../arm64/boot/dts/intel/socfpga_agilex3.dtsi | 17 +++ .../boot/dts/intel/socfpga_agilex3_socdk.dts | 126 ++++++++++++++++++ 3 files changed, 144 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 391d5cbe50b3..a117268267ee 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex3_socdk.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_nand.dtb \ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi new file mode 100644 index 000000000000..4e55513d93c4 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ + +/dts-v1/; +#include "socfpga_agilex5.dtsi" + +/ { + compatible = "intel,socfpga-agilex3", "intel,socfpga-agilex5"; +}; + +/* Agilex3 has only 2 CPUs */ +&{/cpus} { + /delete-node/ cpu@2; + /delete-node/ cpu@3; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts new file mode 100644 index 000000000000..fe353972fbae --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025, Altera Corporation + */ +#include "socfpga_agilex3.dtsi" + +/ { + model = "SoCFPGA Agilex3 SoCDK"; + compatible = "intel,socfpga-agilex3-socdk", "intel,socfpga-agilex3"; + + aliases { + serial0 = &uart0; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "hps_led0"; + gpios = <&porta 1 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&porta 12 GPIO_ACTIVE_HIGH>; + }; + + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0x0 0x80000000 0x0 0x0>; + }; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&emac2_phy0>; + max-frame-size = <9000>; + + mdio0 { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + emac2_phy0: ethernet-phy@0 { + reg = <0>; + rxc-skew-ps = <0>; + rxdv-skew-ps = <0>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txc-skew-ps = <0>; + txen-skew-ps = <60>; + txd0-skew-ps = <60>; + txd1-skew-ps = <60>; + txd2-skew-ps = <60>; + txd3-skew-ps = <60>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&qspi { + status = "okay"; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + m25p,fast-read; + cdns,read-delay = <2>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "u-boot"; + reg = <0x0 0x00600000>; + }; + + root: partition@4200000 { + label = "root"; + reg = <0x00600000 0x03a00000>; + }; + }; + }; +}; + +&smmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-11-12 0:34 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-11 6:17 [PATCH v2 0/2] Add support for Agilex3 SoCFPGA board niravkumarlaxmidas.rabara 2025-11-11 6:17 ` [PATCH v2 1/2] dt-bindings: intel: Add " niravkumarlaxmidas.rabara 2025-11-11 7:51 ` Krzysztof Kozlowski 2025-11-12 0:34 ` Niravkumar L Rabara 2025-11-11 6:17 ` [PATCH v2 2/2] arm64: dts: socfpga: add Agilex3 board niravkumarlaxmidas.rabara
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