From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: Frank Li <Frank.li@nxp.com>
Cc: Guoniu Zhou <guoniu.zhou@oss.nxp.com>,
Rui Miguel Silva <rmfrfs@gmail.com>,
Martin Kepplinger <martink@posteo.de>,
Purism Kernel Team <kernel@puri.sm>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <s.hauer@pengutronix.de>,
Pengutronix Kernel Team <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Guoniu Zhou <guoniu.zhou@nxp.com>,
Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v7 1/5] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible string
Date: Tue, 11 Nov 2025 23:10:25 +0200 [thread overview]
Message-ID: <20251111211025.GA26805@pendragon.ideasonboard.com> (raw)
In-Reply-To: <aROg99ryy6RTZZIx@lizhi-Precision-Tower-5810>
On Tue, Nov 11, 2025 at 03:47:51PM -0500, Frank Li wrote:
> On Mon, Oct 27, 2025 at 02:05:37AM +0200, Laurent Pinchart wrote:
> > On Thu, Oct 23, 2025 at 05:19:42PM +0800, Guoniu Zhou wrote:
> > > From: Guoniu Zhou <guoniu.zhou@nxp.com>
> > >
> > > The CSI-2 receiver in the i.MX8ULP is almost identical to the version
> > > present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk
> > > clock as the input clock for its APB interface of Control and Status
> > > register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and
> > > increase maxItems of Clocks (clock-names) to 4 from 3. And keep the
> > > same restriction for existing compatible.
> > >
> > > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > > Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
> > > ---
> > > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 41 ++++++++++++++++++++--
> > > 1 file changed, 39 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> > > index 3389bab266a9adbda313c8ad795b998641df12f3..da3978da1cab75292ada3f24837443f7f4ab6418 100644
> > > --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> > > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> > > @@ -20,6 +20,7 @@ properties:
> > > - enum:
> > > - fsl,imx8mq-mipi-csi2
> > > - fsl,imx8qxp-mipi-csi2
> > > + - fsl,imx8ulp-mipi-csi2
> > > - items:
> > > - const: fsl,imx8qm-mipi-csi2
> > > - const: fsl,imx8qxp-mipi-csi2
> > > @@ -39,12 +40,16 @@ properties:
> > > clock that the RX DPHY receives.
> > > - description: ui is the pixel clock (phy_ref up to 333Mhz).
> > > See the reference manual for details.
> > > + - description: pclk is clock for csr APB interface.
> > > + minItems: 3
> > >
> > > clock-names:
> > > items:
> > > - const: core
> > > - const: esc
> > > - const: ui
> > > + - const: pclk
> > > + minItems: 3
> > >
> > > power-domains:
> > > maxItems: 1
> > > @@ -130,19 +135,51 @@ allOf:
> > > compatible:
> > > contains:
> > > enum:
> > > - - fsl,imx8qxp-mipi-csi2
> > > + - fsl,imx8ulp-mipi-csi2
> > > + then:
> > > + properties:
> > > + reg:
> > > + minItems: 2
> > > + resets:
> > > + minItems: 2
> > > + maxItems: 2
> > > + clocks:
> > > + minItems: 4
> > > + clock-names:
> > > + minItems: 4
> >
> > Do we need the clock-names constraint ? The DT schemas will enforce that
> > clocks and clock-names always have the same number of elements.
>
> clock-names list already restrict at top section
>
> clock-names:
> items:
> - const: core
> - const: esc
> - const: ui
> - const: pclk
> minItems: 3
>
> Here just restrict need 4 clocks, instead 3 clock for fsl,imx8ulp-mipi-csi2
I understand that. My point was that the dt-schema will always verify
that the number of clocks items is equal to the number of clock-names
items. That's a constraint enforced by the core schemas. As
clocks: minItems is set to 4, the clock-names: minItems constraint is
redundant.
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: fsl,imx8qxp-mipi-csi2
> > > then:
> > > properties:
> > > reg:
> > > minItems: 2
> > > resets:
> > > maxItems: 1
> > > - else:
> > > + clocks:
> > > + maxItems: 3
> > > + clock-names:
> > > + maxItems: 3
> > > +
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + enum:
> > > + - fsl,imx8mq-mipi-csi2
> > > + then:
> > > properties:
> > > reg:
> > > maxItems: 1
> > > resets:
> > > minItems: 3
> > > + clocks:
> > > + maxItems: 3
> > > + clock-names:
> > > + maxItems: 3
> > > required:
> > > - fsl,mipi-phy-gpr
> > >
> >
> > Could you please sort those conditional blocks by alphabetical order of
> > the compatible strings ?
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2025-11-11 21:10 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-23 9:19 [PATCH v7 0/5] Add MIPI CSI-2 support for i.MX8ULP Guoniu Zhou
2025-10-23 9:19 ` [PATCH v7 1/5] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible string Guoniu Zhou
2025-10-27 0:05 ` Laurent Pinchart
2025-11-04 7:13 ` G.N. Zhou (OSS)
2025-11-11 20:47 ` Frank Li
2025-11-11 21:10 ` Laurent Pinchart [this message]
2025-11-11 22:06 ` Frank Li
2025-11-13 2:00 ` Laurent Pinchart
2025-10-23 9:19 ` [PATCH v7 2/5] media: imx8mq-mipi-csi2: Use devm_clk_bulk_get_all() to fetch clocks Guoniu Zhou
2025-10-27 0:11 ` Laurent Pinchart
2025-11-04 7:47 ` G.N. Zhou (OSS)
2025-11-11 17:28 ` Laurent Pinchart
2025-11-21 2:21 ` G.N. Zhou (OSS)
2025-11-21 2:47 ` Laurent Pinchart
2025-10-23 9:19 ` [PATCH v7 3/5] media: imx8mq-mipi-csi2: Explicitly release reset Guoniu Zhou
2025-10-27 0:42 ` Laurent Pinchart
2025-10-23 9:19 ` [PATCH v7 4/5] media: imx8mq-mipi-csi2: Add support for i.MX8ULP Guoniu Zhou
2025-10-27 0:44 ` Laurent Pinchart
2025-10-23 9:19 ` [PATCH v7 5/5] arm64: dts: imx8ulp: Add CSI and ISI Nodes Guoniu Zhou
2025-10-27 1:02 ` Laurent Pinchart
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