[PATCH net-next 0/2] Add support for PHY link active-level configuration in RZN1 MIIC driver

[PATCH net-next 0/2] Add support for PHY link active-level configuration in RZN1 MIIC driver

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series introduces support for configuring the active level of
the PHY-link signals in the Renesas RZN1 MIIC driver. The first patch adds
a new device tree binding property `renesas,miic-phylink-active-low` to
specify whether the PHY-link signals are active low. The second patch
implements the logic in the driver to read this property and configure the
MIIC_PHYLINK register accordingly.

Cheers,
Prabhakar

Lad Prabhakar (2):
  dt-bindings: net: pcs: renesas,rzn1-miic: Add
    renesas,miic-phylink-active-low property
  net: pcs: rzn1-miic: Add support for PHY link active-level
    configuration

 .../bindings/net/pcs/renesas,rzn1-miic.yaml   |   7 ++
 drivers/net/pcs/pcs-rzn1-miic.c               | 108 +++++++++++++++++-
 2 files changed, 113 insertions(+), 2 deletions(-)

-- 
2.43.0

[PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
MIIC binding schema. This property allows configuring the active level
of the PHY-link signals used by the Switch, EtherCAT, and SERCOS III
interfaces.

The signal polarity is controlled by fields in the MIIC_PHYLINK register:
  - SWLNK[3:0]: configures the Switch interface link signal level
      0 - Active High
      1 - Active Low
  - CATLNK[6:4]: configures the EtherCAT interface link signal level
      0 - Active Low
      1 - Active High
  - S3LNK[9:8]: configures the SERCOS III interface link signal level
      0 - Active Low
      1 - Active High

When the `renesas,miic-phylink-active-low` property is present, the
PHY-link signal is configured as active-low. When omitted, the signal
defaults to active-high.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml     | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
index 3adbcf56d2be..825ae8a91e8b 100644
--- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
+++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
@@ -86,6 +86,13 @@ patternProperties:
           and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs.
         $ref: /schemas/types.yaml#/definitions/uint32
 
+      renesas,miic-phylink-active-low:
+        type: boolean
+        description: Indicates that the PHY-link signal provided by the Ethernet switch,
+          EtherCAT, or SERCOS3 interface is active low. When present, this property
+          sets the corresponding signal polarity to active low. When omitted, the signal
+          defaults to active high.
+
     required:
       - reg
       - renesas,miic-input
-- 
2.43.0

[PATCH net-next 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add support to configure the PHY link signal active level per converter
using the DT property "renesas,miic-phylink-active-low".

Introduce the MIIC_PHYLINK register definition and extend the MIIC driver
with a new `phylink` structure to store the mask and value for PHY link
configuration. Implement `miic_configure_phylink()` to determine the bit
position and polarity for each port based on the SoC type, such as RZ/N1
or RZ/T2H/N2H.

The accumulated configuration is stored during Device Tree parsing and
applied later in `miic_probe()` after hardware initialization, since the
MIIC registers can only be modified safely once the hardware setup is
complete.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/net/pcs/pcs-rzn1-miic.c | 108 +++++++++++++++++++++++++++++++-
 1 file changed, 106 insertions(+), 2 deletions(-)

diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c
index 885f17c32643..333467cf91a7 100644
--- a/drivers/net/pcs/pcs-rzn1-miic.c
+++ b/drivers/net/pcs/pcs-rzn1-miic.c
@@ -28,6 +28,8 @@
 
 #define MIIC_MODCTRL			0x8
 
+#define MIIC_PHYLINK			0x14
+
 #define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
 
 #define MIIC_CONVCTRL_CONV_SPEED	GENMASK(1, 0)
@@ -177,6 +179,16 @@ static const char * const rzt2h_reset_ids[] = {
 	"crst",
 };
 
+/**
+ * struct phylink - Phylink configuration
+ * @mask: Mask of phylink bits
+ * @val: Value of phylink bits
+ */
+struct phylink {
+	u32 mask;
+	u32 val;
+};
+
 /**
  * struct miic - MII converter structure
  * @base: base address of the MII converter
@@ -184,6 +196,7 @@ static const char * const rzt2h_reset_ids[] = {
  * @lock: Lock used for read-modify-write access
  * @rsts: Reset controls for the MII converter
  * @of_data: Pointer to OF data
+ * @phylink: Phylink configuration
  */
 struct miic {
 	void __iomem *base;
@@ -191,6 +204,12 @@ struct miic {
 	spinlock_t lock;
 	struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS];
 	const struct miic_of_data *of_data;
+	struct phylink phylink;
+};
+
+enum miic_type {
+	MIIC_TYPE_RZN1,
+	MIIC_TYPE_RZT2H,
 };
 
 /**
@@ -210,6 +229,7 @@ struct miic {
  * @init_unlock_lock_regs: Flag to indicate if registers need to be unlocked
  *  before access.
  * @miic_write: Function pointer to write a value to a MIIC register
+ * @type: Type of MIIC
  */
 struct miic_of_data {
 	struct modctrl_match *match_table;
@@ -226,6 +246,7 @@ struct miic_of_data {
 	u8 reset_count;
 	bool init_unlock_lock_regs;
 	void (*miic_write)(struct miic *miic, int offset, u32 value);
+	enum miic_type type;
 };
 
 /**
@@ -581,10 +602,82 @@ static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg)
 	return -EINVAL;
 }
 
+static void miic_configure_phylink(struct miic *miic, u32 conf,
+				   u32 port, bool active_low)
+{
+	bool polarity_active_high;
+	u32 mask, val;
+	int shift;
+
+	/* determine shift and polarity for this conf */
+	if (miic->of_data->type == MIIC_TYPE_RZN1) {
+		switch (conf) {
+		/* switch ports => bits [3:0] (shift 0), active when low */
+		case MIIC_SWITCH_PORTA:
+		case MIIC_SWITCH_PORTB:
+		case MIIC_SWITCH_PORTC:
+		case MIIC_SWITCH_PORTD:
+			shift = 0;
+			polarity_active_high = false;
+			break;
+
+		/* EtherCAT ports => bits [7:4] (shift 4), active when high */
+		case MIIC_ETHERCAT_PORTA:
+		case MIIC_ETHERCAT_PORTB:
+		case MIIC_ETHERCAT_PORTC:
+			shift = 4;
+			polarity_active_high = true;
+			break;
+
+		/* Sercos ports => bits [11:8] (shift 8), active when high */
+		case MIIC_SERCOS_PORTA:
+		case MIIC_SERCOS_PORTB:
+			shift = 8;
+			polarity_active_high = true;
+			break;
+
+		default:
+			return;
+		}
+	} else {
+		switch (conf) {
+		/* ETHSW ports => bits [3:0] (shift 0), active when low */
+		case ETHSS_ETHSW_PORT0:
+		case ETHSS_ETHSW_PORT1:
+		case ETHSS_ETHSW_PORT2:
+			shift = 0;
+			polarity_active_high = false;
+			break;
+
+		/* ESC ports => bits [7:4] (shift 4), active when high */
+		case ETHSS_ESC_PORT0:
+		case ETHSS_ESC_PORT1:
+		case ETHSS_ESC_PORT2:
+			shift = 4;
+			polarity_active_high = true;
+			break;
+
+		default:
+			return;
+		}
+	}
+
+	mask = BIT(port) << shift;
+
+	if (polarity_active_high)
+		val = (active_low ? 0 : BIT(port)) << shift;
+	else
+		val = (active_low ? BIT(port) : 0) << shift;
+
+	miic->phylink.mask |= mask;
+	miic->phylink.val  = (miic->phylink.val & ~mask) | (val & mask);
+}
+
 static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
 {
 	struct device_node *np = miic->dev->of_node;
 	struct device_node *conv;
+	bool active_low;
 	int port, ret;
 	s8 *dt_val;
 	u32 conf;
@@ -605,8 +698,15 @@ static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
 
 		/* Adjust for 0 based index */
 		port += !miic->of_data->miic_port_start;
-		if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
-			dt_val[port] = conf;
+		if (of_property_read_u32(conv, "renesas,miic-input", &conf))
+			continue;
+
+		dt_val[port] = conf;
+
+		active_low = of_property_read_bool(conv, "renesas,miic-phylink-active-low");
+
+		miic_configure_phylink(miic, conf, port - !miic->of_data->miic_port_start,
+				       active_low);
 	}
 
 	ret = miic_match_dt_conf(miic, dt_val, mode_cfg);
@@ -696,6 +796,8 @@ static int miic_probe(struct platform_device *pdev)
 	if (ret)
 		goto disable_runtime_pm;
 
+	miic_reg_rmw(miic, MIIC_PHYLINK, miic->phylink.mask, miic->phylink.val);
+
 	/* miic_create() relies on that fact that data are attached to the
 	 * platform device to determine if the driver is ready so this needs to
 	 * be the last thing to be done after everything is initialized
@@ -729,6 +831,7 @@ static struct miic_of_data rzn1_miic_of_data = {
 	.sw_mode_mask = GENMASK(4, 0),
 	.init_unlock_lock_regs = true,
 	.miic_write = miic_reg_writel_unlocked,
+	.type = MIIC_TYPE_RZN1,
 };
 
 static struct miic_of_data rzt2h_miic_of_data = {
@@ -745,6 +848,7 @@ static struct miic_of_data rzt2h_miic_of_data = {
 	.reset_ids = rzt2h_reset_ids,
 	.reset_count = ARRAY_SIZE(rzt2h_reset_ids),
 	.miic_write = miic_reg_writel_locked,
+	.type = MIIC_TYPE_RZT2H,
 };
 
 static const struct of_device_id miic_of_mtable[] = {
-- 
2.43.0

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Wolfram Sang]

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Hi Prabhakar,

> Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1

Hmm, we already have "renesas,ether-link-active-low" in
renesas,ether.yaml and renesas,etheravb.yaml. Can't we reuse that?

Happy hacking,

   Wolfram

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Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Andrew Lunn]

On Wed, Nov 12, 2025 at 08:19:36PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
> MIIC binding schema. This property allows configuring the active level
> of the PHY-link signals used by the Switch, EtherCAT, and SERCOS III
> interfaces.
> 
> The signal polarity is controlled by fields in the MIIC_PHYLINK register:
>   - SWLNK[3:0]: configures the Switch interface link signal level
>       0 - Active High
>       1 - Active Low
>   - CATLNK[6:4]: configures the EtherCAT interface link signal level
>       0 - Active Low
>       1 - Active High
>   - S3LNK[9:8]: configures the SERCOS III interface link signal level
>       0 - Active Low
>       1 - Active High
> 
> When the `renesas,miic-phylink-active-low` property is present, the
> PHY-link signal is configured as active-low. When omitted, the signal
> defaults to active-high.

Sorry, but i asked in a previous version, what is phy-link? You still
don't explain what this signal is. phylib/phylink tells you about the
link state, if there is a link partner, what link speed has been
negotiated, duplex, pause etc. What does this signal indicate?

	Andrew

Re: [PATCH net-next 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration

[Andrew Lunn]

On Wed, Nov 12, 2025 at 08:19:37PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support to configure the PHY link signal active level per converter
> using the DT property "renesas,miic-phylink-active-low".
> 
> Introduce the MIIC_PHYLINK register definition and extend the MIIC driver
> with a new `phylink`

You probably want to avoid the name phylink. It is well know that is
all about PHYs , SPFs, PCS, etc.

	Andrew

Re: [PATCH net-next 2/2] net: pcs: rzn1-miic: Add support for PHY link active-level configuration

[Russell King (Oracle)]

On Wed, Nov 12, 2025 at 08:19:37PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add support to configure the PHY link signal active level per converter
> using the DT property "renesas,miic-phylink-active-low".
> 
> Introduce the MIIC_PHYLINK register definition and extend the MIIC driver
> with a new `phylink` structure to store the mask and value for PHY link
> configuration. Implement `miic_configure_phylink()` to determine the bit
> position and polarity for each port based on the SoC type, such as RZ/N1
> or RZ/T2H/N2H.

To echo what Andrew said... really really bad naming.

include/linux/phylink.h:struct phylink;

This structure identifier is already in use, and what's more, this
driver includes that header file.

What exactly is this "PHY link signal" that you talk about in the
commit description? Apart from the LED outputs, I'm not aware of
generally PHYs having a hardware output to indicate link status.

If we're talking about the link status bit in the SGMII config
word, if there's PHYs that have that bit inverted, they deserve to
be broken, because they will be broken with most hardware that
interprets the link state bit (I've never seen the facility to
invert that bit in hardware.)

Basically, please explain what this is for, what this is doing, and
why it is necessary.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Lad, Prabhakar]

Hi Wolfram,

On Wed, Nov 12, 2025 at 8:40 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
>
> Hi Prabhakar,
>
> > Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
>
> Hmm, we already have "renesas,ether-link-active-low" in
> renesas,ether.yaml and renesas,etheravb.yaml. Can't we reuse that?
>
On the RZ/N1x we have the below architecture

                                                      +----> Ethernet Switch
                                                      |           |
                                                      |           v
    MII Converter ----------------------+      GMAC (Synopsys IP)
                                                      |
                                                      +----> EtherCAT
Slave Controller
                                                      |
                                                      +----> SERCOS
Controller

Each of these IPs has its own link status pin as an input to the SoC:

SWITCH_MII_LINK: Switch PHY link status input
S3_MII_LINKP: SERCOS III link status from PHY
CAT_MII_LINK: EtherCAT link status from PHY

The property "renesas,ether-link-active-low" is specific to the AVB
IP. The MII converter enables connections between these IPs, and the
register for controlling the link status signal is part of the MII
converter block, so this property needs to be part of the MII
converter.

If I have misunderstood you, did you mean to rename the property to
"renesas,ether-link-active-low"?

Cheers,
Prabhakar

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Russell King (Oracle)]

On Thu, Nov 13, 2025 at 02:45:18PM +0000, Lad, Prabhakar wrote:
> Hi Wolfram,
> 
> On Wed, Nov 12, 2025 at 8:40 PM Wolfram Sang
> <wsa+renesas@sang-engineering.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
> >
> > Hmm, we already have "renesas,ether-link-active-low" in
> > renesas,ether.yaml and renesas,etheravb.yaml. Can't we reuse that?
> >
> On the RZ/N1x we have the below architecture
> 
>                                                       +----> Ethernet Switch
>                                                       |           |
>                                                       |           v
>     MII Converter ----------------------+      GMAC (Synopsys IP)
>                                                       |
>                                                       +----> EtherCAT
> Slave Controller
>                                                       |
>                                                       +----> SERCOS
> Controller

I'm not sure that diagram has come out correctly. If you're going to
draw diagrams, make sure you do it using a fixed-width font. To me,
it looks like the MII Converter is bolted to GMAC and only has one
connection, and the GMAC has what seems to be maybe five connections.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Lad, Prabhakar]

Hi Andrew,

On Wed, Nov 12, 2025 at 8:58 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Wed, Nov 12, 2025 at 08:19:36PM +0000, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
> > MIIC binding schema. This property allows configuring the active level
> > of the PHY-link signals used by the Switch, EtherCAT, and SERCOS III
> > interfaces.
> >
> > The signal polarity is controlled by fields in the MIIC_PHYLINK register:
> >   - SWLNK[3:0]: configures the Switch interface link signal level
> >       0 - Active High
> >       1 - Active Low
> >   - CATLNK[6:4]: configures the EtherCAT interface link signal level
> >       0 - Active Low
> >       1 - Active High
> >   - S3LNK[9:8]: configures the SERCOS III interface link signal level
> >       0 - Active Low
> >       1 - Active High
> >
> > When the `renesas,miic-phylink-active-low` property is present, the
> > PHY-link signal is configured as active-low. When omitted, the signal
> > defaults to active-high.
>
> Sorry, but i asked in a previous version, what is phy-link? You still
> don't explain what this signal is. phylib/phylink tells you about the
> link state, if there is a link partner, what link speed has been
> negotiated, duplex, pause etc. What does this signal indicate?
>

                                   +----> Ethernet Switch -------->
GMAC (Synopsys IP)
                                    |
                                    |
MII Converter ----------+
                                    |
                                   +----> EtherCAT Slave Controller
                                   |
                                   |
                                   +----> SERCOS Controller

Each of these IPs has its own link status pin as an input to the SoC:

SWITCH_MII_LINK: Switch PHY link status input
S3_MII_LINKP: SERCOS III link status from PHY
CAT_MII_LINK: EtherCAT link status from PHY

The above architecture is for the RZ/N1 SoC. For RZ/T2H SoC we dont
have a SERCOS Controller. So in the case of RZ/T2H EVK the
SWITCH_MII_LINK status pin is connected to the LED1 of VSC8541 PHY.

The PHYLNK register [0] (section 10.2.5 page 763) allows control of
the active level of the link.
0: High active (Default)
1: Active Low

For example the SWITCH requires link-up to be reported to the switch
via the SWITCH_MII_LINK input pin.

[0] https://www.renesas.com/en/document/mah/rzn1d-group-rzn1s-group-rzn1l-group-users-manual-r-engine-and-ethernet-peripherals?r=1054561

Cheers,
Prabhakar

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Lad, Prabhakar]

Hi Russell,

On Thu, Nov 13, 2025 at 3:58 PM Russell King (Oracle)
<linux@armlinux.org.uk> wrote:
>
> On Thu, Nov 13, 2025 at 02:45:18PM +0000, Lad, Prabhakar wrote:
> > Hi Wolfram,
> >
> > On Wed, Nov 12, 2025 at 8:40 PM Wolfram Sang
> > <wsa+renesas@sang-engineering.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > > Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
> > >
> > > Hmm, we already have "renesas,ether-link-active-low" in
> > > renesas,ether.yaml and renesas,etheravb.yaml. Can't we reuse that?
> > >
> > On the RZ/N1x we have the below architecture
> >
> >                                                       +----> Ethernet Switch
> >                                                       |           |
> >                                                       |           v
> >     MII Converter ----------------------+      GMAC (Synopsys IP)
> >                                                       |
> >                                                       +----> EtherCAT
> > Slave Controller
> >                                                       |
> >                                                       +----> SERCOS
> > Controller
>
> I'm not sure that diagram has come out correctly. If you're going to
> draw diagrams, make sure you do it using a fixed-width font. To me,
> it looks like the MII Converter is bolted to GMAC and only has one
> connection, and the GMAC has what seems to be maybe five connections.
>
Sorry when typing the diagram the mail client showed the diagram OK
but when sent everything was messed up. Ive represented now in a
different way.

                                    +-----------------------+
                                    |   MII Converter     |
                                    +-----------+-----------+
                                                    |
           +-----------------------------------------+-------------------------------------------+
            |                                                  |
                                               |
            v                                                 v
                                             v
 +---------------------+
+---------------------------+
+------------------------------+
 | Ethernet Switch  |                   |  EtherCAT Slave      |
            |  SERCOS Controller   |
 +---------+------------+                  |  Controller
|                   +------------------------------+
               |                                  +---------------------------+
               |
               v
  +-------------------------+
 |  GMAC (Synopsys  |
 |       IP)                     |
 +--------------------------+

Cheers,
Prabhakar

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Lad, Prabhakar]

Hi Russell,

On Thu, Nov 13, 2025 at 7:05 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Russell,
>
> On Thu, Nov 13, 2025 at 3:58 PM Russell King (Oracle)
> <linux@armlinux.org.uk> wrote:
> >
> > On Thu, Nov 13, 2025 at 02:45:18PM +0000, Lad, Prabhakar wrote:
> > > Hi Wolfram,
> > >
> > > On Wed, Nov 12, 2025 at 8:40 PM Wolfram Sang
> > > <wsa+renesas@sang-engineering.com> wrote:
> > > >
> > > > Hi Prabhakar,
> > > >
> > > > > Add the boolean DT property `renesas,miic-phylink-active-low` to the RZN1
> > > >
> > > > Hmm, we already have "renesas,ether-link-active-low" in
> > > > renesas,ether.yaml and renesas,etheravb.yaml. Can't we reuse that?
> > > >
> > > On the RZ/N1x we have the below architecture
> > >
> > >                                                       +----> Ethernet Switch
> > >                                                       |           |
> > >                                                       |           v
> > >     MII Converter ----------------------+      GMAC (Synopsys IP)
> > >                                                       |
> > >                                                       +----> EtherCAT
> > > Slave Controller
> > >                                                       |
> > >                                                       +----> SERCOS
> > > Controller
> >
> > I'm not sure that diagram has come out correctly. If you're going to
> > draw diagrams, make sure you do it using a fixed-width font. To me,
> > it looks like the MII Converter is bolted to GMAC and only has one
> > connection, and the GMAC has what seems to be maybe five connections.
> >
> Sorry when typing the diagram the mail client showed the diagram OK
> but when sent everything was messed up. Ive represented now in a
> different way.
>
>                                     +-----------------------+
>                                     |   MII Converter     |
>                                     +-----------+-----------+
>                                                     |
>            +-----------------------------------------+-------------------------------------------+
>             |                                                  |
>                                                |
>             v                                                 v
>                                              v
>  +---------------------+
> +---------------------------+
> +------------------------------+
>  | Ethernet Switch  |                   |  EtherCAT Slave      |
>             |  SERCOS Controller   |
>  +---------+------------+                  |  Controller
> |                   +------------------------------+
>                |                                  +---------------------------+
>                |
>                v
>   +-------------------------+
>  |  GMAC (Synopsys  |
>  |       IP)                     |
>  +--------------------------+
>
Looks like this was messed up too, Ive pasted the diagram here now
https://gist.github.com/prabhakarlad/9549df941eaced5b06efc572ff6c82b5

Sorry for the noise.

Cheers,
Prabhakar

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Andrew Lunn]

> Each of these IPs has its own link status pin as an input to the SoC:

> The above architecture is for the RZ/N1 SoC. For RZ/T2H SoC we dont
> have a SERCOS Controller. So in the case of RZ/T2H EVK the
> SWITCH_MII_LINK status pin is connected to the LED1 of VSC8541 PHY.
> 
> The PHYLNK register [0] (section 10.2.5 page 763) allows control of
> the active level of the link.
> 0: High active (Default)
> 1: Active Low
> 
> For example the SWITCH requires link-up to be reported to the switch
> via the SWITCH_MII_LINK input pin.

Why does the switch require this? The switch also needs to know the
duplex, speed etc. Link on its own is of not enough. So when phylink
mac_link_up is called, you tell it the speed, duplex and also that the
link is up. When the link goes down, mac_link_down callback will be
called and you tell it the link is down.

    Andrew

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Lad, Prabhakar]

Hi Andrew,

On Thu, Nov 13, 2025 at 9:58 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > Each of these IPs has its own link status pin as an input to the SoC:
>
> > The above architecture is for the RZ/N1 SoC. For RZ/T2H SoC we dont
> > have a SERCOS Controller. So in the case of RZ/T2H EVK the
> > SWITCH_MII_LINK status pin is connected to the LED1 of VSC8541 PHY.
> >
> > The PHYLNK register [0] (section 10.2.5 page 763) allows control of
> > the active level of the link.
> > 0: High active (Default)
> > 1: Active Low
> >
> > For example the SWITCH requires link-up to be reported to the switch
> > via the SWITCH_MII_LINK input pin.
>
> Why does the switch require this? The switch also needs to know the
> duplex, speed etc. Link on its own is of not enough. So when phylink
> mac_link_up is called, you tell it the speed, duplex and also that the
> link is up. When the link goes down, mac_link_down callback will be
> called and you tell it the link is down.
>
Sorry for the delayed response. I was awaiting more info from the HW
team on this. Below is the info I got from the HW info.

EtherPHY link-up and link-down status is required as a hardware IP
feature, regardless of whether GMAC or ETHSW is used.
In the case of GMAC, the software retrieves this information from
EtherPHY via MDC/MDIO and then configures GMAC accordingly. In
contrast, ETHSW provides dedicated pins for this purpose.
For ETHSW, this information is also necessary for communication
between two external nodes (e.g., Node A to Node B) that does not
involve the host CPU, as the switching occurs entirely within ETHSW.
This is particularly important for DLR (Device Level Ring: a
redundancy protocol used in EtherNet/IP). DLR relies on detecting
link-down events caused by cable issues as quickly as possible to
enable fast switchover to a redundant path. Handling such path
switching in software introduces performance impacts, which is why
ETHSW includes dedicated pins.
As for Active Level configuration, it is designed to provide
flexibility to accommodate the specifications of external EtherPHY
devices.

Please share your thoughts.

Cheers,
Prabhakar

Re: [PATCH net-next 1/2] dt-bindings: net: pcs: renesas,rzn1-miic: Add renesas,miic-phylink-active-low property

[Andrew Lunn]

On Wed, Nov 26, 2025 at 08:55:53PM +0000, Lad, Prabhakar wrote:
> Hi Andrew,
> 
> On Thu, Nov 13, 2025 at 9:58 PM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > Each of these IPs has its own link status pin as an input to the SoC:
> >
> > > The above architecture is for the RZ/N1 SoC. For RZ/T2H SoC we dont
> > > have a SERCOS Controller. So in the case of RZ/T2H EVK the
> > > SWITCH_MII_LINK status pin is connected to the LED1 of VSC8541 PHY.
> > >
> > > The PHYLNK register [0] (section 10.2.5 page 763) allows control of
> > > the active level of the link.
> > > 0: High active (Default)
> > > 1: Active Low
> > >
> > > For example the SWITCH requires link-up to be reported to the switch
> > > via the SWITCH_MII_LINK input pin.
> >
> > Why does the switch require this? The switch also needs to know the
> > duplex, speed etc. Link on its own is of not enough. So when phylink
> > mac_link_up is called, you tell it the speed, duplex and also that the
> > link is up. When the link goes down, mac_link_down callback will be
> > called and you tell it the link is down.
> >
> Sorry for the delayed response. I was awaiting more info from the HW
> team on this. Below is the info I got from the HW info.
> 
> EtherPHY link-up and link-down status is required as a hardware IP
> feature, regardless of whether GMAC or ETHSW is used.
> In the case of GMAC, the software retrieves this information from
> EtherPHY via MDC/MDIO and then configures GMAC accordingly. In
> contrast, ETHSW provides dedicated pins for this purpose.
> For ETHSW, this information is also necessary for communication
> between two external nodes (e.g., Node A to Node B) that does not
> involve the host CPU, as the switching occurs entirely within ETHSW.
> This is particularly important for DLR (Device Level Ring: a
> redundancy protocol used in EtherNet/IP). DLR relies on detecting
> link-down events caused by cable issues as quickly as possible to
> enable fast switchover to a redundant path. Handling such path
> switching in software introduces performance impacts, which is why
> ETHSW includes dedicated pins.
> As for Active Level configuration, it is designed to provide
> flexibility to accommodate the specifications of external EtherPHY
> devices.
> 
> Please share your thoughts.

Please add this to the commit, to make it clear what these pins are
for.

It actually seems like it is mostly relevant for link down, not up.
If the link goes down, it does not matter if it is 10Half, or 1G Full.
All you want to do is swap to a redundant path as soon as possible.

It would however be interesting it know more about link up. Does the
hardware start using the port as soon as link up is reported by this
pin? So it could be blasting frames out at 1G, until software catches
up and tells the MAC to slow down and do 10Half? So all those frames
are corrupted, causing your nice redundant network to break for a
while?

	Andrew