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Howlett" , Samuel Holland Subject: [PATCH v3 22/22] riscv: dts: eswin: eic7700: Use physical memory ranges for DMA Date: Wed, 12 Nov 2025 17:45:35 -0800 Message-ID: <20251113014656.2605447-23-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20251113014656.2605447-1-samuel.holland@sifive.com> References: <20251113014656.2605447-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit EIC7700 provides a physical memory region which is a noncached alias of normal cacheable DRAM. Declare this alias in the devicetree so Linux can allocate noncached pages for noncoherent DMA, and M-mode firmware can protect the noncached alias with PMPs. Signed-off-by: Samuel Holland --- Changes in v3: - Fix the entry number of the paired region in the DT Changes in v2: - New patch for v2 arch/riscv/Kconfig.socs | 2 ++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a8950206fb75..df3ed1d322fe 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -9,6 +9,8 @@ config ARCH_ANDES config ARCH_ESWIN bool "ESWIN SoCs" + select RISCV_DMA_NONCOHERENT + select RISCV_NONSTANDARD_CACHE_OPS help This enables support for ESWIN SoC platform hardware, including the ESWIN EIC7700 SoC. diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index c3ed93008bca..d566bca4e09e 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -5,9 +5,14 @@ /dts-v1/; +#include + / { #address-cells = <2>; #size-cells = <2>; + riscv,physical-memory-regions = + <0x000 0x80000000 0x00f 0x80000000 (PMA_RWXA | PMA_NONCOHERENT_MEMORY) 0x0>, + <0x0c0 0x00000000 0x010 0x00000000 (PMA_RWX | PMA_NONCACHEABLE_MEMORY | PMR_ALIAS(0)) 0x0>; cpus { #address-cells = <1>; -- 2.47.2