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Thu, 13 Nov 2025 15:30:45 -0800 (PST) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-bc36ed72cd1sm3049486a12.11.2025.11.13.15.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Nov 2025 15:30:45 -0800 (PST) From: Akhil P Oommen Date: Fri, 14 Nov 2025 04:59:05 +0530 Subject: [PATCH v3 08/20] drm/msm/a6xx: Sync latest register definitions Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251114-kaana-gpu-support-v3-8-92300c7ec8ff@oss.qualcomm.com> References: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> In-Reply-To: <20251114-kaana-gpu-support-v3-0-92300c7ec8ff@oss.qualcomm.com> To: Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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Co-developed-by: Rob Clark Signed-off-by: Rob Clark Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 +- drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 8 +- .../gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h | 8 +- .../gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h | 8 +- .../gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h | 8 +- drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1950 +++++++++++++++----- .../gpu/drm/msm/registers/adreno/a6xx_enums.xml | 2 +- .../drm/msm/registers/adreno/a8xx_descriptors.xml | 120 ++ .../gpu/drm/msm/registers/adreno/a8xx_enums.xml | 289 +++ .../gpu/drm/msm/registers/adreno/adreno_common.xml | 1 + 11 files changed, 1896 insertions(+), 513 deletions(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 0c0dfb25f01b..7acf2cc13cd0 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -201,6 +201,7 @@ ADRENO_HEADERS = \ generated/a6xx_perfcntrs.xml.h \ generated/a7xx_enums.xml.h \ generated/a7xx_perfcntrs.xml.h \ + generated/a8xx_enums.xml.h \ generated/a6xx_gmu.xml.h \ generated/adreno_common.xml.h \ generated/adreno_pm4.xml.h \ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 685763c12690..5ede975da95d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -381,7 +381,7 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) rbmemptr_stats(ring, index, alwayson_end)); /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); OUT_RING(ring, submit->seqno); /* @@ -522,7 +522,7 @@ static void a7xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) rbmemptr_stats(ring, index, alwayson_end)); /* Write the fence to the scratch register */ - OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1); + OUT_PKT4(ring, REG_A6XX_CP_SCRATCH(2), 1); OUT_RING(ring, submit->seqno); OUT_PKT7(ring, CP_THREAD_CONTROL, 1); @@ -1291,7 +1291,7 @@ static int hw_init(struct msm_gpu *gpu) } if (adreno_is_a660_family(adreno_gpu)) - gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); + gpu_write(gpu, REG_A7XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020); /* Setting the mem pool size */ if (adreno_is_a610(adreno_gpu)) { @@ -1739,10 +1739,10 @@ static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *da const char *block = "unknown"; u32 scratch[] = { - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)), - gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(4)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(5)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(6)), + gpu_read(gpu, REG_A6XX_CP_SCRATCH(7)), }; if (info) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index 4c5fe627d368..688b8ce02fdc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -71,8 +71,8 @@ static const struct a6xx_cluster { u32 sel_val; } a6xx_clusters[] = { CLUSTER(CLUSTER_GRAS, a6xx_gras_cluster, 0, 0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), - CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rac, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x0), + CLUSTER(CLUSTER_PS, a6xx_ps_cluster_rbp, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0x9), CLUSTER(CLUSTER_PS, a6xx_ps_cluster, 0, 0), CLUSTER(CLUSTER_FE, a6xx_fe_cluster, 0, 0), CLUSTER(CLUSTER_PC_VS, a6xx_pc_vs_cluster, 0, 0), @@ -303,8 +303,8 @@ static const u32 a660_registers[] = { static const struct a6xx_registers a6xx_reglist[] = { REGS(a6xx_registers, 0, 0), REGS(a660_registers, 0, 0), - REGS(a6xx_rb_rac_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 0), - REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, 9), + REGS(a6xx_rb_rac_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 0), + REGS(a6xx_rb_rbp_registers, REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 9), }; static const u32 a6xx_ahb_registers[] = { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h index 087473679893..d513e03fef08 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h @@ -691,14 +691,14 @@ static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = { static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8)); static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x0, }; static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x9, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h index 9bec75e830a3..7897622ea6f7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h @@ -478,14 +478,14 @@ static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = { static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8)); static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x0, }; static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x9, }; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h index 70805a5121be..20125d1aa21d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_9_0_snapshot.h @@ -1105,14 +1105,14 @@ static const u32 gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers[] = { static_assert(IS_ALIGNED(sizeof(gen7_9_0_tpl1_pipe_lpac_cluster_sp_ps_usptp_registers), 8)); static const struct gen7_sel_reg gen7_9_0_rb_rac_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0, }; static const struct gen7_sel_reg gen7_9_0_rb_rbp_sel = { - .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, - .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, .val = 0x9, }; diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index 369b96d7f7c9..484b8f048534 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -7,9 +7,11 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - + + @@ -115,11 +217,16 @@ by a particular renderpass/blit. - + + + + + - + + - + b0..7 identifies where MRB data starts (and RB data ends) b8.15 identifies where VSD data starts (and MRB data ends) @@ -131,7 +238,7 @@ by a particular renderpass/blit. - + low bits identify where CP_SET_DRAW_STATE stateobj processing starts (and IB2 data ends). I'm guessing @@ -147,176 +254,275 @@ by a particular renderpass/blit. - - - - - + + + + + + + + - + + + - + + + + + + + + + + - + + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - + + - + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - number of remaining dwords incl current dword being consumed? - - - - number of remaining dwords incl current dword being consumed? - - - - number of remaining dwords incl current dword being consumed? - - - - number of remaining dwords incl current dword being consumed? - - - - number of dwords that have already been read but haven't been consumed by $addr - - - + + + + + + + + + + + + + + + + + + + + + + number of remaining dwords incl current dword being consumed? - + + + + + + + + + + + + + + + + - - + + + + + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -342,22 +548,59 @@ by a particular renderpass/blit. - - - + + + - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + + + + + + + + + + + + @@ -376,49 +619,96 @@ by a particular renderpass/blit. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + + + - - - - - - - - - - - + + + + + + + + + + + + + + + @@ -610,6 +941,8 @@ by a particular renderpass/blit. + + @@ -638,72 +971,277 @@ by a particular renderpass/blit. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - Set to true when binning, isn't changed afterwards - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - - - - - - + + + + + + + + + + - + - - - + + + + + + + + + + + + + - - + + + + - - - - - - + + + + + + - - + + - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + @@ -712,26 +1250,55 @@ by a particular renderpass/blit. + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -803,10 +1370,14 @@ by a particular renderpass/blit. - - + + + + - + + + @@ -829,6 +1400,7 @@ by a particular renderpass/blit. + @@ -839,6 +1411,18 @@ by a particular renderpass/blit. + + + + + + + + + + + + @@ -853,6 +1437,7 @@ by a particular renderpass/blit. + @@ -860,9 +1445,7 @@ by a particular renderpass/blit. - - - + @@ -887,6 +1470,7 @@ by a particular renderpass/blit. + @@ -921,10 +1505,23 @@ by a particular renderpass/blit. + + + + + + + + + + + + + @@ -951,6 +1548,13 @@ by a particular renderpass/blit. + + + + + + + @@ -958,25 +1562,31 @@ by a particular renderpass/blit. + + + + + + @@ -984,9 +1594,17 @@ by a particular renderpass/blit. + + + + + + + + @@ -994,6 +1612,7 @@ by a particular renderpass/blit. + @@ -1008,6 +1627,7 @@ by a particular renderpass/blit. + @@ -1022,10 +1642,16 @@ by a particular renderpass/blit. + + + + + + @@ -1085,6 +1711,7 @@ by a particular renderpass/blit. + @@ -1123,6 +1750,23 @@ by a particular renderpass/blit. + + + + + Disable LRZ feedback writes + + + Allows draws that don't have GRAS_LRZ_CNTL.LRZ_WRITE but have + GRAS_LRZ_CNTL.ENABLE to contribute to LRZ during RENDERING pass. + In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. + + + + + + + @@ -1130,6 +1774,7 @@ by a particular renderpass/blit. + @@ -1137,6 +1782,7 @@ by a particular renderpass/blit. + @@ -1158,13 +1804,21 @@ by a particular renderpass/blit. + + + + + + + + @@ -1176,14 +1830,26 @@ by a particular renderpass/blit. + + + + + + + + + + + + @@ -1203,6 +1869,7 @@ by a particular renderpass/blit. + @@ -1210,6 +1877,7 @@ by a particular renderpass/blit. + @@ -1217,8 +1885,10 @@ by a particular renderpass/blit. + + @@ -1226,6 +1896,7 @@ by a particular renderpass/blit. + @@ -1263,6 +1934,12 @@ by a particular renderpass/blit. + + + + + + @@ -1275,14 +1952,17 @@ by a particular renderpass/blit. + + + @@ -1290,6 +1970,9 @@ by a particular renderpass/blit. + + + + + + + @@ -1357,11 +2044,11 @@ by a particular renderpass/blit. + LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values. - - - + + @@ -1408,16 +2095,35 @@ by a particular renderpass/blit. + + + + + + + + + + - + - - - - - + + + + + + + + + + + + + + + @@ -1534,8 +2241,32 @@ by a particular renderpass/blit. - - + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -1627,6 +2358,8 @@ by a particular renderpass/blit. + + @@ -1708,6 +2441,14 @@ by a particular renderpass/blit. + + + + + + + + @@ -1720,6 +2461,14 @@ by a particular renderpass/blit. + + + + + + + + @@ -1799,7 +2548,7 @@ by a particular renderpass/blit. - + @@ -1814,7 +2563,17 @@ by a particular renderpass/blit. --> - + + + + + + + + + + + @@ -1849,9 +2608,19 @@ by a particular renderpass/blit. the address is specified through CP_EVENT_WRITE7::WRITE_SAMPLE_COUNT. - - + + + + + + + + + + + + - + - + @@ -1963,7 +2732,7 @@ by a particular renderpass/blit. - + @@ -1972,26 +2741,40 @@ by a particular renderpass/blit. - + + + + + - + + + + + + + - - - - + + + + + + + - - + + + @@ -2014,6 +2797,10 @@ by a particular renderpass/blit. + + + + @@ -2028,6 +2815,9 @@ by a particular renderpass/blit. + + + @@ -2042,6 +2832,7 @@ by a particular renderpass/blit. + @@ -2051,6 +2842,7 @@ by a particular renderpass/blit. + @@ -2091,9 +2883,13 @@ by a particular renderpass/blit. + + + + @@ -2119,6 +2915,15 @@ by a particular renderpass/blit. + + Packed array of a6xx_varying_interp_mode + + + + Packed array of a6xx_varying_ps_repl_mode + + + @@ -2128,6 +2933,11 @@ by a particular renderpass/blit. + + + + + + + @@ -2181,13 +2994,23 @@ by a particular renderpass/blit. + + + + + + + + + + @@ -2211,6 +3034,10 @@ by a particular renderpass/blit. + + + + @@ -2231,6 +3058,7 @@ by a particular renderpass/blit. + - - - - + + + + + + + + + + - - - - + + + + + + + + + + @@ -2285,6 +3142,7 @@ by a particular renderpass/blit. + @@ -2292,10 +3150,13 @@ by a particular renderpass/blit. + + + @@ -2304,6 +3165,7 @@ by a particular renderpass/blit. + @@ -2311,12 +3173,19 @@ by a particular renderpass/blit. + + + + + + + @@ -2326,6 +3195,9 @@ by a particular renderpass/blit. + + + @@ -2333,6 +3205,7 @@ by a particular renderpass/blit. + + + + @@ -2381,7 +3258,13 @@ by a particular renderpass/blit. + + + + + + @@ -2391,24 +3274,37 @@ by a particular renderpass/blit. + + - - - - + + + + + + + + + + + + + + + @@ -2419,6 +3315,10 @@ by a particular renderpass/blit. + + + + @@ -2430,20 +3330,30 @@ by a particular renderpass/blit. + + + + + Written by CP_SET_VISIBILITY_OVERRIDE handler + - + + + - + + + @@ -2532,9 +3442,13 @@ by a particular renderpass/blit. - + + + + + - - - @@ -3036,6 +3951,7 @@ by a particular renderpass/blit. must be at least the actual CONSTLEN. + @@ -3158,6 +4074,18 @@ by a particular renderpass/blit. + + + + + + + + + + + + + + + @@ -3235,7 +4168,8 @@ by a particular renderpass/blit. - + + @@ -3244,10 +4178,14 @@ by a particular renderpass/blit. - + + + + + - + + + + + + + + + + + + + + + + + + + + - - + + + + + @@ -3307,6 +4271,8 @@ by a particular renderpass/blit. + + @@ -3387,10 +4353,11 @@ by a particular renderpass/blit. + - + @@ -3458,10 +4430,8 @@ by a particular renderpass/blit. - - - - + + @@ -3745,6 +4715,7 @@ by a particular renderpass/blit. + @@ -3784,12 +4755,12 @@ by a particular renderpass/blit. - + - + @@ -3918,6 +4889,7 @@ by a particular renderpass/blit. + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml index 4e42f055b85f..81538831dc19 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml @@ -303,7 +303,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml b/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml new file mode 100644 index 000000000000..aee8871d006f --- /dev/null +++ b/drivers/gpu/drm/msm/registers/adreno/a8xx_enums.xml @@ -0,0 +1,289 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml index 06020dc1df44..79d204f1e400 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_common.xml @@ -11,6 +11,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + -- 2.51.0