[PATCH 0/4] Add Altera Agilex5 DWC3 support

[PATCH 0/4] Add Altera Agilex5 DWC3 support

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

This patch series adds USB3.1 support for the Altera Agilex5 SoCFPGA
platform. The integration is based on the Synopsys DesignWare USB3
(DWC3) controller, wrapped by an Altera-specific layer that manages
clocks, resets, and other SoC-level interfaces.

The series introduces a new device tree binding for the Altera DWC3
wrapper, adds the corresponding device tree nodes for Agilex5 and its
SoCDK board, enables support for the new compatible in the dwc3-of-simple
driver, and extends the DWC3 core to handle configurable DMA addressable
bits. This allows Agilex5, which uses a 40-bit DMA address space, to
function correctly with SMMU-enabled systems.

This series also disables the DWC2 USB controller node, as the daughter
card does not support simultaneous operation of both USB controllers.

Adrian Ng Ho Yin (4):
  dt-bindings: usb: dwc3-altera: Add binding for Altera DWC3 wrapper
  arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK
  usb: dwc3: of-simple: Add support for Agilex5 SoCFPGA
  usb: dwc3: add support for configurable DMA addressable bits

 .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 ++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++-
 drivers/usb/dwc3/core.c                       |  9 ++-
 drivers/usb/dwc3/core.h                       |  3 +
 drivers/usb/dwc3/dwc3-of-simple.c             |  1 +
 6 files changed, 122 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml

-- 
2.49.GIT

[PATCH 1/4] dt-bindings: usb: dwc3-altera: Add binding for Altera DWC3 wrapper

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add a device tree binding document for the Altera wrapper around the
Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
SoC-specific integration such as clock and reset control for the USB
subsystem.

A parent–child node structure is used to comply with the generic DWC3
binding, which restricts the core node to a single clock and reset.
The wrapper node provides the additional clocks, resets, and address
translation required for the Agilex5 integration.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml

diff --git a/Documentation/devicetree/bindings/usb/dwc3-altera.yaml b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
new file mode 100644
index 000000000000..c998d587723d
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/dwc3-altera.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Altera DWC3 USB Controller Wrapper
+
+maintainers:
+  - Adrian Ng <adrianhoyin.ng@altera.com>
+
+description: |
+  The Altera SoCFPGA wrapper around the Synopsys DesignWare USB3 (DWC3) core.
+  The wrapper provides SoC-specific integration such as reset and clock control.
+
+properties:
+  compatible:
+    const: altr,agilex5-dwc3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 2
+
+  resets:
+    minItems: 1
+    maxItems: 2
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  ranges: true
+
+required:
+  - compatible
+  - reg
+  - ranges
+  - clocks
+  - resets
+
+patternProperties:
+  "^usb(@[0-9a-f]+)?$":
+    type: object
+    $ref: /schemas/usb/snps,dwc3.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    usb@11000000 {
+        compatible = "altr,agilex5-dwc3";
+        reg = <0x11000000 0x100000>;
+        ranges = <0x0 0x11000000 0x100000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        clocks = <&clkmgr 54>, <&clkmgr 55>;
+        resets = <&rst 36>, <&rst 44>;
+
+        dwc3: usb@0 {
+            compatible = "snps,dwc3";
+            reg = <0x0 0x100000>;
+            interrupts = <0 94 4>;
+            iommus = <&smmu 7>;
+            phys = <&usbphy0>, <&usbphy0>;
+            phy-names = "usb2-phy", "usb3-phy";
+            dr_mode = "host";
+            maximum-speed = "super-speed";
+            snps,dis_u2_susphy_quirk;
+            snps,dis_u3_susphy_quirk;
+            status = "okay";
+        };
+    };
+...
-- 
2.49.GIT

[PATCH 2/4] arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add device tree nodes for the USB3.1 controller on the Agilex5 SoC
and enable it on the SoCDK board. The USB3.1 block consists of a
SoC-specific wrapper around the Synopsys DWC3 core that handles clock,
reset, and address translation configuration.

The DWC3 core is described as a child of the wrapper to reflect the
hardware hierarchy and comply with the DWC3 binding requirements.

This commit also disables the DWC2 USB controller node, as the daughter
card does not support simultaneous operation of both USB controllers.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 +++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++++++-
 2 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index a22cf6a211e2..6253bda0e819 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -444,6 +444,30 @@ usb0: usb@10b00000 {
 			status = "disabled";
 		};
 
+		usb31: usb1@11000000 {
+			compatible = "altr,agilex5-dwc3";
+			reg = <0x11000000 0x100000>;
+			ranges = <0x0 0x11000000 0x100000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			clocks = <&clkmgr AGILEX5_USB31_SUSPEND_CLK>,
+				<&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>;
+			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
+
+			dwc3: usb@0 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0x10000>;
+				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+				iommus = <&smmu 7>;
+				dr_mode = "host";
+				maximum-speed = "super-speed";
+				phys = <&usbphy0>, <&usbphy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,dis_u2_susphy_quirk;
+				snps,dis_u3_susphy_quirk;
+			};
+		};
+
 		watchdog0: watchdog@10d00200 {
 			compatible = "snps,dw-wdt";
 			reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..af301191b262 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -103,10 +103,17 @@ &uart0 {
 };
 
 &usb0 {
-	status = "okay";
 	disable-over-current;
 };
 
+&usb31 {
+	status = "okay";
+};
+
+&dwc3 {
+	dr_mode = "host";
+};
+
 &watchdog0 {
 	status = "okay";
 };
-- 
2.49.GIT

[PATCH 3/4] usb: dwc3: of-simple: Add support for Agilex5 SoCFPGA

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add the compatible string "altr,agilex5-dwc3" to the
dwc3-of-simple driver match table to enable support for the DWC3
controller on Agilex5 SoCFPGA platform.

The DWC3 controller on Agilex5 is instantiated as a child node
under the DWC3 simple glue layer. The simple glue layer is sufficient
for Agilex5 as no platform-specific initialization or custom control
logic is required.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 drivers/usb/dwc3/dwc3-of-simple.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index a4954a21be93..52f9ee236a1e 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -174,6 +174,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "hisilicon,hi3670-dwc3" },
 	{ .compatible = "hisilicon,hi3798mv200-dwc3" },
 	{ .compatible = "intel,keembay-dwc3" },
+	{ .compatible = "altr,agilex5-dwc3" },
 	{ /* Sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
-- 
2.49.GIT

[PATCH 4/4] usb: dwc3: add support for configurable DMA addressable bits

[adrianhoyin.ng]

From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>

Add support for configuring the DMA addressable bit width in the
Synopsys DesignWare USB3 (DWC3) core driver.

Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect
DMA mask (such as the default 64-bit) can lead to address truncation or
translation faults when the SMMU is enabled.

This commit introduces a new field, dma_addressable_bits, in the dwc3
structure to track the platform’s supported DMA width. The default value
is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the
value is overridden to 40 bits. This field is then used when setting the
DMA mask to ensure compatibility with the system’s actual address bus
capabilities.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
---
 drivers/usb/dwc3/core.c | 9 ++++++++-
 drivers/usb/dwc3/core.h | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index ae140c356295..20e655364135 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 	dwc->xhci_resources[0].flags = res->flags;
 	dwc->xhci_resources[0].name = res->name;
 
+	/* Initialize dma addressable bit to 64 bits as default */
+	dwc->dma_addressable_bits = 64;
+
 	/*
 	 * Request memory region but exclude xHCI regs,
 	 * since it will be requested by the xhci-plat driver.
@@ -2194,6 +2197,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 			dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
 		}
 
+		if (of_device_is_compatible(parent, "altr,agilex5-dwc3"))
+			dwc->dma_addressable_bits = 40;
+
 		of_node_put(parent);
 	}
 
@@ -2243,7 +2249,8 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
 
 	if (!dwc->sysdev_is_parent &&
 	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
-		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
+		ret = dma_set_mask_and_coherent(dwc->sysdev,
+						DMA_BIT_MASK(dwc->dma_addressable_bits));
 		if (ret)
 			goto err_disable_clks;
 	}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a5fc92c4ffa3..ddc42c88da93 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1180,6 +1180,8 @@ struct dwc3_glue_ops {
  * @wakeup_pending_funcs: Indicates whether any interface has requested for
  *			 function wakeup in bitmap format where bit position
  *			 represents interface_id.
+ * @dma_addressable_bits: set if we need to configure a different
+ *			dma-bit-mask other than 64 bits.
  */
 struct dwc3 {
 	struct work_struct	drd_work;
@@ -1414,6 +1416,7 @@ struct dwc3 {
 	struct dentry		*debug_root;
 	u32			gsbuscfg0_reqinfo;
 	u32			wakeup_pending_funcs;
+	u32			dma_addressable_bits;
 };
 
 #define INCRX_BURST_MODE 0
-- 
2.49.GIT

Re: [PATCH 1/4] dt-bindings: usb: dwc3-altera: Add binding for Altera DWC3 wrapper

[Krzysztof Kozlowski]

On Tue, Nov 11, 2025 at 02:18:45PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add a device tree binding document for the Altera wrapper around the
> Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
> SoC-specific integration such as clock and reset control for the USB
> subsystem.
> 
> A parent–child node structure is used to comply with the generic DWC3

No, that's long time legacy. Use single node.

> binding, which restricts the core node to a single clock and reset.
> The wrapper node provides the additional clocks, resets, and address
> translation required for the Agilex5 integration.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  .../devicetree/bindings/usb/dwc3-altera.yaml  | 78 +++++++++++++++++++
>  1 file changed, 78 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/usb/dwc3-altera.yaml
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3-altera.yaml b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml
> new file mode 100644
> index 000000000000..c998d587723d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/dwc3-altera.yaml

Filename matching compatible.

> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/dwc3-altera.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Altera DWC3 USB Controller Wrapper
> +
> +maintainers:
> +  - Adrian Ng <adrianhoyin.ng@altera.com>
> +
> +description: |

Do not need '|' unless you need to preserve formatting.

> +  The Altera SoCFPGA wrapper around the Synopsys DesignWare USB3 (DWC3) core.
> +  The wrapper provides SoC-specific integration such as reset and clock control.
> +
> +properties:
> +  compatible:
> +    const: altr,agilex5-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +    maxItems: 2

No, this cannot be flexible. Please do not write bindings completely
different than everything else.

List the items, fix size/length of the array.

> +
> +  resets:
> +    minItems: 1
> +    maxItems: 2

Same problem,

> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 1

No. Use single node.

> +
> +  ranges: true

Drop

> +
> +required:
> +  - compatible
> +  - reg
> +  - ranges
> +  - clocks
> +  - resets
> +
> +patternProperties:
> +  "^usb(@[0-9a-f]+)?$":
> +    type: object
> +    $ref: /schemas/usb/snps,dwc3.yaml#

Drop

> +
> +unevaluatedProperties: false

That's wrong in this context. Please read example-schema or writing
schema.

> +
> +examples:
> +  - |
> +    usb@11000000 {
> +        compatible = "altr,agilex5-dwc3";
> +        reg = <0x11000000 0x100000>;
> +        ranges = <0x0 0x11000000 0x100000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        clocks = <&clkmgr 54>, <&clkmgr 55>;
> +        resets = <&rst 36>, <&rst 44>;
> +
> +        dwc3: usb@0 {
> +            compatible = "snps,dwc3";
> +            reg = <0x0 0x100000>;
> +            interrupts = <0 94 4>;

We don't use such code... Look at any decent DTS.

> +            iommus = <&smmu 7>;
> +            phys = <&usbphy0>, <&usbphy0>;
> +            phy-names = "usb2-phy", "usb3-phy";
> +            dr_mode = "host";
> +            maximum-speed = "super-speed";
> +            snps,dis_u2_susphy_quirk;
> +            snps,dis_u3_susphy_quirk;
> +            status = "okay";

Drop

This is a pretty poor binding. You just repeat basic mistakes, fixed in
other NEW bindings. Last time few-line patch, with obvious issues, had
two reviewed-by from Altera. This one - bigger patch - no one cared to
review?

Best regards,
Krzysztof

Re: [PATCH 1/4] dt-bindings: usb: dwc3-altera: Add binding for Altera DWC3 wrapper

[Krzysztof Kozlowski]

On Tue, Nov 11, 2025 at 02:18:45PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add a device tree binding document for the Altera wrapper around the
> Synopsys DesignWare USB3 (DWC3) controller. The wrapper manages
> SoC-specific integration such as clock and reset control for the USB
> subsystem.
> 
> A parent–child node structure is used to comply with the generic DWC3
> binding, which restricts the core node to a single clock and reset.
> The wrapper node provides the additional clocks, resets, and address
> translation required for the Agilex5 integration.

Also, standard message:

A nit, subject: drop second/last, redundant "binding for". The
"dt-bindings" prefix is already stating that these are bindings.
See also:
https://elixir.bootlin.com/linux/v6.17-rc3/source/Documentation/devicetree/bindings/submitting-patches.rst#L18

Best regards,
Krzysztof

Re: [PATCH 2/4] arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK

[Krzysztof Kozlowski]

On Tue, Nov 11, 2025 at 02:18:46PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add device tree nodes for the USB3.1 controller on the Agilex5 SoC
> and enable it on the SoCDK board. The USB3.1 block consists of a
> SoC-specific wrapper around the Synopsys DWC3 core that handles clock,
> reset, and address translation configuration.
> 
> The DWC3 core is described as a child of the wrapper to reflect the
> hardware hierarchy and comply with the DWC3 binding requirements.
> 
> This commit also disables the DWC2 USB controller node, as the daughter
> card does not support simultaneous operation of both USB controllers.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 24 +++++++++++++++++++
>  .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  9 ++++++-

DTS cannot be mixed here. You are targetting USB, so you cannot mix up
other subsystems.

Best regards,
Krzysztof

Re: [PATCH 4/4] usb: dwc3: add support for configurable DMA addressable bits

[Krzysztof Kozlowski]

On Tue, Nov 11, 2025 at 02:18:48PM +0800, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add support for configuring the DMA addressable bit width in the
> Synopsys DesignWare USB3 (DWC3) core driver.
> 
> Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect
> DMA mask (such as the default 64-bit) can lead to address truncation or
> translation faults when the SMMU is enabled.
> 
> This commit introduces a new field, dma_addressable_bits, in the dwc3
> structure to track the platform’s supported DMA width. The default value
> is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the
> value is overridden to 40 bits. This field is then used when setting the
> DMA mask to ensure compatibility with the system’s actual address bus
> capabilities.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  drivers/usb/dwc3/core.c | 9 ++++++++-
>  drivers/usb/dwc3/core.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ae140c356295..20e655364135 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  	dwc->xhci_resources[0].flags = res->flags;
>  	dwc->xhci_resources[0].name = res->name;
>  
> +	/* Initialize dma addressable bit to 64 bits as default */
> +	dwc->dma_addressable_bits = 64;
> +
>  	/*
>  	 * Request memory region but exclude xHCI regs,
>  	 * since it will be requested by the xhci-plat driver.
> @@ -2194,6 +2197,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  			dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
>  		}
>  
> +		if (of_device_is_compatible(parent, "altr,agilex5-dwc3"))

No, this does not scale. Don't sprinkle compatible all over driver code.
You have driver match data for that.

Best regards,
Krzysztof

Re: [PATCH 3/4] usb: dwc3: of-simple: Add support for Agilex5 SoCFPGA

[Thinh Nguyen]

On Tue, Nov 11, 2025, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add the compatible string "altr,agilex5-dwc3" to the
> dwc3-of-simple driver match table to enable support for the DWC3
> controller on Agilex5 SoCFPGA platform.
> 
> The DWC3 controller on Agilex5 is instantiated as a child node
> under the DWC3 simple glue layer. The simple glue layer is sufficient
> for Agilex5 as no platform-specific initialization or custom control
> logic is required.
> 

As noted by Krzysztof Kozlowski, use the new flatten model and
dwc3-generic-plat driver.

BR,
Thinh

> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  drivers/usb/dwc3/dwc3-of-simple.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
> index a4954a21be93..52f9ee236a1e 100644
> --- a/drivers/usb/dwc3/dwc3-of-simple.c
> +++ b/drivers/usb/dwc3/dwc3-of-simple.c
> @@ -174,6 +174,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
>  	{ .compatible = "hisilicon,hi3670-dwc3" },
>  	{ .compatible = "hisilicon,hi3798mv200-dwc3" },
>  	{ .compatible = "intel,keembay-dwc3" },
> +	{ .compatible = "altr,agilex5-dwc3" },
>  	{ /* Sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
> -- 
> 2.49.GIT
> 

Re: [PATCH 4/4] usb: dwc3: add support for configurable DMA addressable bits

[Thinh Nguyen]

On Tue, Nov 11, 2025, adrianhoyin.ng@altera.com wrote:
> From: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> 
> Add support for configuring the DMA addressable bit width in the
> Synopsys DesignWare USB3 (DWC3) core driver.
> 
> Altera Agilex5 supports only 40-bit DMA addressing. Setting an incorrect
> DMA mask (such as the default 64-bit) can lead to address truncation or
> translation faults when the SMMU is enabled.
> 
> This commit introduces a new field, dma_addressable_bits, in the dwc3
> structure to track the platform’s supported DMA width. The default value
> is set to 64 bits, but for Agilex5 platforms (altr,agilex5-dwc3), the
> value is overridden to 40 bits. This field is then used when setting the
> DMA mask to ensure compatibility with the system’s actual address bus
> capabilities.
> 
> Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
> ---
>  drivers/usb/dwc3/core.c | 9 ++++++++-
>  drivers/usb/dwc3/core.h | 3 +++
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index ae140c356295..20e655364135 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -2179,6 +2179,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  	dwc->xhci_resources[0].flags = res->flags;
>  	dwc->xhci_resources[0].name = res->name;
>  
> +	/* Initialize dma addressable bit to 64 bits as default */
> +	dwc->dma_addressable_bits = 64;

This should be a dwc3 property that can be passed by the glue.

> +
>  	/*
>  	 * Request memory region but exclude xHCI regs,
>  	 * since it will be requested by the xhci-plat driver.
> @@ -2194,6 +2197,9 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  			dwc_res.start += DWC3_RTK_RTD_GLOBALS_REGS_START;
>  		}
>  
> +		if (of_device_is_compatible(parent, "altr,agilex5-dwc3"))

Avoid of_device_is_compatible() in the core. Do this in the glue.

> +			dwc->dma_addressable_bits = 40;
> +
>  		of_node_put(parent);
>  	}
>  
> @@ -2243,7 +2249,8 @@ int dwc3_core_probe(const struct dwc3_probe_data *data)
>  
>  	if (!dwc->sysdev_is_parent &&
>  	    DWC3_GHWPARAMS0_AWIDTH(dwc->hwparams.hwparams0) == 64) {
> -		ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
> +		ret = dma_set_mask_and_coherent(dwc->sysdev,
> +						DMA_BIT_MASK(dwc->dma_addressable_bits));
>  		if (ret)
>  			goto err_disable_clks;
>  	}
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index a5fc92c4ffa3..ddc42c88da93 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -1180,6 +1180,8 @@ struct dwc3_glue_ops {
>   * @wakeup_pending_funcs: Indicates whether any interface has requested for
>   *			 function wakeup in bitmap format where bit position
>   *			 represents interface_id.
> + * @dma_addressable_bits: set if we need to configure a different
> + *			dma-bit-mask other than 64 bits.
>   */
>  struct dwc3 {
>  	struct work_struct	drd_work;
> @@ -1414,6 +1416,7 @@ struct dwc3 {
>  	struct dentry		*debug_root;
>  	u32			gsbuscfg0_reqinfo;
>  	u32			wakeup_pending_funcs;
> +	u32			dma_addressable_bits;
>  };
>  
>  #define INCRX_BURST_MODE 0
> -- 
> 2.49.GIT
> 

BR,
Thinh

Re: [PATCH 2/4] arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK

[kernel test robot]

Hi,

kernel test robot noticed the following build errors:

[auto build test ERROR on usb/usb-testing]
[also build test ERROR on usb/usb-next usb/usb-linus robh/for-next westeri-thunderbolt/next linus/master v6.18-rc5 next-20251113]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/adrianhoyin-ng-altera-com/dt-bindings-usb-dwc3-altera-Add-binding-for-Altera-DWC3-wrapper/20251111-142609
base:   https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb-testing
patch link:    https://lore.kernel.org/r/7ec6e1787a677f6614f7f991a31a9ac58b539780.1762839776.git.adrianhoyin.ng%40altera.com
patch subject: [PATCH 2/4] arm64: dts: intel: agilex5: Add USB3.1 support for Agilex5 SoCDK
config: arm64-randconfig-002-20251113 (https://download.01.org/0day-ci/archive/20251114/202511141429.Ae8oNWSX-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 0bba1e76581bad04e7d7f09f5115ae5e2989e0d9)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251114/202511141429.Ae8oNWSX-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511141429.Ae8oNWSX-lkp@intel.com/

All errors (new ones prefixed by >>):

   also defined at arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts:111.7-113.3
>> ERROR: Input tree has errors, aborting (use -f to force output)
--
>> ERROR: Input tree has errors, aborting (use -f to force output)

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki