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[178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b734fda933fsm606189866b.56.2025.11.15.06.14.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 15 Nov 2025 06:14:16 -0800 (PST) From: Jernej Skrabec To: wens@csie.org, samuel@sholland.org Cc: mripard@kernel.org, maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Jernej Skrabec Subject: [PATCH 3/7] clk: sunxi-ng: de2: Export register regmap for DE33 Date: Sat, 15 Nov 2025 15:13:43 +0100 Message-ID: <20251115141347.13087-4-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.2 In-Reply-To: <20251115141347.13087-1-jernej.skrabec@gmail.com> References: <20251115141347.13087-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit DE33 clock pre-set plane mapping, which is not something that we want from clock driver. Export registers instead, so DRM driver can set them properly. Signed-off-by: Jernej Skrabec --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 53 ++++++++++++++++++++++++++-- 1 file changed, 50 insertions(+), 3 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index a6cd0f988859..2841ec922025 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include #include +#include #include #include "ccu_common.h" @@ -250,6 +252,41 @@ static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = { .num_resets = ARRAY_SIZE(sun50i_h5_de2_resets), }; +/* + * Add a regmap for the DE33 plane driver to access plane + * mapping registers. + * Only these registers are allowed to be written, to prevent + * overriding clock and reset configuration. + */ + +#define SUN50I_DE33_CHN2CORE_REG 0x24 +#define SUN50I_DE33_PORT02CHN_REG 0x28 +#define SUN50I_DE33_PORT12CHN_REG 0x2c + +static bool sun8i_de2_ccu_regmap_accessible_reg(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case SUN50I_DE33_CHN2CORE_REG: + case SUN50I_DE33_PORT02CHN_REG: + case SUN50I_DE33_PORT12CHN_REG: + return true; + default: + return false; + } +} + +static const struct regmap_config sun8i_de2_ccu_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = 0xe0, + + /* other devices have no business accessing other registers */ + .readable_reg = sun8i_de2_ccu_regmap_accessible_reg, + .writeable_reg = sun8i_de2_ccu_regmap_accessible_reg, +}; + static int sunxi_de2_clk_probe(struct platform_device *pdev) { struct clk *bus_clk, *mod_clk; @@ -303,13 +340,23 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev) } /* - * The DE33 requires these additional (unknown) registers set + * The DE33 requires these additional plane mapping registers set * during initialisation. */ if (of_device_is_compatible(pdev->dev.of_node, "allwinner,sun50i-h616-de33-clk")) { - writel(0, reg + 0x24); - writel(0x0000a980, reg + 0x28); + struct regmap *regmap; + + regmap = devm_regmap_init_mmio(&pdev->dev, reg, + &sun8i_de2_ccu_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + goto err_assert_reset; + } + + ret = of_syscon_register_regmap(pdev->dev.of_node, regmap); + if (ret) + goto err_assert_reset; } ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc); -- 2.51.2