* [PATCH] arm64: qcom: dts: sm8750: add coresight nodes
@ 2025-11-17 9:31 Jie Gan
2025-11-18 10:03 ` Konrad Dybcio
0 siblings, 1 reply; 4+ messages in thread
From: Jie Gan @ 2025-11-17 9:31 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel, Jie Gan
Add CoreSight DT nodes for AOSS, QDSS, Turing, and Modem blocks to enable
the STM and TPDM sources to route trace data to the ETF for debugging.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sm8750.dtsi | 981 +++++++++++++++++++++++++++++++++++
1 file changed, 981 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index 3f0b57f428bb..56c2605f3e0d 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -3313,6 +3313,948 @@ tcsrcc: clock-controller@f204008 {
#reset-cells = <1>;
};
+ stm@10002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x0 0x10002000 0x0 0x1000>,
+ <0x0 0x37280000 0x0 0x180000>;
+ reg-names = "stm-base",
+ "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel_in0_in7>;
+ };
+ };
+ };
+ };
+
+ tpda@10004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10004000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ tpda_qdss_in1: endpoint {
+ remote-endpoint = <&tpdm_spdm_out>;
+ };
+ };
+
+ };
+
+ out-ports {
+ port {
+ tpda_qdss_out: endpoint {
+ remote-endpoint = <&funnel_in0_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@1000f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1000f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_spdm_out: endpoint {
+ remote-endpoint = <&tpda_qdss_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@10041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10041000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ funnel_in0_in0: endpoint {
+ remote-endpoint =
+ <&tn_ag_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ funnel_in0_in6: endpoint {
+ remote-endpoint = <&tpda_qdss_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_in0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_in0_out: endpoint {
+ remote-endpoint = <&funnel_aoss_in7>;
+ };
+ };
+ };
+ };
+
+ tpdm@10800000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10800000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_modem0_out: endpoint {
+ remote-endpoint = <&tpda_modem_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@10803000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10803000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_modem_in0: endpoint {
+ remote-endpoint = <&tpdm_modem0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_modem_in1: endpoint {
+ remote-endpoint = <&tpdm_modem1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_modem_out: endpoint {
+ remote-endpoint = <&funnel_modem_dl_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10804000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10804000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_modem_dl_in0: endpoint {
+ remote-endpoint = <&tpda_modem_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_modem_dl_out: endpoint {
+ remote-endpoint = <&tn_ag_in13>;
+ };
+ };
+ };
+ };
+
+ cti@1080b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x1080b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@1082c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1082c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_gcc_out: endpoint {
+ remote-endpoint = <&tn_ag_in17>;
+ };
+ };
+ };
+ };
+
+ tpdm@10841000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10841000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_prng_out: endpoint {
+ remote-endpoint = <&tn_ag_in18>;
+ };
+ };
+ };
+ };
+
+ tpdm@1084e000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1084e000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_mm_bcv_out: endpoint {
+ remote-endpoint = <&tpda_mm_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@1084f000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x1084f000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <32>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_mm_lmh_out: endpoint {
+ remote-endpoint = <&tpda_mm_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@10850000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10850000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_mm_dpm_out: endpoint {
+ remote-endpoint = <&tpda_mm_in2>;
+ };
+ };
+ };
+ };
+
+ tpda@10851000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10851000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_mm_in0: endpoint {
+ remote-endpoint = <&tpdm_mm_bcv_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_mm_in1: endpoint {
+ remote-endpoint = <&tpdm_mm_lmh_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_mm_in2: endpoint {
+ remote-endpoint = <&tpdm_mm_dpm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_mm_out: endpoint {
+ remote-endpoint = <&tn_ag_in4>;
+ };
+ };
+ };
+ };
+
+ tpdm@10980000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10980000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_turing_out: endpoint {
+ remote-endpoint = <&tpda_turing_in0>;
+ };
+ };
+ };
+ };
+
+ tpda@10986000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10986000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_turing_in0: endpoint {
+ remote-endpoint = <&tpdm_turing_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_turing_in1: endpoint {
+ remote-endpoint = <&tpdm_turing_llm_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_turing_in2: endpoint {
+ remote-endpoint = <&tpdm_turing_llm2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_turing_out: endpoint {
+ remote-endpoint = <&funnel_turing_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@10987000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10987000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ funnel_turing_in0: endpoint {
+ remote-endpoint = <&tpda_turing_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel_turing_out: endpoint {
+ remote-endpoint = <&tn_ag_in16>;
+ };
+ };
+ };
+ };
+
+ cti@1098b000 {
+ compatible = "arm,coresight-cti", "arm,primecell";
+ reg = <0x0 0x1098b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm@109a3000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a3000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_pmu_out: endpoint {
+ remote-endpoint = <&tn_ag_in29>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a4000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a4000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_ipcc_cmb_out: endpoint {
+ remote-endpoint = <&tn_ag_in28>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a5000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a5000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_dl_mm_out: endpoint {
+ remote-endpoint = <&tn_ag_in25>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a6000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a6000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_north_dsb_out: endpoint {
+ remote-endpoint = <&tn_ag_in26>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a7000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a7000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_south_dsb_out: endpoint {
+ remote-endpoint = <&tn_ag_in27>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a8000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a8000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb0_out: endpoint {
+ remote-endpoint = <&tn_ag_in30>;
+ };
+ };
+ };
+ };
+
+ tpdm@109a9000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109a9000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb1_out: endpoint {
+ remote-endpoint = <&tn_ag_in31>;
+ };
+ };
+ };
+ };
+
+ tpdm@109aa000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109aa000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_rdpm_cmb2_out: endpoint {
+ remote-endpoint = <&tn_ag_in32>;
+ };
+ };
+ };
+ };
+
+ tn@109ab000 {
+ compatible = "qcom,coresight-tnoc", "arm,primecell";
+ reg = <0x0 0x109ab000 0x0 0x4200>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+
+ tn_ag_in4: endpoint {
+ remote-endpoint = <&tpda_mm_out>;
+ };
+ };
+
+ port@d {
+ reg = <0xd>;
+
+ tn_ag_in13: endpoint {
+ remote-endpoint = <&funnel_modem_dl_out>;
+ };
+ };
+
+ port@10 {
+ reg = <0x10>;
+
+ tn_ag_in16: endpoint {
+ remote-endpoint = <&funnel_turing_out>;
+ };
+ };
+
+ port@11 {
+ reg = <0x11>;
+
+ tn_ag_in17: endpoint {
+ remote-endpoint = <&tpdm_gcc_out>;
+ };
+ };
+
+ port@12 {
+ reg = <0x12>;
+
+ tn_ag_in18: endpoint {
+ remote-endpoint = <&tpdm_prng_out>;
+ };
+ };
+
+ port@13 {
+ reg = <0x13>;
+
+ tn_ag_in19: endpoint {
+ remote-endpoint = <&tpdm_qm_out>;
+ };
+ };
+
+ port@19 {
+ reg = <0x19>;
+
+ tn_ag_in25: endpoint {
+ remote-endpoint = <&tpdm_dl_mm_out>;
+ };
+ };
+
+ port@1a {
+ reg = <0x1a>;
+
+ tn_ag_in26: endpoint {
+ remote-endpoint = <&tpdm_north_dsb_out>;
+ };
+ };
+
+ port@1b {
+ reg = <0x1b>;
+
+ tn_ag_in27: endpoint {
+ remote-endpoint = <&tpdm_south_dsb_out>;
+ };
+ };
+
+ port@1c {
+ reg = <0x1c>;
+
+ tn_ag_in28: endpoint {
+ remote-endpoint = <&tpdm_ipcc_cmb_out>;
+ };
+ };
+
+ port@1d {
+ reg = <0x1d>;
+
+ tn_ag_in29: endpoint {
+ remote-endpoint = <&tpdm_pmu_out>;
+ };
+ };
+
+ port@1e {
+ reg = <0x1e>;
+
+ tn_ag_in30: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb0_out>;
+ };
+ };
+
+ port@1f {
+ reg = <0x1f>;
+
+ tn_ag_in31: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb1_out>;
+ };
+ };
+
+ port@20 {
+ reg = <0x20>;
+
+ tn_ag_in32: endpoint {
+ remote-endpoint = <&tpdm_rdpm_cmb2_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tn_ag_out: endpoint {
+ remote-endpoint = <&funnel_in0_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@109d0000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x109d0000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_qm_out: endpoint {
+ remote-endpoint = <&tn_ag_in19>;
+ };
+ };
+ };
+ };
+
+ funnel@10b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0x0 0x10b04000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+
+ funnel_aoss_in6: endpoint {
+ remote-endpoint = <&tpda_aoss_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+
+ funnel_aoss_in7: endpoint {
+ remote-endpoint = <&funnel_in0_out>;
+ };
+ };
+
+ };
+
+ out-ports {
+ port {
+ funnel_aoss_out: endpoint {
+ remote-endpoint = <&tmc_etf_in>;
+ };
+ };
+ };
+ };
+
+ tmc@10b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x0 0x10b05000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ port {
+ tmc_etf_in: endpoint {
+ remote-endpoint = <&funnel_aoss_out>;
+ };
+ };
+ };
+ };
+
+ tpda@10b08000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x0 0x10b08000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tpda_aoss_in0: endpoint {
+ remote-endpoint = <&tpdm_swao_prio0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tpda_aoss_in1: endpoint {
+ remote-endpoint = <&tpdm_swao_prio1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ tpda_aoss_in2: endpoint {
+ remote-endpoint = <&tpdm_swao_prio2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ tpda_aoss_in3: endpoint {
+ remote-endpoint = <&tpdm_swao_prio3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ tpda_aoss_in4: endpoint {
+ remote-endpoint =<&tpdm_swao_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_aoss_out: endpoint {
+ remote-endpoint = <&funnel_aoss_in6>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b09000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b09000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio0_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in0>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0a000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0a000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio1_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0b000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0b000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio2_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0c000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,cmb-element-bits = <64>;
+ qcom,cmb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_prio3_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in3>;
+ };
+ };
+ };
+ };
+
+ tpdm@10b0d000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x0 0x10b0d000 0x0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ qcom,dsb-element-bits = <32>;
+ qcom,dsb-msrs-num = <32>;
+
+ out-ports {
+ port {
+ tpdm_swao_out: endpoint {
+ remote-endpoint = <&tpda_aoss_in4>;
+ };
+ };
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
@@ -4239,4 +5181,43 @@ timer {
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+
+ tpdm_llm {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_turing_llm_out: endpoint {
+ remote-endpoint = <&tpda_turing_in1>;
+ };
+ };
+ };
+ };
+
+ tpdm_llm2 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,cmb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_turing_llm2_out: endpoint {
+ remote-endpoint = <&tpda_turing_in2>;
+ };
+ };
+ };
+ };
+
+ tpdm_modem1 {
+ compatible = "qcom,coresight-static-tpdm";
+ qcom,dsb-element-bits = <32>;
+
+ out-ports {
+ port {
+ tpdm_modem1_out: endpoint {
+ remote-endpoint = <&tpda_modem_in1>;
+ };
+ };
+ };
+ };
};
---
base-commit: 0f2995693867bfb26197b117cd55624ddc57582f
change-id: 20251117-add-coresight-nodes-for-pakala-65620d8ca6e9
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: qcom: dts: sm8750: add coresight nodes
2025-11-17 9:31 [PATCH] arm64: qcom: dts: sm8750: add coresight nodes Jie Gan
@ 2025-11-18 10:03 ` Konrad Dybcio
2025-11-19 2:01 ` Jie Gan
0 siblings, 1 reply; 4+ messages in thread
From: Konrad Dybcio @ 2025-11-18 10:03 UTC (permalink / raw)
To: Jie Gan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/17/25 10:31 AM, Jie Gan wrote:
> Add CoreSight DT nodes for AOSS, QDSS, Turing, and Modem blocks to enable
> the STM and TPDM sources to route trace data to the ETF for debugging.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/sm8750.dtsi | 981 +++++++++++++++++++++++++++++++++++
> 1 file changed, 981 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> index 3f0b57f428bb..56c2605f3e0d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
> @@ -3313,6 +3313,948 @@ tcsrcc: clock-controller@f204008 {
> #reset-cells = <1>;
> };
>
> + stm@10002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0x0 0x10002000 0x0 0x1000>,
> + <0x0 0x37280000 0x0 0x180000>;
This region is a little bigger but it's not described clearly. Is there
a reason to use this slice of it and not the whole thing?
[...]
> + funnel_in0_in0: endpoint {
> + remote-endpoint =
> + <&tn_ag_out>;
Please unwrap this line
[...]
> + tn@109ab000 {
> + compatible = "qcom,coresight-tnoc", "arm,primecell";
"tnoc@"?
[...]
> + tpdm_llm {
Node names still can't include underscores ;)
Please also rename 'llm' and 'turing' to 'cdsp' unless there's a good
reason not to
I confirmed the coresight components addresses match their claimed function
Konrad
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: qcom: dts: sm8750: add coresight nodes
2025-11-18 10:03 ` Konrad Dybcio
@ 2025-11-19 2:01 ` Jie Gan
2025-11-19 14:06 ` Konrad Dybcio
0 siblings, 1 reply; 4+ messages in thread
From: Jie Gan @ 2025-11-19 2:01 UTC (permalink / raw)
To: Konrad Dybcio, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/18/2025 6:03 PM, Konrad Dybcio wrote:
> On 11/17/25 10:31 AM, Jie Gan wrote:
>> Add CoreSight DT nodes for AOSS, QDSS, Turing, and Modem blocks to enable
>> the STM and TPDM sources to route trace data to the ETF for debugging.
>>
>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 981 +++++++++++++++++++++++++++++++++++
>> 1 file changed, 981 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> index 3f0b57f428bb..56c2605f3e0d 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>> @@ -3313,6 +3313,948 @@ tcsrcc: clock-controller@f204008 {
>> #reset-cells = <1>;
>> };
>>
>> + stm@10002000 {
>> + compatible = "arm,coresight-stm", "arm,primecell";
>> + reg = <0x0 0x10002000 0x0 0x1000>,
>> + <0x0 0x37280000 0x0 0x180000>;
>
> This region is a little bigger but it's not described clearly. Is there
> a reason to use this slice of it and not the whole thing?
This region is about the STM channels which are allocated for APSS/HLOS.
The channel 10240-20479 is allocated for APSS/HLOS, each occupied 256.
So the start address is 10240 * 256 = 2,621,440 (0x28000). The length is
0x180000 because we only use part of these channels so far.
>
> [...]
>
>> + funnel_in0_in0: endpoint {
>> + remote-endpoint =
>> + <&tn_ag_out>;
>
> Please unwrap this line
Will fix it.
>
> [...]
>
>
>> + tn@109ab000 {
>> + compatible = "qcom,coresight-tnoc", "arm,primecell";
>
> "tnoc@"?
In dt-binding, we suggested tn, it also could be tnoc here.
>
> [...]
>
>
>> + tpdm_llm {
>
> Node names still can't include underscores ;)
Sure, missed this part, will fix.
>
> Please also rename 'llm' and 'turing' to 'cdsp' unless there's a good
> reason not to
>
Will fix.
> I confirmed the coresight components addresses match their claimed function
Thanks for checking, it's a huge effort.
Thanks,
Jie
>
> Konrad
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] arm64: qcom: dts: sm8750: add coresight nodes
2025-11-19 2:01 ` Jie Gan
@ 2025-11-19 14:06 ` Konrad Dybcio
0 siblings, 0 replies; 4+ messages in thread
From: Konrad Dybcio @ 2025-11-19 14:06 UTC (permalink / raw)
To: Jie Gan, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Tingwei Zhang
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/19/25 3:01 AM, Jie Gan wrote:
>
>
> On 11/18/2025 6:03 PM, Konrad Dybcio wrote:
>> On 11/17/25 10:31 AM, Jie Gan wrote:
>>> Add CoreSight DT nodes for AOSS, QDSS, Turing, and Modem blocks to enable
>>> the STM and TPDM sources to route trace data to the ETF for debugging.
>>>
>>> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
>>> ---
>>> arch/arm64/boot/dts/qcom/sm8750.dtsi | 981 +++++++++++++++++++++++++++++++++++
>>> 1 file changed, 981 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>>> index 3f0b57f428bb..56c2605f3e0d 100644
>>> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
>>> @@ -3313,6 +3313,948 @@ tcsrcc: clock-controller@f204008 {
>>> #reset-cells = <1>;
>>> };
>>> + stm@10002000 {
>>> + compatible = "arm,coresight-stm", "arm,primecell";
>>> + reg = <0x0 0x10002000 0x0 0x1000>,
>>> + <0x0 0x37280000 0x0 0x180000>;
>>
>> This region is a little bigger but it's not described clearly. Is there
>> a reason to use this slice of it and not the whole thing?
>
> This region is about the STM channels which are allocated for APSS/HLOS. The channel 10240-20479 is allocated for APSS/HLOS, each occupied 256. So the start address is 10240 * 256 = 2,621,440 (0x28000). The length is 0x180000 because we only use part of these channels so far.
This is useful information. Could we better document it internally in the
usual place one would go to check on registers?
Konrad
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-11-19 14:06 UTC | newest]
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2025-11-17 9:31 [PATCH] arm64: qcom: dts: sm8750: add coresight nodes Jie Gan
2025-11-18 10:03 ` Konrad Dybcio
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2025-11-19 14:06 ` Konrad Dybcio
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