* [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board
@ 2025-11-20 8:29 Hal Feng
2025-11-20 8:29 ` [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property Hal Feng
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Hal Feng @ 2025-11-20 8:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow
Cc: Hal Feng, devicetree, linux-riscv, linux-kernel
VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI
VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
Changes since v2:
- Drop patch 3, 4, 5.
patch 6:
- jh7110s-starfive-visionfive-2-lite.dtsi directly includes "jh7110.dtsi"
instead of "jh7110s-common.dtsi".
Changes since v1:
- Drop patch 1 because it is applied.
- Rename jh7110.dtsi to jh711x.dtsi.
- Move the content of jh7110-common.dtsi to the new file
jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
patch 4:
- Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
patch 5:
- Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.
Changes since RFC:
- Add jh7110s compatible to the generic cpufreq driver.
- Fix the dtbs_check error by adding the missing "enable-gpios" property
in jh7110 pcie dt-bindings.
- Rebase on the latest mainline.
- Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
for VisionFive 2 Lite variants.
- Add usb switch pin configuration (GPIO62).
- Improve the commit messages.
History:
v2: https://lore.kernel.org/all/20251107095530.114775-1-hal.feng@starfivetech.com/
v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/
Hal Feng (5):
dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
board
riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite
variants
riscv: dts: starfive: Add VisionFive 2 Lite board device tree
riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
.../bindings/pci/starfive,jh7110-pcie.yaml | 4 +
.../devicetree/bindings/riscv/starfive.yaml | 6 +
arch/riscv/boot/dts/starfive/Makefile | 3 +
...h7110s-starfive-visionfive-2-lite-emmc.dts | 22 +
.../jh7110s-starfive-visionfive-2-lite.dts | 20 +
.../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++
6 files changed, 746 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
base-commit: fe4d0dea039f2befb93f27569593ec209843b0f5
--
2.43.2
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
@ 2025-11-20 8:29 ` Hal Feng
2025-11-20 12:52 ` Manivannan Sadhasivam
2025-11-20 8:29 ` [PATCH v3 2/5] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board Hal Feng
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Hal Feng @ 2025-11-20 8:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow
Cc: Hal Feng, devicetree, linux-riscv, linux-kernel
Add enable-gpios property for controlling the PCI bus device power.
This property had been supported in the driver but not added in the
dt-bindings.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Fixes: 22fe32239770 ("dt-bindings: PCI: Add StarFive JH7110 PCIe controller")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../devicetree/bindings/pci/starfive,jh7110-pcie.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
index 33c80626e8ec..1e36f92ec852 100644
--- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
@@ -59,6 +59,10 @@ properties:
description:
The phandle to System Register Controller syscon node.
+ enable-gpios:
+ description: GPIO used to enable the PCI bus device power
+ maxItems: 1
+
perst-gpios:
description: GPIO controlled connection to PERST# signal
maxItems: 1
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/5] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
2025-11-20 8:29 ` [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property Hal Feng
@ 2025-11-20 8:29 ` Hal Feng
2025-11-20 16:24 ` Rob Herring (Arm)
2025-11-20 8:29 ` [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants Hal Feng
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Hal Feng @ 2025-11-20 8:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow
Cc: Hal Feng, devicetree, linux-riscv, linux-kernel
Add device tree bindings for the StarFive JH7110S SoC
and the VisionFive 2 Lite board equipped with it.
JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
and up to 1.25GHz. Its CPU cores and peripherals are the same as
those of the JH7110 SoC.
VisionFive 2 Lite boards have SD card version (default) and eMMC version,
which are called "VisionFive 2 Lite" and "VisionFive 2 Lite eMMC"
respectively.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 04510341a71e..797d9956b949 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -35,6 +35,12 @@ properties:
- starfive,visionfive-2-v1.3b
- const: starfive,jh7110
+ - items:
+ - enum:
+ - starfive,visionfive-2-lite
+ - starfive,visionfive-2-lite-emmc
+ - const: starfive,jh7110s
+
additionalProperties: true
...
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
2025-11-20 8:29 ` [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property Hal Feng
2025-11-20 8:29 ` [PATCH v3 2/5] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board Hal Feng
@ 2025-11-20 8:29 ` Hal Feng
2025-11-21 11:51 ` Emil Renner Berthing
2025-11-20 8:29 ` [PATCH v3 4/5] riscv: dts: starfive: Add VisionFive 2 Lite board device tree Hal Feng
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Hal Feng @ 2025-11-20 8:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow
Cc: Hal Feng, devicetree, linux-riscv, linux-kernel
Add common board dtsi for use by VisionFive 2 Lite variants.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++
1 file changed, 691 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
new file mode 100644
index 000000000000..aa375c4a3fa3
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
@@ -0,0 +1,691 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include "jh7110-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
+
+/ {
+ aliases {
+ ethernet0 = &gmac0;
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ mmc0 = &mmc0;
+ mmc1 = &mmc1;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ bootph-pre-ram;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_power: led-0 {
+ gpios = <&aongpio 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&cpu_opp {
+ /delete-node/ opp-375000000;
+ /delete-node/ opp-500000000;
+ /delete-node/ opp-750000000;
+ /delete-node/ opp-1500000000;
+
+ opp-312500000 {
+ opp-hz = /bits/ 64 <312500000>;
+ opp-microvolt = <800000>;
+ };
+ opp-417000000 {
+ opp-hz = /bits/ 64 <417000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-625000000 {
+ opp-hz = /bits/ 64 <625000000>;
+ opp-microvolt = <800000>;
+ };
+ opp-1250000000 {
+ opp-hz = /bits/ 64 <1250000000>;
+ opp-microvolt = <1000000>;
+ };
+};
+
+&cpus {
+ timebase-frequency = <4000000>;
+};
+
+&dvp_clk {
+ clock-frequency = <74250000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&hdmitx0_pixelclk {
+ clock-frequency = <297000000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&camss {
+ assigned-clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>,
+ <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>;
+ assigned-clock-rates = <49500000>, <198000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ camss_from_csi2rx: endpoint {
+ remote-endpoint = <&csi2rx_to_camss>;
+ };
+ };
+ };
+};
+
+&csi2rx {
+ assigned-clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>;
+ assigned-clock-rates = <297000000>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ /* remote MIPI sensor endpoint */
+ };
+
+ port@1 {
+ reg = <1>;
+
+ csi2rx_to_camss: endpoint {
+ remote-endpoint = <&camss_from_csi2rx>;
+ };
+ };
+ };
+};
+
+&gmac0 {
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ starfive,tx-use-rgmii-clk;
+ assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+ assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ motorcomm,tx-clk-adj-enabled;
+ motorcomm,tx-clk-100-inverted;
+ motorcomm,tx-clk-1000-inverted;
+ motorcomm,rx-clk-drv-microamp = <3970>;
+ motorcomm,rx-data-drv-microamp = <2910>;
+ rx-internal-delay-ps = <1500>;
+ tx-internal-delay-ps = <1500>;
+ };
+ };
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+
+ axp15060: pmic@36 {
+ compatible = "x-powers,axp15060";
+ reg = <0x36>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ regulators {
+ vcc_3v3: dcdc1 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_3v3";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1540000>;
+ regulator-name = "vdd_cpu";
+ };
+
+ emmc_vdd: aldo4 {
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "emmc_vdd";
+ };
+ };
+ };
+
+ eeprom@50 {
+ compatible = "atmel,24c04";
+ reg = <0x50>;
+ bootph-pre-ram;
+ pagesize = <16>;
+ };
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ max-frequency = <100000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ bus-width = <8>;
+ bootph-pre-ram;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "okay";
+};
+
+&mmc1 {
+ max-frequency = <50000000>;
+ assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
+ assigned-clock-rates = <50000000>;
+ bus-width = <4>;
+ bootph-pre-ram;
+ cap-sd-highspeed;
+ keep-power-in-suspend;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ status = "okay";
+};
+
+&pcie1 {
+ enable-gpios = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
+ perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>;
+ phys = <&pciephy1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&qspi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ nor_flash: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ bootph-pre-ram;
+ cdns,read-delay = <2>;
+ spi-max-frequency = <100000000>;
+ cdns,tshsl-ns = <1>;
+ cdns,tsd2d-ns = <1>;
+ cdns,tchsh-ns = <1>;
+ cdns,tslch-ns = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ spl@0 {
+ reg = <0x0 0xf0000>;
+ };
+ uboot-env@f0000 {
+ reg = <0xf0000 0x10000>;
+ };
+ uboot@100000 {
+ reg = <0x100000 0xf00000>;
+ };
+ };
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+};
+
+&syscrg {
+ assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+ <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+ <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF>,
+ <&syscrg JH7110_SYSCLK_CPU_CORE>,
+ <&pllclk JH7110_PLLCLK_PLL0_OUT>;
+ assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+ <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+ <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+ assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
+};
+
+&sysgpio {
+ i2c0_pins: i2c0-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(57, GPOUT_LOW,
+ GPOEN_SYS_I2C0_CLK,
+ GPI_SYS_I2C0_CLK)>,
+ <GPIOMUX(58, GPOUT_LOW,
+ GPOEN_SYS_I2C0_DATA,
+ GPI_SYS_I2C0_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c2_pins: i2c2-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(3, GPOUT_LOW,
+ GPOEN_SYS_I2C2_CLK,
+ GPI_SYS_I2C2_CLK)>,
+ <GPIOMUX(2, GPOUT_LOW,
+ GPOEN_SYS_I2C2_DATA,
+ GPI_SYS_I2C2_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-0 {
+ bootph-pre-ram;
+
+ i2c-pins {
+ pinmux = <GPIOMUX(19, GPOUT_LOW,
+ GPOEN_SYS_I2C5_CLK,
+ GPI_SYS_I2C5_CLK)>,
+ <GPIOMUX(20, GPOUT_LOW,
+ GPOEN_SYS_I2C5_DATA,
+ GPI_SYS_I2C5_DATA)>;
+ bias-disable; /* external pull-up */
+ bootph-pre-ram;
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c6_pins: i2c6-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(16, GPOUT_LOW,
+ GPOEN_SYS_I2C6_CLK,
+ GPI_SYS_I2C6_CLK)>,
+ <GPIOMUX(17, GPOUT_LOW,
+ GPOEN_SYS_I2C6_DATA,
+ GPI_SYS_I2C6_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ mmc0_pins: mmc0-0 {
+ mmc-pins {
+ pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
+ <PINMUX(PAD_SD0_CMD, 0)>,
+ <PINMUX(PAD_SD0_DATA0, 0)>,
+ <PINMUX(PAD_SD0_DATA1, 0)>,
+ <PINMUX(PAD_SD0_DATA2, 0)>,
+ <PINMUX(PAD_SD0_DATA3, 0)>,
+ <PINMUX(PAD_SD0_DATA4, 0)>,
+ <PINMUX(PAD_SD0_DATA5, 0)>,
+ <PINMUX(PAD_SD0_DATA6, 0)>,
+ <PINMUX(PAD_SD0_DATA7, 0)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ };
+ };
+
+ mmc1_pins: mmc1-0 {
+ clk-pins {
+ pinmux = <GPIOMUX(10, GPOUT_SYS_SDIO1_CLK,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ mmc-pins {
+ pinmux = <GPIOMUX(9, GPOUT_SYS_SDIO1_CMD,
+ GPOEN_SYS_SDIO1_CMD,
+ GPI_SYS_SDIO1_CMD)>,
+ <GPIOMUX(11, GPOUT_SYS_SDIO1_DATA0,
+ GPOEN_SYS_SDIO1_DATA0,
+ GPI_SYS_SDIO1_DATA0)>,
+ <GPIOMUX(12, GPOUT_SYS_SDIO1_DATA1,
+ GPOEN_SYS_SDIO1_DATA1,
+ GPI_SYS_SDIO1_DATA1)>,
+ <GPIOMUX(7, GPOUT_SYS_SDIO1_DATA2,
+ GPOEN_SYS_SDIO1_DATA2,
+ GPI_SYS_SDIO1_DATA2)>,
+ <GPIOMUX(8, GPOUT_SYS_SDIO1_DATA3,
+ GPOEN_SYS_SDIO1_DATA3,
+ GPI_SYS_SDIO1_DATA3)>;
+ bias-pull-up;
+ drive-strength = <12>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ pcie1_pins: pcie1-0 {
+ clkreq-pins {
+ pinmux = <GPIOMUX(29, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-down;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ wake-pins {
+ pinmux = <GPIOMUX(21, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_NONE)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ pwm_pins: pwm-0 {
+ pwm-pins {
+ pinmux = <GPIOMUX(46, GPOUT_SYS_PWM_CHANNEL0,
+ GPOEN_SYS_PWM0_CHANNEL0,
+ GPI_NONE)>,
+ <GPIOMUX(59, GPOUT_SYS_PWM_CHANNEL1,
+ GPOEN_SYS_PWM0_CHANNEL1,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+ };
+
+ spi0_pins: spi0-0 {
+ mosi-pins {
+ pinmux = <GPIOMUX(52, GPOUT_SYS_SPI0_TXD,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+
+ miso-pins {
+ pinmux = <GPIOMUX(53, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_SPI0_RXD)>;
+ bias-pull-up;
+ input-enable;
+ input-schmitt-enable;
+ };
+
+ sck-pins {
+ pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_CLK,
+ GPOEN_ENABLE,
+ GPI_SYS_SPI0_CLK)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+
+ ss-pins {
+ pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
+ GPOEN_ENABLE,
+ GPI_SYS_SPI0_FSS)>;
+ bias-disable;
+ input-disable;
+ input-schmitt-disable;
+ };
+ };
+
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_UART0_RX)>;
+ bias-disable; /* external pull-up */
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ uart1_pins: uart1-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(23, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_UART1_RX)>;
+ bias-pull-up;
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+
+ cts-pins {
+ pinmux = <GPIOMUX(24, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_UART1_CTS)>;
+ input-enable;
+ };
+
+ rts-pins {
+ pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ input-enable;
+ };
+ };
+
+ usb0_pins: usb0-0 {
+ power-pins {
+ pinmux = <GPIOMUX(26, GPOUT_HIGH,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ input-disable;
+ };
+
+ switch-pins {
+ pinmux = <GPIOMUX(62, GPOUT_LOW,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ input-disable;
+ };
+ };
+};
+
+&uart0 {
+ bootph-pre-ram;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_pins>;
+ status = "okay";
+};
+
+&usb_cdns3 {
+ phys = <&usbphy0>, <&pciephy0>;
+ phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};
+
+&U74_1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&U74_4 {
+ cpu-supply = <&vdd_cpu>;
+};
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/5] riscv: dts: starfive: Add VisionFive 2 Lite board device tree
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
` (2 preceding siblings ...)
2025-11-20 8:29 ` [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants Hal Feng
@ 2025-11-20 8:29 ` Hal Feng
2025-11-21 11:51 ` Emil Renner Berthing
2025-11-20 8:29 ` [PATCH v3 5/5] riscv: dts: starfive: Add VisionFive 2 Lite eMMC " Hal Feng
2025-11-21 18:23 ` [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Matthias Brugger
5 siblings, 1 reply; 16+ messages in thread
From: Hal Feng @ 2025-11-20 8:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow
Cc: Hal Feng, devicetree, linux-riscv, linux-kernel
VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI
VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/Makefile | 2 ++
.../jh7110s-starfive-visionfive-2-lite.dts | 20 +++++++++++++++++++
2 files changed, 22 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 62b659f89ba7..f53109253d41 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -15,3 +15,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
+
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
new file mode 100644
index 000000000000..ac5e66027bad
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110s-starfive-visionfive-2-lite.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 Lite";
+ compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
+ disable-wp;
+ cap-sd-highspeed;
+};
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 5/5] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
` (3 preceding siblings ...)
2025-11-20 8:29 ` [PATCH v3 4/5] riscv: dts: starfive: Add VisionFive 2 Lite board device tree Hal Feng
@ 2025-11-20 8:29 ` Hal Feng
2025-11-21 11:52 ` Emil Renner Berthing
2025-11-21 18:23 ` [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Matthias Brugger
5 siblings, 1 reply; 16+ messages in thread
From: Hal Feng @ 2025-11-20 8:29 UTC (permalink / raw)
To: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow
Cc: Hal Feng, devicetree, linux-riscv, linux-kernel
VisionFive 2 Lite eMMC board uses a non-removable onboard 64GiB eMMC
instead of the MicroSD slot.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/Makefile | 1 +
...h7110s-starfive-visionfive-2-lite-emmc.dts | 22 +++++++++++++++++++
2 files changed, 23 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index f53109253d41..a60244803829 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -17,3 +17,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110s-starfive-visionfive-2-lite-emmc.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
new file mode 100644
index 000000000000..60ce2753f2d1
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110s-starfive-visionfive-2-lite.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 Lite eMMC";
+ compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s";
+};
+
+&mmc0 {
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&emmc_vdd>;
+};
--
2.43.2
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
2025-11-20 8:29 ` [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property Hal Feng
@ 2025-11-20 12:52 ` Manivannan Sadhasivam
2025-11-21 4:23 ` Hal Feng
0 siblings, 1 reply; 16+ messages in thread
From: Manivannan Sadhasivam @ 2025-11-20 12:52 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Emil Renner Berthing, Heinrich Schuchardt, E Shattow, devicetree,
linux-riscv, linux-kernel
On Thu, Nov 20, 2025 at 04:29:42PM +0800, Hal Feng wrote:
> Add enable-gpios property for controlling the PCI bus device power.
> This property had been supported in the driver but not added in the
> dt-bindings.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Fixes: 22fe32239770 ("dt-bindings: PCI: Add StarFive JH7110 PCIe controller")
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../devicetree/bindings/pci/starfive,jh7110-pcie.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> index 33c80626e8ec..1e36f92ec852 100644
> --- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> @@ -59,6 +59,10 @@ properties:
> description:
> The phandle to System Register Controller syscon node.
>
> + enable-gpios:
> + description: GPIO used to enable the PCI bus device power
This feels wrong to me. Is this GPIO associated with the PCIe controller? I bet
this is just controlling some regulator that powers the VDD of the PCIe
device/slot. If so, this should be added as a part of the regulator node and
referenced in the PCIe node using the existing -supply properties.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 2/5] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board
2025-11-20 8:29 ` [PATCH v3 2/5] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board Hal Feng
@ 2025-11-20 16:24 ` Rob Herring (Arm)
0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring (Arm) @ 2025-11-20 16:24 UTC (permalink / raw)
To: Hal Feng
Cc: E Shattow, devicetree, Viresh Kumar, Krzysztof Wilczyński,
Manivannan Sadhasivam, Lorenzo Pieralisi, Emil Renner Berthing,
Heinrich Schuchardt, Palmer Dabbelt, linux-riscv,
Rafael J . Wysocki, linux-kernel, Conor Dooley, Paul Walmsley,
Albert Ou, Krzysztof Kozlowski, Bjorn Helgaas
On Thu, 20 Nov 2025 16:29:43 +0800, Hal Feng wrote:
> Add device tree bindings for the StarFive JH7110S SoC
> and the VisionFive 2 Lite board equipped with it.
>
> JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
> and up to 1.25GHz. Its CPU cores and peripherals are the same as
> those of the JH7110 SoC.
>
> VisionFive 2 Lite boards have SD card version (default) and eMMC version,
> which are called "VisionFive 2 Lite" and "VisionFive 2 Lite eMMC"
> respectively.
>
> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
2025-11-20 12:52 ` Manivannan Sadhasivam
@ 2025-11-21 4:23 ` Hal Feng
2025-11-23 14:33 ` Krzysztof Kozlowski
0 siblings, 1 reply; 16+ messages in thread
From: Hal Feng @ 2025-11-21 4:23 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Emil Renner Berthing, Heinrich Schuchardt, E Shattow,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
> On 12.11.25 21:54, Manivannan Sadhasivam wrote:
> On Thu, Nov 20, 2025 at 04:29:42PM +0800, Hal Feng wrote:
> > Add enable-gpios property for controlling the PCI bus device power.
> > This property had been supported in the driver but not added in the
> > dt-bindings.
> >
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Fixes: 22fe32239770 ("dt-bindings: PCI: Add StarFive JH7110 PCIe
> > controller")
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > .../devicetree/bindings/pci/starfive,jh7110-pcie.yaml | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > index 33c80626e8ec..1e36f92ec852 100644
> > --- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > @@ -59,6 +59,10 @@ properties:
> > description:
> > The phandle to System Register Controller syscon node.
> >
> > + enable-gpios:
> > + description: GPIO used to enable the PCI bus device power
>
> This feels wrong to me. Is this GPIO associated with the PCIe controller? I bet
> this is just controlling some regulator that powers the VDD of the PCIe
> device/slot. If so, this should be added as a part of the regulator node and
> referenced in the PCIe node using the existing -supply properties.
This GPIO just controls the power of PCIe devices, not PCIe controller.
I think there may be no design adding power control GPIOs for the PCIe controller,
because usually we don't need to control the PCIe controller power but the PCIe
device power.
I find a similar "pwren-gpios" in
Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml .
It uses the GPIO to control the power of PCIe devices too.
Could I continue to do so? Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
2025-11-20 8:29 ` [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants Hal Feng
@ 2025-11-21 11:51 ` Emil Renner Berthing
2025-11-22 3:30 ` E Shattow
2025-11-25 9:54 ` Hal Feng
0 siblings, 2 replies; 16+ messages in thread
From: Emil Renner Berthing @ 2025-11-21 11:51 UTC (permalink / raw)
To: Albert Ou, Bjorn Helgaas, Conor Dooley, E Shattow, Hal Feng,
Heinrich Schuchardt, Krzysztof Kozlowski,
Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Palmer Dabbelt, Paul Walmsley,
Rafael J . Wysocki, Rob Herring, Viresh Kumar
Cc: devicetree, linux-riscv, linux-kernel
Quoting Hal Feng (2025-11-20 09:29:44)
> Add common board dtsi for use by VisionFive 2 Lite variants.
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> .../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++
> 1 file changed, 691 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
> new file mode 100644
> index 000000000000..aa375c4a3fa3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
> @@ -0,0 +1,691 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
''
I'm confused. In [1] you said "remove jh7110s-common.dtsi, because only one
board uses JH7110S now." but this series still adds two different boards.
Also this derives from jh7110.dtsi rather than from jh7110-common.dts as I
suggested in [2].
In any case I'm fine with doing it this way, so
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[1]: https://lore.kernel.org/linux-riscv/ZQ2PR01MB13076544E2136E7E7C2EEDA1E6CD2@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn/
[2]: https://lore.kernel.org/linux-riscv/CAJM55Z-MfpVX3EuQ_AjvDSk6FwR51R5cQdN5RybS9pbJ8r9NNg@mail.gmail.com/
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 4/5] riscv: dts: starfive: Add VisionFive 2 Lite board device tree
2025-11-20 8:29 ` [PATCH v3 4/5] riscv: dts: starfive: Add VisionFive 2 Lite board device tree Hal Feng
@ 2025-11-21 11:51 ` Emil Renner Berthing
0 siblings, 0 replies; 16+ messages in thread
From: Emil Renner Berthing @ 2025-11-21 11:51 UTC (permalink / raw)
To: Albert Ou, Bjorn Helgaas, Conor Dooley, E Shattow, Hal Feng,
Heinrich Schuchardt, Krzysztof Kozlowski,
Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Palmer Dabbelt, Paul Walmsley,
Rafael J . Wysocki, Rob Herring, Viresh Kumar
Cc: devicetree, linux-riscv, linux-kernel
Quoting Hal Feng (2025-11-20 09:29:45)
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
>
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
>
> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 5/5] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
2025-11-20 8:29 ` [PATCH v3 5/5] riscv: dts: starfive: Add VisionFive 2 Lite eMMC " Hal Feng
@ 2025-11-21 11:52 ` Emil Renner Berthing
0 siblings, 0 replies; 16+ messages in thread
From: Emil Renner Berthing @ 2025-11-21 11:52 UTC (permalink / raw)
To: Albert Ou, Bjorn Helgaas, Conor Dooley, E Shattow, Hal Feng,
Heinrich Schuchardt, Krzysztof Kozlowski,
Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Palmer Dabbelt, Paul Walmsley,
Rafael J . Wysocki, Rob Herring, Viresh Kumar
Cc: devicetree, linux-riscv, linux-kernel
Quoting Hal Feng (2025-11-20 09:29:46)
> VisionFive 2 Lite eMMC board uses a non-removable onboard 64GiB eMMC
> instead of the MicroSD slot.
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
` (4 preceding siblings ...)
2025-11-20 8:29 ` [PATCH v3 5/5] riscv: dts: starfive: Add VisionFive 2 Lite eMMC " Hal Feng
@ 2025-11-21 18:23 ` Matthias Brugger
5 siblings, 0 replies; 16+ messages in thread
From: Matthias Brugger @ 2025-11-21 18:23 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Emil Renner Berthing, Heinrich Schuchardt,
E Shattow, devicetree, linux-riscv, linux-kernel
On Thu, Nov 20, 2025 at 04:29:41PM +0800, Hal Feng wrote:
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
>
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
>
> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
>
> Changes since v2:
> - Drop patch 3, 4, 5.
> patch 6:
> - jh7110s-starfive-visionfive-2-lite.dtsi directly includes "jh7110.dtsi"
> instead of "jh7110s-common.dtsi".
>
> Changes since v1:
> - Drop patch 1 because it is applied.
> - Rename jh7110.dtsi to jh711x.dtsi.
> - Move the content of jh7110-common.dtsi to the new file
> jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
> patch 4:
> - Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
> patch 5:
> - Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.
>
> Changes since RFC:
> - Add jh7110s compatible to the generic cpufreq driver.
> - Fix the dtbs_check error by adding the missing "enable-gpios" property
> in jh7110 pcie dt-bindings.
> - Rebase on the latest mainline.
> - Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
> for VisionFive 2 Lite variants.
> - Add usb switch pin configuration (GPIO62).
> - Improve the commit messages.
>
> History:
> v2: https://lore.kernel.org/all/20251107095530.114775-1-hal.feng@starfivetech.com/
> v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
> RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/
>
> Hal Feng (5):
> dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
> dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
> board
> riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite
> variants
> riscv: dts: starfive: Add VisionFive 2 Lite board device tree
> riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
>
> .../bindings/pci/starfive,jh7110-pcie.yaml | 4 +
> .../devicetree/bindings/riscv/starfive.yaml | 6 +
> arch/riscv/boot/dts/starfive/Makefile | 3 +
> ...h7110s-starfive-visionfive-2-lite-emmc.dts | 22 +
> .../jh7110s-starfive-visionfive-2-lite.dts | 20 +
> .../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++
> 6 files changed, 746 insertions(+)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite-emmc.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>
>
> base-commit: fe4d0dea039f2befb93f27569593ec209843b0f5
> --
Tested against v6.18-rc6 together with
fa939a287224d ("dts: starfive: jh7110-common: split out mmc0 reset pins from common into boards")
Tested-by: Matthias Brugger <mbrugger@suse.com>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
2025-11-21 11:51 ` Emil Renner Berthing
@ 2025-11-22 3:30 ` E Shattow
2025-11-25 9:54 ` Hal Feng
1 sibling, 0 replies; 16+ messages in thread
From: E Shattow @ 2025-11-22 3:30 UTC (permalink / raw)
To: Emil Renner Berthing, Albert Ou, Bjorn Helgaas, Conor Dooley,
Hal Feng, Heinrich Schuchardt, Krzysztof Kozlowski,
Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Palmer Dabbelt, Paul Walmsley,
Rafael J . Wysocki, Rob Herring, Viresh Kumar
Cc: devicetree, linux-riscv, linux-kernel
On 11/21/25 03:51, Emil Renner Berthing wrote:
> Quoting Hal Feng (2025-11-20 09:29:44)
>> Add common board dtsi for use by VisionFive 2 Lite variants.
>>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> .../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++
>> 1 file changed, 691 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>> new file mode 100644
>> index 000000000000..aa375c4a3fa3
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
>> @@ -0,0 +1,691 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110.dtsi"
>> +#include "jh7110-pinfunc.h"
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/leds/common.h>
>> +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
> ''
> I'm confused. In [1] you said "remove jh7110s-common.dtsi, because only one
> board uses JH7110S now." but this series still adds two different boards.
>
> Also this derives from jh7110.dtsi rather than from jh7110-common.dts as I
> suggested in [2].
>
> In any case I'm fine with doing it this way, so
> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> [1]: https://lore.kernel.org/linux-riscv/ZQ2PR01MB13076544E2136E7E7C2EEDA1E6CD2@ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn/
> [2]: https://lore.kernel.org/linux-riscv/CAJM55Z-MfpVX3EuQ_AjvDSk6FwR51R5cQdN5RybS9pbJ8r9NNg@mail.gmail.com/
"Yes" or "No" question from me: Is it necessary to introduce new
"jh7110s" compatible?
I am also confused as suggestions and feedback from v2 are not
implemented in v3:
"jh7110" or "jh7110s" filename prefix ?
<prefix>-starfive-visionfive-2-lite.dtsi includes jh7110-common.dtsi ?
Not changed in v3 with include of "jh7110.dtsi" and duplicating
jh7110-common.dtsi in a board dtsi file. This may be acceptable but it
makes no sense to me why is this done when the suggestion is for minimal
changes.
<prefix>-starfive-visionfive-2-lite.dtsi adds four pairs of
'/delete-property/' with OPP table where different from jh7110-common.dtsi ?
<prefix>-starfive-visionfive-2-lite.dts:
compatible = "starfive,visionfive-2-lite", "starfive,jh7110"
? (or else)
compatible = "starfive,visionfive-2-lite", "starfive,jh7110s"
? (or else)
compatible = "starfive,visionfive-2-lite", "starfive,jh7110s",
"starfive,jh7110"
?
<prefix>-starfive-visionfive-2-lite-emmc.dts:
compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110"
? (or else)
compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s"
? (or else)
compatible = "starfive,visionfive-2-lite", "starfive,jh7110s",
"starfive,jh7110"
?
-E
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property
2025-11-21 4:23 ` Hal Feng
@ 2025-11-23 14:33 ` Krzysztof Kozlowski
0 siblings, 0 replies; 16+ messages in thread
From: Krzysztof Kozlowski @ 2025-11-23 14:33 UTC (permalink / raw)
To: Hal Feng, Manivannan Sadhasivam
Cc: Conor Dooley, Rob Herring, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Albert Ou, Rafael J . Wysocki, Viresh Kumar,
Bjorn Helgaas, Lorenzo Pieralisi, Krzysztof Wilczyński,
Emil Renner Berthing, Heinrich Schuchardt, E Shattow,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
On 21/11/2025 05:23, Hal Feng wrote:
>> On 12.11.25 21:54, Manivannan Sadhasivam wrote:
>> On Thu, Nov 20, 2025 at 04:29:42PM +0800, Hal Feng wrote:
>>> Add enable-gpios property for controlling the PCI bus device power.
>>> This property had been supported in the driver but not added in the
>>> dt-bindings.
>>>
>>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>>> Fixes: 22fe32239770 ("dt-bindings: PCI: Add StarFive JH7110 PCIe
>>> controller")
>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>> ---
>>> .../devicetree/bindings/pci/starfive,jh7110-pcie.yaml | 4 ++++
>>> 1 file changed, 4 insertions(+)
>>>
>>> diff --git
>>> a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>>> b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>>> index 33c80626e8ec..1e36f92ec852 100644
>>> --- a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>>> +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
>>> @@ -59,6 +59,10 @@ properties:
>>> description:
>>> The phandle to System Register Controller syscon node.
>>>
>>> + enable-gpios:
>>> + description: GPIO used to enable the PCI bus device power
>>
>> This feels wrong to me. Is this GPIO associated with the PCIe controller? I bet
>> this is just controlling some regulator that powers the VDD of the PCIe
>> device/slot. If so, this should be added as a part of the regulator node and
>> referenced in the PCIe node using the existing -supply properties.
>
> This GPIO just controls the power of PCIe devices, not PCIe controller.
> I think there may be no design adding power control GPIOs for the PCIe controller,
> because usually we don't need to control the PCIe controller power but the PCIe
> device power.
So this is not PCIe controller enable gpios...
>
> I find a similar "pwren-gpios" in
> Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml .
> It uses the GPIO to control the power of PCIe devices too.
>
> Could I continue to do so? Thanks.
No. You already got response what you are supposed to do. Please read it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
2025-11-21 11:51 ` Emil Renner Berthing
2025-11-22 3:30 ` E Shattow
@ 2025-11-25 9:54 ` Hal Feng
1 sibling, 0 replies; 16+ messages in thread
From: Hal Feng @ 2025-11-25 9:54 UTC (permalink / raw)
To: Emil Renner Berthing, Albert Ou, Bjorn Helgaas, Conor Dooley,
E Shattow, Heinrich Schuchardt, Krzysztof Kozlowski,
Krzysztof Wilczyński, Lorenzo Pieralisi,
Manivannan Sadhasivam, Palmer Dabbelt, Paul Walmsley,
Rafael J . Wysocki, Rob Herring, Viresh Kumar
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
> On 21.11.25 19:51, Emil Renner Berthing wrote:
> Quoting Hal Feng (2025-11-20 09:29:44)
> > Add common board dtsi for use by VisionFive 2 Lite variants.
> >
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> > .../jh7110s-starfive-visionfive-2-lite.dtsi | 691 ++++++++++++++++++
> > 1 file changed, 691 insertions(+)
> > create mode 100644
> > arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
> >
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.dtsi
> > new file mode 100644
> > index 000000000000..aa375c4a3fa3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110s-starfive-visionfive-2-lite.
> > +++ dtsi
> > @@ -0,0 +1,691 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com> */
> > +
> > +/dts-v1/;
> > +#include "jh7110.dtsi"
> > +#include "jh7110-pinfunc.h"
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
> ''
> I'm confused. In [1] you said "remove jh7110s-common.dtsi, because only
> one board uses JH7110S now." but this series still adds two different boards.
In my view, VisionFive 2 Lite and VisionFive 2 Lite eMMC are one type of board,
but they have different storage components.
>
> Also this derives from jh7110.dtsi rather than from jh7110-common.dts as I
> suggested in [2].
Sorry, I misunderstood your messages. I sent v4 [1] just now, please check it.
[1] https://lore.kernel.org/all/20251125075604.69370-1-hal.feng@starfivetech.com/
Best regards,
Hal
>
> In any case I'm fine with doing it this way, so
> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>
> [1]: https://lore.kernel.org/linux-
> riscv/ZQ2PR01MB13076544E2136E7E7C2EEDA1E6CD2@ZQ2PR01MB1307.
> CHNPR01.prod.partner.outlook.cn/
> [2]: https://lore.kernel.org/linux-riscv/CAJM55Z-
> MfpVX3EuQ_AjvDSk6FwR51R5cQdN5RybS9pbJ8r9NNg@mail.gmail.com/
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2025-11-25 11:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-20 8:29 [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Hal Feng
2025-11-20 8:29 ` [PATCH v3 1/5] dt-bindings: PCI: starfive,jh7110-pcie: Add enable-gpios property Hal Feng
2025-11-20 12:52 ` Manivannan Sadhasivam
2025-11-21 4:23 ` Hal Feng
2025-11-23 14:33 ` Krzysztof Kozlowski
2025-11-20 8:29 ` [PATCH v3 2/5] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board Hal Feng
2025-11-20 16:24 ` Rob Herring (Arm)
2025-11-20 8:29 ` [PATCH v3 3/5] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants Hal Feng
2025-11-21 11:51 ` Emil Renner Berthing
2025-11-22 3:30 ` E Shattow
2025-11-25 9:54 ` Hal Feng
2025-11-20 8:29 ` [PATCH v3 4/5] riscv: dts: starfive: Add VisionFive 2 Lite board device tree Hal Feng
2025-11-21 11:51 ` Emil Renner Berthing
2025-11-20 8:29 ` [PATCH v3 5/5] riscv: dts: starfive: Add VisionFive 2 Lite eMMC " Hal Feng
2025-11-21 11:52 ` Emil Renner Berthing
2025-11-21 18:23 ` [PATCH v3 0/5] Add support for StarFive VisionFive 2 Lite board Matthias Brugger
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