From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD5C3350D4C; Fri, 21 Nov 2025 14:26:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763735167; cv=none; b=JL2/2sZoIVt8b5LkJ6j0p/mltokNPLDtsbnBePvNrfrk71FUJLG4FDtqYg06hCjgalbzlrfriwcvo3YKljrxJQOI2DPcHzGt72vKs2Jf8pl8E5Iy2fFZqev/5+nNW8IahN+Mab0rtjA88avQc2lFbTzS8qnMtOKXpz5cMhqpIg4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763735167; c=relaxed/simple; bh=YbrPtkB06/Jg3xfKlxAAt1KSm17776sC1HO/GQZ1S88=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ps6mOmuuRBKKMWAQacJrmSrffmvZ7M8rM/joZ1MnldhnIQMiPD5ZX5nvZe3v+Qkz7JPVU+cxbO+sz9QqxTAg9Mpo678WFdRjgEXOPfbc454YJXJhLKiH6xhDT9xAdjlaftdKJ4+wPVP4uv/ojq8iO8emDFpP6FAPkmGgJXnW9pI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=YhMTPHHb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="YhMTPHHb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C5F5AC4CEF1; Fri, 21 Nov 2025 14:26:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1763735166; bh=YbrPtkB06/Jg3xfKlxAAt1KSm17776sC1HO/GQZ1S88=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YhMTPHHbVjfqaYVVAyXmbfZ6m+WxBdDRDNMYB/aFueMvGaIimyUb3L6orZbC3BrCi x4FPHuL/zwELdgYWE/x9SUl5ZFMdEVqWkCGId/cjsX+wyC8Io1ld2f/OKrOvDtb8NX CF4w3J6HAfPSji1auxCoxp8e44KYJ0c+FrDMPGVA= Date: Fri, 21 Nov 2025 15:21:49 +0100 From: Greg Kroah-Hartman To: Roy Luo Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thinh Nguyen , Philipp Zabel , Peter Griffin , =?iso-8859-1?Q?Andr=E9?= Draszik , Tudor Ambarus , Joy Chakraborty , Naveen Kumar , Badhri Jagan Sridharan , Doug Anderson , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v7 2/2] usb: dwc3: Add Google Tensor SoC DWC3 glue driver Message-ID: <2025112144-claw-recolor-49c3@gregkh> References: <20251119093749.292926-1-royluo@google.com> <20251119093749.292926-3-royluo@google.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251119093749.292926-3-royluo@google.com> On Wed, Nov 19, 2025 at 09:37:48AM +0000, Roy Luo wrote: > Add support for the DWC3 USB controller found on Google Tensor G5 > (codename: laguna). The controller features dual-role functionality > and hibernation. > > The primary focus is implementing hibernation support in host mode, > enabling the controller to enter a low-power state (D3). This is > particularly relevant during system power state transition and > runtime power management for power efficiency. > Highlights: > - Align suspend callback with dwc3_suspend_common() for deciding > between a full teardown and hibernation in host mode. > - Integration with `psw` (power switchable) and `top` power domains, > managing their states and device links to support hibernation. > - A notifier callback dwc3_google_usb_psw_pd_notifier() for > `psw` power domain events to manage controller state > transitions to/from D3. > - Coordination of the `non_sticky` reset during power state > transitions, asserting it on D3 entry and deasserting on D0 entry > in hibernation scenario. > - Handling of high-speed and super-speed PME interrupts > that are generated by remote wakeup during hibernation. > > Acked-by: Thinh Nguyen > Co-developed-by: Joy Chakraborty > Signed-off-by: Joy Chakraborty > Co-developed-by: Naveen Kumar > Signed-off-by: Naveen Kumar > Signed-off-by: Roy Luo > --- > drivers/usb/dwc3/Kconfig | 10 + > drivers/usb/dwc3/Makefile | 1 + > drivers/usb/dwc3/dwc3-google.c | 628 +++++++++++++++++++++++++++++++++ > 3 files changed, 639 insertions(+) > create mode 100644 drivers/usb/dwc3/dwc3-google.c > > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig > index 4925d15084f8..bb0e4dc97da3 100644 > --- a/drivers/usb/dwc3/Kconfig > +++ b/drivers/usb/dwc3/Kconfig > @@ -200,4 +200,14 @@ config USB_DWC3_GENERIC_PLAT > the dwc3 child node in the device tree. > Say 'Y' or 'M' here if your platform integrates DWC3 in a similar way. > > +config USB_DWC3_GOOGLE > + tristate "Google Platform" > + depends on OF && COMMON_CLK && RESET_CONTROLLER No build testing? > + default n This is always the default, no need to list it here. > + help > + Support the DesignWare Core USB3 IP found on Google Tensor > + SoCs, starting with the G5 generation. This driver includes > + support for hibernation in host mode. > + Say 'Y' or 'M' if you have one such device. You forgot the module name :( > +#define to_dwc3_google(d) container_of((d), struct dwc3_google, dwc) container_of_const() please. thanks, greg k-h