[PATCH v4 0/6] Add support for StarFive VisionFive 2 Lite board

[PATCH v4 0/6] Add support for StarFive VisionFive 2 Lite board

[Hal Feng]

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.

Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html

Changes since v3:
patch 1:
- Enable PCIe slot 3V3 power using regulator APIs instead of GPIO APIs.
patch 3: (reuse the dts structure implemented in v1)
- Add a new patch to move out the uncommon nodes in jh7110-common.dtsi.
- Include "jh7110-common.dtsi" instead of "jh7110.dtsi".
- Add the regulator-vcc-3v3-pcie node and reference it in the pcie1 node.
patch 3, 4, 5:
- Use "jh7110" instead of "jh7110s" as the device tree filename prefix.

Changes since v2:
- Drop patch 3, 4, 5.
patch 6:
- jh7110s-starfive-visionfive-2-lite.dtsi directly includes "jh7110.dtsi"
  instead of "jh7110s-common.dtsi".

Changes since v1:
- Drop patch 1 because it is applied.
- Rename jh7110.dtsi to jh711x.dtsi.
- Move the content of jh7110-common.dtsi to the new file
  jh711x-common.dtsi and move opp table to jh7110-common.dtsi.
patch 4:
- Move the uncommon nodes to jh7110-common.dtsi instead of board dts.
patch 5:
- Add jh7110s-common.dtsi and include it in jh7110s-starfive-visionfive-2-lite.dtsi.

Changes since RFC:
- Add jh7110s compatible to the generic cpufreq driver.
- Fix the dtbs_check error by adding the missing "enable-gpios" property
  in jh7110 pcie dt-bindings.
- Rebase on the latest mainline.
- Add VisionFive 2 Lite eMMC board device tree and add a common board dtsi
  for VisionFive 2 Lite variants.
- Add usb switch pin configuration (GPIO62).
- Improve the commit messages.

History:
v3: https://lore.kernel.org/all/20251120082946.109378-1-hal.feng@starfivetech.com/
v2: https://lore.kernel.org/all/20251107095530.114775-1-hal.feng@starfivetech.com/
v1: https://lore.kernel.org/all/20251016080054.12484-1-hal.feng@starfivetech.com/
RFC: https://lore.kernel.org/all/20250821100930.71404-1-hal.feng@starfivetech.com/

Hal Feng (6):
  PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the
    3V3 power supply of PCIe slots
  dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite
    board
  riscv: dts: starfive: jh7110-common: Move out some nodes to the board
    dts
  riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite
    variants
  riscv: dts: starfive: Add VisionFive 2 Lite board device tree
  riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree

 .../devicetree/bindings/riscv/starfive.yaml   |   6 +
 arch/riscv/boot/dts/starfive/Makefile         |   2 +
 .../boot/dts/starfive/jh7110-common.dtsi      |   8 -
 .../jh7110-deepcomputing-fml13v01.dts         |  14 ++
 .../boot/dts/starfive/jh7110-milkv-mars.dts   |  14 ++
 .../dts/starfive/jh7110-milkv-marscm-emmc.dts |   9 +
 .../dts/starfive/jh7110-milkv-marscm-lite.dts |   1 +
 .../dts/starfive/jh7110-pine64-star64.dts     |  14 ++
 ...jh7110-starfive-visionfive-2-lite-emmc.dts |  22 +++
 .../jh7110-starfive-visionfive-2-lite.dts     |  20 +++
 .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
 .../jh7110-starfive-visionfive-2.dtsi         |  11 ++
 drivers/pci/controller/plda/pcie-starfive.c   |  25 +--
 13 files changed, 289 insertions(+), 18 deletions(-)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi


base-commit: 422f3140bbcb657e1b86c484296972ab76f6d1ff
-- 
2.43.2

[PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Hal Feng]

The "enable-gpio" property is not documented in the dt-bindings and
using GPIO APIs is not a standard method to enable or disable PCIe
slot power, so use regulator APIs to replace them.

Tested-by: Matthias Brugger <mbrugger@suse.com>
Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 drivers/pci/controller/plda/pcie-starfive.c | 25 ++++++++++++---------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
index 3caf53c6c082..298036c3e7f9 100644
--- a/drivers/pci/controller/plda/pcie-starfive.c
+++ b/drivers/pci/controller/plda/pcie-starfive.c
@@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
 	struct reset_control *resets;
 	struct clk_bulk_data *clks;
 	struct regmap *reg_syscon;
-	struct gpio_desc *power_gpio;
+	struct regulator *vpcie3v3;
 	struct gpio_desc *reset_gpio;
 	struct phy *phy;
 
@@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie,
 		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
 				     "failed to get perst-gpio\n");
 
-	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
-						   GPIOD_OUT_LOW);
-	if (IS_ERR(pcie->power_gpio))
-		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
-				     "failed to get power-gpio\n");
+	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
+	if (IS_ERR(pcie->vpcie3v3)) {
+		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
+			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
+					     "failed to get vpcie3v3 regulator\n");
+		pcie->vpcie3v3 = NULL;
+	}
 
 	return 0;
 }
@@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda)
 		container_of(plda, struct starfive_jh7110_pcie, plda);
 
 	starfive_pcie_clk_rst_deinit(pcie);
-	if (pcie->power_gpio)
-		gpiod_set_value_cansleep(pcie->power_gpio, 0);
+	if (pcie->vpcie3v3)
+		regulator_disable(pcie->vpcie3v3);
 	starfive_pcie_disable_phy(pcie);
 }
 
@@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct plda_pcie_rp *plda)
 	if (ret)
 		return ret;
 
-	if (pcie->power_gpio)
-		gpiod_set_value_cansleep(pcie->power_gpio, 1);
+	if (pcie->vpcie3v3) {
+		ret = regulator_enable(pcie->vpcie3v3);
+		if (ret)
+			dev_err_probe(dev, ret, "failed to enable vpcie3v3 regulator\n");
+	}
 
 	if (pcie->reset_gpio)
 		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
-- 
2.43.2

Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Conor Dooley]

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On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> The "enable-gpio" property is not documented in the dt-bindings and
> using GPIO APIs is not a standard method to enable or disable PCIe
> slot power, so use regulator APIs to replace them.
> 
> Tested-by: Matthias Brugger <mbrugger@suse.com>

Is this actually a valid tag?
He provided one for the series on v3, which didn't include this patch.

[-- Attachment #2: signature.asc --]
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Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Matthias Brugger]

On 25/11/25 21:00, Conor Dooley wrote:
> On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
>> The "enable-gpio" property is not documented in the dt-bindings and
>> using GPIO APIs is not a standard method to enable or disable PCIe
>> slot power, so use regulator APIs to replace them.
>>
>> Tested-by: Matthias Brugger <mbrugger@suse.com>
> 
> Is this actually a valid tag?
> He provided one for the series on v3, which didn't include this patch.
> 

No it is not. As I only tested v3. But I was able to test v4 as well, so 
for the whole series:

Tested-by: Matthias Brugger <mbrugger@suse.com>

Regards,
Matthias

RE: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Hal Feng]

> On 25.11.25 15:56, Hal Feng wrote: 
> The "enable-gpio" property is not documented in the dt-bindings and using
> GPIO APIs is not a standard method to enable or disable PCIe slot power, so
> use regulator APIs to replace them.
> 
> Tested-by: Matthias Brugger <mbrugger@suse.com>
> Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  drivers/pci/controller/plda/pcie-starfive.c | 25 ++++++++++++---------
>  1 file changed, 15 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/pci/controller/plda/pcie-starfive.c
> b/drivers/pci/controller/plda/pcie-starfive.c
> index 3caf53c6c082..298036c3e7f9 100644
> --- a/drivers/pci/controller/plda/pcie-starfive.c
> +++ b/drivers/pci/controller/plda/pcie-starfive.c
> @@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
>  	struct reset_control *resets;
>  	struct clk_bulk_data *clks;
>  	struct regmap *reg_syscon;
> -	struct gpio_desc *power_gpio;
> +	struct regulator *vpcie3v3;
>  	struct gpio_desc *reset_gpio;
>  	struct phy *phy;
> 
> @@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct
> starfive_jh7110_pcie *pcie,
>  		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
>  				     "failed to get perst-gpio\n");
> 
> -	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> -						   GPIOD_OUT_LOW);
> -	if (IS_ERR(pcie->power_gpio))
> -		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> -				     "failed to get power-gpio\n");
> +	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> +	if (IS_ERR(pcie->vpcie3v3)) {
> +		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
> +			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
> +					     "failed to get vpcie3v3
> regulator\n");
> +		pcie->vpcie3v3 = NULL;
> +	}
> 
>  	return 0;
>  }
> @@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct
> plda_pcie_rp *plda)
>  		container_of(plda, struct starfive_jh7110_pcie, plda);
> 
>  	starfive_pcie_clk_rst_deinit(pcie);
> -	if (pcie->power_gpio)
> -		gpiod_set_value_cansleep(pcie->power_gpio, 0);
> +	if (pcie->vpcie3v3)
> +		regulator_disable(pcie->vpcie3v3);
>  	starfive_pcie_disable_phy(pcie);
>  }
> 
> @@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct plda_pcie_rp
> *plda)
>  	if (ret)
>  		return ret;
> 
> -	if (pcie->power_gpio)
> -		gpiod_set_value_cansleep(pcie->power_gpio, 1);
> +	if (pcie->vpcie3v3) {
> +		ret = regulator_enable(pcie->vpcie3v3);
> +		if (ret)
> +			dev_err_probe(dev, ret, "failed to enable vpcie3v3
> regulator\n");
> +	}
> 
>  	if (pcie->reset_gpio)
>  		gpiod_set_value_cansleep(pcie->reset_gpio, 1);

Hi, Manivannan and the other PCIe maintainers,

Could you please help review and merge this patch? Thanks.

Best regards,
Hal

Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Bjorn Helgaas]

[+cc Kevin, pcie-starfive.c maintainer; will need his ack]

Subject line is excessively long.

On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> The "enable-gpio" property is not documented in the dt-bindings and
> using GPIO APIs is not a standard method to enable or disable PCIe
> slot power, so use regulator APIs to replace them.

I can't tell from this whether existing DTs will continue to work
after this change.  It looks like previously we looked for an
"enable-gpios" or "enable-gpio" property and now we'll look for a
"vpcie3v3-supply" regulator property.

I don't see "enable-gpios" or "enable-gpio" mentioned in any of the DT
patches in this series, so maybe that property was never actually used
before, and the code for pcie->power_gpio was actually dead?

Please add something here about how we know this won't break any
existing setups using DTs that are already in the field.

> Tested-by: Matthias Brugger <mbrugger@suse.com>
> Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")

Based on the cover letter, it looks like the point of this is to add
support for a new device, which I don't think really qualifies as a
"fix".

> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  drivers/pci/controller/plda/pcie-starfive.c | 25 ++++++++++++---------
>  1 file changed, 15 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
> index 3caf53c6c082..298036c3e7f9 100644
> --- a/drivers/pci/controller/plda/pcie-starfive.c
> +++ b/drivers/pci/controller/plda/pcie-starfive.c
> @@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
>  	struct reset_control *resets;
>  	struct clk_bulk_data *clks;
>  	struct regmap *reg_syscon;
> -	struct gpio_desc *power_gpio;
> +	struct regulator *vpcie3v3;
>  	struct gpio_desc *reset_gpio;
>  	struct phy *phy;
>  
> @@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie,
>  		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
>  				     "failed to get perst-gpio\n");
>  
> -	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> -						   GPIOD_OUT_LOW);
> -	if (IS_ERR(pcie->power_gpio))
> -		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> -				     "failed to get power-gpio\n");
> +	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> +	if (IS_ERR(pcie->vpcie3v3)) {
> +		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
> +			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
> +					     "failed to get vpcie3v3 regulator\n");
> +		pcie->vpcie3v3 = NULL;
> +	}
>  
>  	return 0;
>  }
> @@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct plda_pcie_rp *plda)
>  		container_of(plda, struct starfive_jh7110_pcie, plda);
>  
>  	starfive_pcie_clk_rst_deinit(pcie);
> -	if (pcie->power_gpio)
> -		gpiod_set_value_cansleep(pcie->power_gpio, 0);
> +	if (pcie->vpcie3v3)
> +		regulator_disable(pcie->vpcie3v3);
>  	starfive_pcie_disable_phy(pcie);
>  }
>  
> @@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct plda_pcie_rp *plda)
>  	if (ret)
>  		return ret;
>  
> -	if (pcie->power_gpio)
> -		gpiod_set_value_cansleep(pcie->power_gpio, 1);
> +	if (pcie->vpcie3v3) {
> +		ret = regulator_enable(pcie->vpcie3v3);
> +		if (ret)
> +			dev_err_probe(dev, ret, "failed to enable vpcie3v3 regulator\n");
> +	}
>  
>  	if (pcie->reset_gpio)
>  		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> -- 
> 2.43.2
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

回复: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Kevin Xie]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="gb2312", Size: 5073 bytes --]

> Krzysztof Kozlowski <krzk+dt@kernel.org>; Palmer Dabbelt
> <palmer@dabbelt.com>; Paul Walmsley <pjw@kernel.org>; Albert Ou
> <aou@eecs.berkeley.edu>; Rafael J . Wysocki <rafael@kernel.org>; Viresh
> Kumar <viresh.kumar@linaro.org>; Lorenzo Pieralisi <lpieralisi@kernel.org>;
> Krzysztof Wilczy¨½ski <kwilczynski@kernel.org>; Manivannan Sadhasivam
> <mani@kernel.org>; Bjorn Helgaas <bhelgaas@google.com>; Liam Girdwood
> <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Emil Renner
> Berthing <emil.renner.berthing@canonical.com>; Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>; E Shattow <e@freeshell.de>;
> devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Kevin Xie
> <kevin.xie@starfivetech.com>
> Ö÷Ìâ: Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs
> to enable the 3V3 power supply of PCIe slots
> 
> [+cc Kevin, pcie-starfive.c maintainer; will need his ack]
> 
> Subject line is excessively long.
> 
> On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> > The "enable-gpio" property is not documented in the dt-bindings and
> > using GPIO APIs is not a standard method to enable or disable PCIe
> > slot power, so use regulator APIs to replace them.
> 
> I can't tell from this whether existing DTs will continue to work after this
> change.  It looks like previously we looked for an "enable-gpios" or
> "enable-gpio" property and now we'll look for a "vpcie3v3-supply" regulator
> property.
> 
> I don't see "enable-gpios" or "enable-gpio" mentioned in any of the DT patches
> in this series, so maybe that property was never actually used before, and the
> code for pcie->power_gpio was actually dead?
> 

pcie->power_gpio is used in the our JH7110 EVB, it share the same pcie controller
driver with VisionFive2 board. Although JH7110 was not upstreamed, we still hope
to maintain the compatibility of the driver.

> Please add something here about how we know this won't break any existing
> setups using DTs that are already in the field.
> 
> > Tested-by: Matthias Brugger <mbrugger@suse.com>
> > Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")
> 
> Based on the cover letter, it looks like the point of this is to add support for a
> new device, which I don't think really qualifies as a "fix".
> 
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> >  drivers/pci/controller/plda/pcie-starfive.c | 25
> > ++++++++++++---------
> >  1 file changed, 15 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/pci/controller/plda/pcie-starfive.c
> > b/drivers/pci/controller/plda/pcie-starfive.c
> > index 3caf53c6c082..298036c3e7f9 100644
> > --- a/drivers/pci/controller/plda/pcie-starfive.c
> > +++ b/drivers/pci/controller/plda/pcie-starfive.c
> > @@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
> >  	struct reset_control *resets;
> >  	struct clk_bulk_data *clks;
> >  	struct regmap *reg_syscon;
> > -	struct gpio_desc *power_gpio;
> > +	struct regulator *vpcie3v3;
> >  	struct gpio_desc *reset_gpio;
> >  	struct phy *phy;
> >
> > @@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct
> starfive_jh7110_pcie *pcie,
> >  		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
> >  				     "failed to get perst-gpio\n");
> >
> > -	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> > -						   GPIOD_OUT_LOW);
> > -	if (IS_ERR(pcie->power_gpio))
> > -		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> > -				     "failed to get power-gpio\n");
> > +	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> > +	if (IS_ERR(pcie->vpcie3v3)) {
> > +		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
> > +			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
> > +					     "failed to get vpcie3v3 regulator\n");
> > +		pcie->vpcie3v3 = NULL;
> > +	}
> >
> >  	return 0;
> >  }
> > @@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct
> plda_pcie_rp *plda)
> >  		container_of(plda, struct starfive_jh7110_pcie, plda);
> >
> >  	starfive_pcie_clk_rst_deinit(pcie);
> > -	if (pcie->power_gpio)
> > -		gpiod_set_value_cansleep(pcie->power_gpio, 0);
> > +	if (pcie->vpcie3v3)
> > +		regulator_disable(pcie->vpcie3v3);
> >  	starfive_pcie_disable_phy(pcie);
> >  }
> >
> > @@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct
> plda_pcie_rp *plda)
> >  	if (ret)
> >  		return ret;
> >
> > -	if (pcie->power_gpio)
> > -		gpiod_set_value_cansleep(pcie->power_gpio, 1);
> > +	if (pcie->vpcie3v3) {
> > +		ret = regulator_enable(pcie->vpcie3v3);
> > +		if (ret)
> > +			dev_err_probe(dev, ret, "failed to enable vpcie3v3 regulator\n");
> > +	}
> >
> >  	if (pcie->reset_gpio)
> >  		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > --
> > 2.43.2
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Kevin Xie]

> Krzysztof Kozlowski <krzk+dt@kernel.org>; Palmer Dabbelt
> <palmer@dabbelt.com>; Paul Walmsley <pjw@kernel.org>; Albert Ou
> <aou@eecs.berkeley.edu>; Rafael J . Wysocki <rafael@kernel.org>; Viresh
> Kumar <viresh.kumar@linaro.org>; Lorenzo Pieralisi <lpieralisi@kernel.org>;
> Krzysztof Wilczyński <kwilczynski@kernel.org>; Manivannan Sadhasivam
> <mani@kernel.org>; Bjorn Helgaas <bhelgaas@google.com>; Liam Girdwood
> <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Emil Renner
> Berthing <emil.renner.berthing@canonical.com>; Heinrich Schuchardt
> <heinrich.schuchardt@canonical.com>; E Shattow <e@freeshell.de>;
> devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org
>Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO
> APIs to enable the 3V3 power supply of PCIe slots
> 
> > Krzysztof Kozlowski <krzk+dt@kernel.org>; Palmer Dabbelt
> > <palmer@dabbelt.com>; Paul Walmsley <pjw@kernel.org>; Albert Ou
> > <aou@eecs.berkeley.edu>; Rafael J . Wysocki <rafael@kernel.org>;
> > Viresh Kumar <viresh.kumar@linaro.org>; Lorenzo Pieralisi
> > <lpieralisi@kernel.org>; Krzysztof Wilczyński
> > <kwilczynski@kernel.org>; Manivannan Sadhasivam <mani@kernel.org>;
> > Bjorn Helgaas <bhelgaas@google.com>; Liam Girdwood
> > <lgirdwood@gmail.com>; Mark Brown <broonie@kernel.org>; Emil Renner
> > Berthing <emil.renner.berthing@canonical.com>; Heinrich Schuchardt
> > <heinrich.schuchardt@canonical.com>; E Shattow <e@freeshell.de>;
> > devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> > linux-riscv@lists.infradead.org; linux-kernel@vger.kernel.org; Kevin
> > Xie <kevin.xie@starfivetech.com>
> >Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of
> > GPIO APIs to enable the 3V3 power supply of PCIe slots
> >
> > [+cc Kevin, pcie-starfive.c maintainer; will need his ack]
> >
> > Subject line is excessively long.
> >
> > On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> > > The "enable-gpio" property is not documented in the dt-bindings and
> > > using GPIO APIs is not a standard method to enable or disable PCIe
> > > slot power, so use regulator APIs to replace them.
> >
> > I can't tell from this whether existing DTs will continue to work
> > after this change.  It looks like previously we looked for an
> > "enable-gpios" or "enable-gpio" property and now we'll look for a
> > "vpcie3v3-supply" regulator property.
> >
> > I don't see "enable-gpios" or "enable-gpio" mentioned in any of the DT
> > patches in this series, so maybe that property was never actually used
> > before, and the code for pcie->power_gpio was actually dead?
> >
> 
> pcie->power_gpio is used in the our JH7110 EVB, it share the same pcie
> pcie->controller
> driver with VisionFive2 board. Although JH7110 was not upstreamed, we still
> hope to maintain the compatibility of the driver.
> 

Sorry, I missed the background information regarding replacing enable_gpio with
regulator APIs. I agree with this change.

> > Please add something here about how we know this won't break any
> > existing setups using DTs that are already in the field.
> >
> > > Tested-by: Matthias Brugger <mbrugger@suse.com>
> > > Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")
> >
> > Based on the cover letter, it looks like the point of this is to add
> > support for a new device, which I don't think really qualifies as a "fix".
> >
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > >  drivers/pci/controller/plda/pcie-starfive.c | 25
> > > ++++++++++++---------
> > >  1 file changed, 15 insertions(+), 10 deletions(-)
> > >
> > > diff --git a/drivers/pci/controller/plda/pcie-starfive.c
> > > b/drivers/pci/controller/plda/pcie-starfive.c
> > > index 3caf53c6c082..298036c3e7f9 100644
> > > --- a/drivers/pci/controller/plda/pcie-starfive.c
> > > +++ b/drivers/pci/controller/plda/pcie-starfive.c
> > > @@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
> > >  	struct reset_control *resets;
> > >  	struct clk_bulk_data *clks;
> > >  	struct regmap *reg_syscon;
> > > -	struct gpio_desc *power_gpio;
> > > +	struct regulator *vpcie3v3;
> > >  	struct gpio_desc *reset_gpio;
> > >  	struct phy *phy;
> > >
> > > @@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct
> > starfive_jh7110_pcie *pcie,
> > >  		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
> > >  				     "failed to get perst-gpio\n");
> > >
> > > -	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> > > -						   GPIOD_OUT_LOW);
> > > -	if (IS_ERR(pcie->power_gpio))
> > > -		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> > > -				     "failed to get power-gpio\n");
> > > +	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> > > +	if (IS_ERR(pcie->vpcie3v3)) {
> > > +		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
> > > +			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
> > > +					     "failed to get vpcie3v3 regulator\n");
> > > +		pcie->vpcie3v3 = NULL;
> > > +	}
> > >
> > >  	return 0;
> > >  }
> > > @@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct
> > plda_pcie_rp *plda)
> > >  		container_of(plda, struct starfive_jh7110_pcie, plda);
> > >
> > >  	starfive_pcie_clk_rst_deinit(pcie);
> > > -	if (pcie->power_gpio)
> > > -		gpiod_set_value_cansleep(pcie->power_gpio, 0);
> > > +	if (pcie->vpcie3v3)
> > > +		regulator_disable(pcie->vpcie3v3);
> > >  	starfive_pcie_disable_phy(pcie);
> > >  }
> > >
> > > @@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct
> > plda_pcie_rp *plda)
> > >  	if (ret)
> > >  		return ret;
> > >
> > > -	if (pcie->power_gpio)
> > > -		gpiod_set_value_cansleep(pcie->power_gpio, 1);
> > > +	if (pcie->vpcie3v3) {
> > > +		ret = regulator_enable(pcie->vpcie3v3);
> > > +		if (ret)
> > > +			dev_err_probe(dev, ret, "failed to enable vpcie3v3 regulator\n");
> > > +	}
> > >
> > >  	if (pcie->reset_gpio)
> > >  		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > > --
> > > 2.43.2
> > >
> > >
> > > _______________________________________________
> > > linux-riscv mailing list
> > > linux-riscv@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Kevin Xie]

> > >Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of  GPIO
> > >APIs to enable the 3V3 power supply of PCIe slots
> > >
> > > [+cc Kevin, pcie-starfive.c maintainer; will need his ack]
> > >
> > > Subject line is excessively long.
> > >
> > > On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> > > > The "enable-gpio" property is not documented in the dt-bindings
> > > > and using GPIO APIs is not a standard method to enable or disable
> > > > PCIe slot power, so use regulator APIs to replace them.
> > >
> > > I can't tell from this whether existing DTs will continue to work
> > > after this change.  It looks like previously we looked for an
> > > "enable-gpios" or "enable-gpio" property and now we'll look for a
> > > "vpcie3v3-supply" regulator property.
> > >
> > > I don't see "enable-gpios" or "enable-gpio" mentioned in any of the
> > > DT patches in this series, so maybe that property was never actually
> > > used before, and the code for pcie->power_gpio was actually dead?
> > >
> >
> > pcie->power_gpio is used in the our JH7110 EVB, it share the same pcie
> > pcie->controller
> > driver with VisionFive2 board. Although JH7110 was not upstreamed, we
> > still hope to maintain the compatibility of the driver.
> >
> 
> Sorry, I missed the background information regarding replacing enable_gpio
> with regulator APIs. I agree with this change.
> 
> > > Please add something here about how we know this won't break any
> > > existing setups using DTs that are already in the field.
> > >
> > > > Tested-by: Matthias Brugger <mbrugger@suse.com>
> > > > Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")
> > >
> > > Based on the cover letter, it looks like the point of this is to add
> > > support for a new device, which I don't think really qualifies as a "fix".
> > >
> > > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>

Acked-by: Kevin Xie <kevin.xie@starfivetech.com>

> > > > ---
> > > >  drivers/pci/controller/plda/pcie-starfive.c | 25
> > > > ++++++++++++---------
> > > >  1 file changed, 15 insertions(+), 10 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/plda/pcie-starfive.c
> > > > b/drivers/pci/controller/plda/pcie-starfive.c
> > > > index 3caf53c6c082..298036c3e7f9 100644
> > > > --- a/drivers/pci/controller/plda/pcie-starfive.c
> > > > +++ b/drivers/pci/controller/plda/pcie-starfive.c
> > > > @@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
> > > >  	struct reset_control *resets;
> > > >  	struct clk_bulk_data *clks;
> > > >  	struct regmap *reg_syscon;
> > > > -	struct gpio_desc *power_gpio;
> > > > +	struct regulator *vpcie3v3;
> > > >  	struct gpio_desc *reset_gpio;
> > > >  	struct phy *phy;
> > > >
> > > > @@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct
> > > starfive_jh7110_pcie *pcie,
> > > >  		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
> > > >  				     "failed to get perst-gpio\n");
> > > >
> > > > -	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> > > > -						   GPIOD_OUT_LOW);
> > > > -	if (IS_ERR(pcie->power_gpio))
> > > > -		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> > > > -				     "failed to get power-gpio\n");
> > > > +	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> > > > +	if (IS_ERR(pcie->vpcie3v3)) {
> > > > +		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
> > > > +			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
> > > > +					     "failed to get vpcie3v3 regulator\n");
> > > > +		pcie->vpcie3v3 = NULL;
> > > > +	}
> > > >
> > > >  	return 0;
> > > >  }
> > > > @@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct
> > > plda_pcie_rp *plda)
> > > >  		container_of(plda, struct starfive_jh7110_pcie, plda);
> > > >
> > > >  	starfive_pcie_clk_rst_deinit(pcie);
> > > > -	if (pcie->power_gpio)
> > > > -		gpiod_set_value_cansleep(pcie->power_gpio, 0);
> > > > +	if (pcie->vpcie3v3)
> > > > +		regulator_disable(pcie->vpcie3v3);
> > > >  	starfive_pcie_disable_phy(pcie);  }
> > > >
> > > > @@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct
> > > plda_pcie_rp *plda)
> > > >  	if (ret)
> > > >  		return ret;
> > > >
> > > > -	if (pcie->power_gpio)
> > > > -		gpiod_set_value_cansleep(pcie->power_gpio, 1);
> > > > +	if (pcie->vpcie3v3) {
> > > > +		ret = regulator_enable(pcie->vpcie3v3);
> > > > +		if (ret)
> > > > +			dev_err_probe(dev, ret, "failed to enable vpcie3v3
> regulator\n");
> > > > +	}
> > > >
> > > >  	if (pcie->reset_gpio)
> > > >  		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > > > --
> > > > 2.43.2
> > > >
> > > >
> > > > _______________________________________________
> > > > linux-riscv mailing list
> > > > linux-riscv@lists.infradead.org
> > > > http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Bjorn Helgaas]

On Tue, Dec 02, 2025 at 03:02:48AM +0000, Kevin Xie wrote:
> ...

> > > On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> > > > The "enable-gpio" property is not documented in the dt-bindings and
> > > > using GPIO APIs is not a standard method to enable or disable PCIe
> > > > slot power, so use regulator APIs to replace them.
> > >
> > > I can't tell from this whether existing DTs will continue to work
> > > after this change.  It looks like previously we looked for an
> > > "enable-gpios" or "enable-gpio" property and now we'll look for a
> > > "vpcie3v3-supply" regulator property.
> > >
> > > I don't see "enable-gpios" or "enable-gpio" mentioned in any of the DT
> > > patches in this series, so maybe that property was never actually used
> > > before, and the code for pcie->power_gpio was actually dead?
> > 
> > pcie->power_gpio is used in the our JH7110 EVB, it share the same
> > pcie pcie->controller driver with VisionFive2 board. Although
> > JH7110 was not upstreamed, we still hope to maintain the
> > compatibility of the driver.
> 
> Sorry, I missed the background information regarding replacing
> enable_gpio with regulator APIs. I agree with this change.

OK, thanks.  I would still like to have something added to the commit
log to the effect that this change will break any DTs that use
"enable-gpios" or "enable-gpio", but that's not a problem because such
DTs were only internal to StarFive and we are OK with updating them
and dealing with the fact that the DT is rev-locked with the kernel
version (old kernels would require an old DT with "enable-gpio" and
new kernels require an updated DT with "vpcie3v3-supply").  Or DTs
using "enable-gpio" never existed in the first place.

Or whatever.  I just want the commit log to be clear that
"enable-gpio" is no longer supported and "vpcie3v3-supply" must be
included instead, AND that you are aware of the breaking nature of the
change and here is why that's not an issue.

We can't make kernel changes that require end users to upgrade the DT
when they update the kernel or downgrade the DT when rolling back.

Bjorn

RE: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Hal Feng]

> On 03.12.25 00:31, Bjorn Helgaas wrote:
> On Tue, Dec 02, 2025 at 03:02:48AM +0000, Kevin Xie wrote:
> > ...
> 
> > > > On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> > > > > The "enable-gpio" property is not documented in the dt-bindings
> > > > > and using GPIO APIs is not a standard method to enable or
> > > > > disable PCIe slot power, so use regulator APIs to replace them.
> > > >
> > > > I can't tell from this whether existing DTs will continue to work
> > > > after this change.  It looks like previously we looked for an
> > > > "enable-gpios" or "enable-gpio" property and now we'll look for a
> > > > "vpcie3v3-supply" regulator property.
> > > >
> > > > I don't see "enable-gpios" or "enable-gpio" mentioned in any of
> > > > the DT patches in this series, so maybe that property was never
> > > > actually used before, and the code for pcie->power_gpio was actually
> dead?
> > >
> > > pcie->power_gpio is used in the our JH7110 EVB, it share the same
> > > pcie pcie->controller driver with VisionFive2 board. Although
> > > JH7110 was not upstreamed, we still hope to maintain the
> > > compatibility of the driver.
> >
> > Sorry, I missed the background information regarding replacing
> > enable_gpio with regulator APIs. I agree with this change.
> 
> OK, thanks.  I would still like to have something added to the commit log to the
> effect that this change will break any DTs that use "enable-gpios" or "enable-
> gpio", but that's not a problem because such DTs were only internal to StarFive
> and we are OK with updating them and dealing with the fact that the DT is rev-
> locked with the kernel version (old kernels would require an old DT with
> "enable-gpio" and new kernels require an updated DT with "vpcie3v3-
> supply").  Or DTs using "enable-gpio" never existed in the first place.
> 
> Or whatever.  I just want the commit log to be clear that "enable-gpio" is no
> longer supported and "vpcie3v3-supply" must be included instead, AND that
> you are aware of the breaking nature of the change and here is why that's not
> an issue.

OK. I send another patch [1] today and add the some description to the commit
log accordingly. Please check it. Thanks for your review.

[1] https://lore.kernel.org/all/20251204064956.118747-1-hal.feng@starfivetech.com/

Best regards,
Hal

> 
> We can't make kernel changes that require end users to upgrade the DT when
> they update the kernel or downgrade the DT when rolling back.
> 
> Bjorn

RE: [PATCH v4 1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots

[Hal Feng]

> On 02.12.25 04:53, Bjorn Helgaas wrote:
> [+cc Kevin, pcie-starfive.c maintainer; will need his ack]
> 
> Subject line is excessively long.
> 
> On Tue, Nov 25, 2025 at 03:55:59PM +0800, Hal Feng wrote:
> > The "enable-gpio" property is not documented in the dt-bindings and
> > using GPIO APIs is not a standard method to enable or disable PCIe
> > slot power, so use regulator APIs to replace them.
> 
> I can't tell from this whether existing DTs will continue to work after this
> change.  It looks like previously we looked for an "enable-gpios" or "enable-
> gpio" property and now we'll look for a "vpcie3v3-supply" regulator property.
> 
> I don't see "enable-gpios" or "enable-gpio" mentioned in any of the DT
> patches in this series, so maybe that property was never actually used before,
> and the code for pcie->power_gpio was actually dead?

Yes, "enable-gpios" or "enable-gpio" is never used in any DTs, and pcie->power_gpio
related code is never run actually. Even the "enable-gpios" or "enable-gpio"
property was not added in the dt-bindings
Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml.

Suggested by Manivannan in the previous version [1], let's use regulator APIs instead.

[1] https://lore.kernel.org/all/xxswzi4v6gpuqbe3cczj2yjmprhvln26fl5ligsp5vkiogrnwk@hpifxivaps6j/

Best regards,
Hal

> 
> Please add something here about how we know this won't break any existing
> setups using DTs that are already in the field.
> 
> > Tested-by: Matthias Brugger <mbrugger@suse.com>
> > Fixes: 39b91eb40c6a ("PCI: starfive: Add JH7110 PCIe controller")
> 
> Based on the cover letter, it looks like the point of this is to add support for a
> new device, which I don't think really qualifies as a "fix".
> 
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> >  drivers/pci/controller/plda/pcie-starfive.c | 25
> > ++++++++++++---------
> >  1 file changed, 15 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/pci/controller/plda/pcie-starfive.c
> > b/drivers/pci/controller/plda/pcie-starfive.c
> > index 3caf53c6c082..298036c3e7f9 100644
> > --- a/drivers/pci/controller/plda/pcie-starfive.c
> > +++ b/drivers/pci/controller/plda/pcie-starfive.c
> > @@ -55,7 +55,7 @@ struct starfive_jh7110_pcie {
> >  	struct reset_control *resets;
> >  	struct clk_bulk_data *clks;
> >  	struct regmap *reg_syscon;
> > -	struct gpio_desc *power_gpio;
> > +	struct regulator *vpcie3v3;
> >  	struct gpio_desc *reset_gpio;
> >  	struct phy *phy;
> >
> > @@ -153,11 +153,13 @@ static int starfive_pcie_parse_dt(struct
> starfive_jh7110_pcie *pcie,
> >  		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
> >  				     "failed to get perst-gpio\n");
> >
> > -	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> > -						   GPIOD_OUT_LOW);
> > -	if (IS_ERR(pcie->power_gpio))
> > -		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> > -				     "failed to get power-gpio\n");
> > +	pcie->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
> > +	if (IS_ERR(pcie->vpcie3v3)) {
> > +		if (PTR_ERR(pcie->vpcie3v3) != -ENODEV)
> > +			return dev_err_probe(dev, PTR_ERR(pcie->vpcie3v3),
> > +					     "failed to get vpcie3v3
> regulator\n");
> > +		pcie->vpcie3v3 = NULL;
> > +	}
> >
> >  	return 0;
> >  }
> > @@ -270,8 +272,8 @@ static void starfive_pcie_host_deinit(struct
> plda_pcie_rp *plda)
> >  		container_of(plda, struct starfive_jh7110_pcie, plda);
> >
> >  	starfive_pcie_clk_rst_deinit(pcie);
> > -	if (pcie->power_gpio)
> > -		gpiod_set_value_cansleep(pcie->power_gpio, 0);
> > +	if (pcie->vpcie3v3)
> > +		regulator_disable(pcie->vpcie3v3);
> >  	starfive_pcie_disable_phy(pcie);
> >  }
> >
> > @@ -304,8 +306,11 @@ static int starfive_pcie_host_init(struct
> plda_pcie_rp *plda)
> >  	if (ret)
> >  		return ret;
> >
> > -	if (pcie->power_gpio)
> > -		gpiod_set_value_cansleep(pcie->power_gpio, 1);
> > +	if (pcie->vpcie3v3) {
> > +		ret = regulator_enable(pcie->vpcie3v3);
> > +		if (ret)
> > +			dev_err_probe(dev, ret, "failed to enable vpcie3v3
> regulator\n");
> > +	}
> >
> >  	if (pcie->reset_gpio)
> >  		gpiod_set_value_cansleep(pcie->reset_gpio, 1);
> > --
> > 2.43.2
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

[PATCH v4 2/6] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board

[Hal Feng]

Add device tree bindings for the StarFive JH7110S SoC
and the VisionFive 2 Lite board equipped with it.

JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
and up to 1.25GHz. Its CPU cores and peripherals are the same as
those of the JH7110 SoC.

VisionFive 2 Lite boards have MicroSD card version (default) and eMMC
version, which are called "VisionFive 2 Lite" and "VisionFive 2 Lite eMMC"
respectively.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 Documentation/devicetree/bindings/riscv/starfive.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
index 04510341a71e..797d9956b949 100644
--- a/Documentation/devicetree/bindings/riscv/starfive.yaml
+++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
@@ -35,6 +35,12 @@ properties:
               - starfive,visionfive-2-v1.3b
           - const: starfive,jh7110
 
+      - items:
+          - enum:
+              - starfive,visionfive-2-lite
+              - starfive,visionfive-2-lite-emmc
+          - const: starfive,jh7110s
+
 additionalProperties: true
 
 ...
-- 
2.43.2

[PATCH v4 3/6] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts

[Hal Feng]

Some node in this file are not used by the upcoming VisionFive 2 Lite
board. Move them to the board dts to prepare for adding the new
VisionFive 2 Lite device tree.

Tested-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110-common.dtsi    |  8 --------
 .../dts/starfive/jh7110-deepcomputing-fml13v01.dts | 14 ++++++++++++++
 arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts | 14 ++++++++++++++
 .../boot/dts/starfive/jh7110-milkv-marscm-emmc.dts |  9 +++++++++
 .../boot/dts/starfive/jh7110-milkv-marscm-lite.dts |  1 +
 .../boot/dts/starfive/jh7110-pine64-star64.dts     | 14 ++++++++++++++
 .../dts/starfive/jh7110-starfive-visionfive-2.dtsi | 11 +++++++++++
 7 files changed, 63 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 083ec80b4e44..8cfe8033305d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -281,14 +281,8 @@ &mmc0 {
 	assigned-clock-rates = <50000000>;
 	bus-width = <8>;
 	bootph-pre-ram;
-	cap-mmc-highspeed;
-	mmc-ddr-1_8v;
-	mmc-hs200-1_8v;
-	cap-mmc-hw-reset;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc0_pins>;
-	vmmc-supply = <&vcc_3v3>;
-	vqmmc-supply = <&emmc_vdd>;
 	status = "okay";
 };
 
@@ -298,8 +292,6 @@ &mmc1 {
 	assigned-clock-rates = <50000000>;
 	bus-width = <4>;
 	bootph-pre-ram;
-	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
-	disable-wp;
 	cap-sd-highspeed;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mmc1_pins>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
index 0243e54a84ed..d8db9ed4474d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
@@ -11,6 +11,15 @@ / {
 	compatible = "deepcomputing,fml13v01", "starfive,jh7110";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
 &mmc0_pins {
 	 rst-pins {
 		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
@@ -24,6 +33,11 @@ GPOEN_ENABLE,
 	};
 };
 
+&mmc1 {
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
 &pcie1 {
 	perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
 	phys = <&pciephy1>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
index 5ca10597dcd9..21873612d993 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
@@ -22,6 +22,15 @@ &i2c0 {
 	status = "okay";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
 &mmc0_pins {
 	 rst-pins {
 		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
@@ -35,6 +44,11 @@ GPOEN_ENABLE,
 	};
 };
 
+&mmc1 {
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
 &pcie0 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
index e568537af2c4..ce95496263af 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-emmc.dts
@@ -10,3 +10,12 @@ / {
 	model = "Milk-V Mars CM";
 	compatible = "milkv,marscm-emmc", "starfive,jh7110";
 };
+
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
index 6c40d0ec4011..63aa94d65ab5 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
@@ -14,6 +14,7 @@ / {
 &mmc0 {
 	bus-width = <4>;
 	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
 };
 
 &mmc0_pins {
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
index 980e24e3dbc8..aec7ae3d1f5b 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
@@ -44,6 +44,15 @@ &i2c0 {
 	status = "okay";
 };
 
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
+
 &mmc0_pins {
 	 rst-pins {
 		pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
@@ -57,6 +66,11 @@ GPOEN_ENABLE,
 	};
 };
 
+&mmc1 {
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
 &pcie1 {
 	status = "okay";
 };
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 574e128138c2..edc8f4588133 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -38,6 +38,12 @@ &i2c0 {
 };
 
 &mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
 	non-removable;
 };
 
@@ -54,6 +60,11 @@ GPOEN_ENABLE,
 	};
 };
 
+&mmc1 {
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	disable-wp;
+};
+
 &pcie0 {
 	status = "okay";
 };
-- 
2.43.2

[PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[Hal Feng]

Add a common board dtsi for use by VisionFive 2 Lite and
VisionFive 2 Lite eMMC.

Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
 1 file changed, 161 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
new file mode 100644
index 000000000000..f8797a666dbf
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-common.dtsi"
+
+/ {
+	vcc_3v3_pcie: regulator-vcc-3v3-pcie {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc_3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&cpu_opp {
+	/delete-node/ opp-375000000;
+	/delete-node/ opp-500000000;
+	/delete-node/ opp-750000000;
+	/delete-node/ opp-1500000000;
+
+	opp-312500000 {
+		opp-hz = /bits/ 64 <312500000>;
+		opp-microvolt = <800000>;
+	};
+	opp-417000000 {
+		opp-hz = /bits/ 64 <417000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-625000000 {
+		opp-hz = /bits/ 64 <625000000>;
+		opp-microvolt = <800000>;
+	};
+	opp-1250000000 {
+		opp-hz = /bits/ 64 <1250000000>;
+		opp-microvolt = <1000000>;
+	};
+};
+
+&gmac0 {
+	starfive,tx-use-rgmii-clk;
+	assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
+	assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&mmc1 {
+	max-frequency = <50000000>;
+	keep-power-in-suspend;
+	non-removable;
+};
+
+&pcie1 {
+	vpcie3v3-supply = <&vcc_3v3_pcie>;
+	status = "okay";
+};
+
+&phy0 {
+	motorcomm,tx-clk-adj-enabled;
+	motorcomm,tx-clk-100-inverted;
+	motorcomm,tx-clk-1000-inverted;
+	motorcomm,rx-clk-drv-microamp = <3970>;
+	motorcomm,rx-data-drv-microamp = <2910>;
+	rx-internal-delay-ps = <1500>;
+	tx-internal-delay-ps = <1500>;
+};
+
+&pwm {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&syscrg {
+	assigned-clock-rates = <0>, <0>, <0>, <0>, <500000000>, <1250000000>;
+};
+
+&sysgpio {
+	uart1_pins: uart1-0 {
+		tx-pins {
+			pinmux = <GPIOMUX(22, GPOUT_SYS_UART1_TX,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			bias-disable;
+			drive-strength = <12>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+
+		rx-pins {
+			pinmux = <GPIOMUX(23, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_RX)>;
+			bias-pull-up;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-enable;
+			slew-rate = <0>;
+		};
+
+		cts-pins {
+			pinmux = <GPIOMUX(24, GPOUT_LOW,
+					      GPOEN_DISABLE,
+					      GPI_SYS_UART1_CTS)>;
+			input-enable;
+		};
+
+		rts-pins {
+			pinmux = <GPIOMUX(25, GPOUT_SYS_UART1_RTS,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-enable;
+		};
+	};
+
+	usb0_pins: usb0-0 {
+		power-pins {
+			pinmux = <GPIOMUX(26, GPOUT_HIGH,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+
+		switch-pins {
+			pinmux = <GPIOMUX(62, GPOUT_LOW,
+					      GPOEN_ENABLE,
+					      GPI_NONE)>;
+			input-disable;
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "host";
+	pinctrl-names = "default";
+	pinctrl-0 = <&usb0_pins>;
+	status = "okay";
+};
+
+&usb_cdns3 {
+	phys = <&usbphy0>, <&pciephy0>;
+	phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy";
+};
-- 
2.43.2

Re: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[Anand Moon]

Hi Hal,

On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> Add a common board dtsi for use by VisionFive 2 Lite and
> VisionFive 2 Lite eMMC.
>
> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Tested-by: Matthias Brugger <mbrugger@suse.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
>  1 file changed, 161 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> new file mode 100644
> index 000000000000..f8797a666dbf
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-common.dtsi"
> +
> +/ {
> +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
> +               compatible = "regulator-fixed";
> +               enable-active-high;
> +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> +               regulator-name = "vcc_3v3_pcie";
> +               regulator-min-microvolt = <3300000>;
> +               regulator-max-microvolt = <3300000>;
> +       };
> +};

The vcc_3v3_pcie regulator node is common to all JH7110 development boards.
and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).

VisionFive 2 Product Design Schematics below
[1] https://doc-en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf

Mars_Hardware_Schematics
[2] https://github.com/milkv-mars/mars-files/blob/main/Mars_Hardware_Schematics/Milk-V_Mars_SCH_V1.21_2024-0510.pdf

Thanks
-Anand

Re: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[Maud Spierings]

> 
> Hi Hal,
> 
> On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng@starfivetech.com> wrote:
>>
>> Add a common board dtsi for use by VisionFive 2 Lite and
>> VisionFive 2 Lite eMMC.
>>
>> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>> Tested-by: Matthias Brugger <mbrugger@suse.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>>  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
>>  1 file changed, 161 insertions(+)
>>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
>> new file mode 100644
>> index 000000000000..f8797a666dbf
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
>> @@ -0,0 +1,161 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-common.dtsi"
>> +
>> +/ {
>> +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
>> +               compatible = "regulator-fixed";
>> +               enable-active-high;
>> +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
>> +               regulator-name = "vcc_3v3_pcie";
>> +               regulator-min-microvolt = <3300000>;
>> +               regulator-max-microvolt = <3300000>;
>> +       };
>> +};
> 
> The vcc_3v3_pcie regulator node is common to all JH7110 development boards.
> and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).
> 
> VisionFive 2 Product Design Schematics below
> [1] https://doc-en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf
> 
> Mars_Hardware_Schematics
> [2] https://github.com/milkv-mars/mars-files/blob/main/Mars_Hardware_Schematics/Milk-V_Mars_SCH_V1.21_2024-0510.pdf
> 

I'm not sure if this also holds true for the deepcomputing fml13v01, 
sadly as far as I know there is no schematics available for that.

the downstream dts [3] doesn't contain any evidence of it, neither does 
upstream.

I wouldn't be surprised if it is there but just not present in the dts, 
but it may be nice to get some feedback from someone at deepcomputing.

adding Sandie Cao who did some of the upstreaming work.

Link: 
https://github.com/DC-DeepComputing/fml13v01-linux/blob/97c64fe2832b6826914b6da7aa4febcdd4d3d444/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts#L416-L432 
[3]

kind regards,
Maud

Re: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[E Shattow]

On 12/4/25 23:23, Maud Spierings wrote:
>>
>> Hi Hal,
>>
>> On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng@starfivetech.com> wrote:
>>>
>>> Add a common board dtsi for use by VisionFive 2 Lite and
>>> VisionFive 2 Lite eMMC.
>>>
>>> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
>>> Tested-by: Matthias Brugger <mbrugger@suse.com>
>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>> ---
>>>  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
>>>  1 file changed, 161 insertions(+)
>>>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-
>>> visionfive-2-lite.dtsi
>>>
>>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-
>>> visionfive-2-lite.dtsi b/arch/riscv/boot/dts/starfive/jh7110-
>>> starfive-visionfive-2-lite.dtsi
>>> new file mode 100644
>>> index 000000000000..f8797a666dbf
>>> --- /dev/null
>>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-
>>> lite.dtsi
>>> @@ -0,0 +1,161 @@
>>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>>> +/*
>>> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
>>> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
>>> + */
>>> +
>>> +/dts-v1/;
>>> +#include "jh7110-common.dtsi"
>>> +
>>> +/ {
>>> +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
>>> +               compatible = "regulator-fixed";
>>> +               enable-active-high;
>>> +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
>>> +               regulator-name = "vcc_3v3_pcie";
>>> +               regulator-min-microvolt = <3300000>;
>>> +               regulator-max-microvolt = <3300000>;
>>> +       };
>>> +};
>>
>> The vcc_3v3_pcie regulator node is common to all JH7110 development
>> boards.
>> and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).
>>
>> VisionFive 2 Product Design Schematics below
>> [1] https://doc-en.rvspace.org/VisionFive2/PDF/
>> SCH_RV002_V1.2A_20221216.pdf
>>
>> Mars_Hardware_Schematics
>> [2] https://github.com/milkv-mars/mars-files/blob/main/
>> Mars_Hardware_Schematics/Milk-V_Mars_SCH_V1.21_2024-0510.pdf
>>
> 
> I'm not sure if this also holds true for the deepcomputing fml13v01,
> sadly as far as I know there is no schematics available for that.
> 
> the downstream dts [3] doesn't contain any evidence of it, neither does
> upstream.
> 
> I wouldn't be surprised if it is there but just not present in the dts,
> but it may be nice to get some feedback from someone at deepcomputing.
> 
> adding Sandie Cao who did some of the upstreaming work.
> 
> Link: https://github.com/DC-DeepComputing/fml13v01-linux/
> blob/97c64fe2832b6826914b6da7aa4febcdd4d3d444/arch/riscv/boot/dts/
> starfive/jh7110-deepcomputing-fml13v01.dts#L416-L432 [3]
> 
> kind regards,
> Maud
> 

I asked (to DeepComputing sales e-mail address) for schematics 28th July
2025, the reply was "There is no plan to public it by now." I also got
some generic response when I asked a technical question about RGPIO3
connection to look at the DeepComputing repo on github.

No schematics and no help to developers.

-E

RE: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[Hal Feng]

> On 05.12.25 01:05, Anand Moon wrote:
> Hi Hal,
> 
> On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng@starfivetech.com> wrote:
> >
> > Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2
> > Lite eMMC.
> >
> > Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > Tested-by: Matthias Brugger <mbrugger@suse.com>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > ---
> >  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
> >  1 file changed, 161 insertions(+)
> >  create mode 100644
> > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> >
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > new file mode 100644
> > index 000000000000..f8797a666dbf
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.d
> > +++ tsi
> > @@ -0,0 +1,161 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > +/*
> > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>  */
> > +
> > +/dts-v1/;
> > +#include "jh7110-common.dtsi"
> > +
> > +/ {
> > +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
> > +               compatible = "regulator-fixed";
> > +               enable-active-high;
> > +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> > +               regulator-name = "vcc_3v3_pcie";
> > +               regulator-min-microvolt = <3300000>;
> > +               regulator-max-microvolt = <3300000>;
> > +       };
> > +};
> 
> The vcc_3v3_pcie regulator node is common to all JH7110 development
> boards.
> and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).
> 
> VisionFive 2 Product Design Schematics below [1] https://doc-
> en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf
> 
> Mars_Hardware_Schematics
> [2] https://github.com/milkv-mars/mars-
> files/blob/main/Mars_Hardware_Schematics/Milk-
> V_Mars_SCH_V1.21_2024-0510.pdf

No, GPIO32 is connected to the WAKE pin, it is not used to control the PCIe slot power.

Best regards,
Hal

Re: [PATCH v4 4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants

[Anand Moon]

Hi Hal,

On Fri, 5 Dec 2025 at 13:11, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> > On 05.12.25 01:05, Anand Moon wrote:
> > Hi Hal,
> >
> > On Tue, 25 Nov 2025 at 13:27, Hal Feng <hal.feng@starfivetech.com> wrote:
> > >
> > > Add a common board dtsi for use by VisionFive 2 Lite and VisionFive 2
> > > Lite eMMC.
> > >
> > > Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > > Tested-by: Matthias Brugger <mbrugger@suse.com>
> > > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > > ---
> > >  .../jh7110-starfive-visionfive-2-lite.dtsi    | 161 ++++++++++++++++++
> > >  1 file changed, 161 insertions(+)
> > >  create mode 100644
> > > arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > >
> > > diff --git
> > > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi
> > > new file mode 100644
> > > index 000000000000..f8797a666dbf
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.d
> > > +++ tsi
> > > @@ -0,0 +1,161 @@
> > > +// SPDX-License-Identifier: GPL-2.0 OR MIT
> > > +/*
> > > + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> > > + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>  */
> > > +
> > > +/dts-v1/;
> > > +#include "jh7110-common.dtsi"
> > > +
> > > +/ {
> > > +       vcc_3v3_pcie: regulator-vcc-3v3-pcie {
> > > +               compatible = "regulator-fixed";
> > > +               enable-active-high;
> > > +               gpio = <&sysgpio 27 GPIO_ACTIVE_HIGH>;
> > > +               regulator-name = "vcc_3v3_pcie";
> > > +               regulator-min-microvolt = <3300000>;
> > > +               regulator-max-microvolt = <3300000>;
> > > +       };
> > > +};
> >
> > The vcc_3v3_pcie regulator node is common to all JH7110 development
> > boards.
> > and it is enabled through the PWREN_H signal (PCIE0_PWREN_H_GPIO32).
> >
> > VisionFive 2 Product Design Schematics below [1] https://doc-
> > en.rvspace.org/VisionFive2/PDF/SCH_RV002_V1.2A_20221216.pdf
> >
> > Mars_Hardware_Schematics
> > [2] https://github.com/milkv-mars/mars-
> > files/blob/main/Mars_Hardware_Schematics/Milk-
> > V_Mars_SCH_V1.21_2024-0510.pdf
>
> No, GPIO32 is connected to the WAKE pin, it is not used to control the PCIe slot power.
>
Ok, GPIO32 is used for pcie0 (PCIE0_PWREN_H_GPIO32)
Only PCIE0 supports power for the 4-port USB ports.

As per VisionFive 2 Single Board Computer Quick Start Guide
USB30 4 × USB 3.0 ports (multiplexed with a PCIe 2.0 1x lane).

> Best regards,
> Hal

Thanks
-Anand

[PATCH v4 5/6] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[Hal Feng]

VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.

Board features:
- JH7110S SoC
- 4/8 GiB LPDDR4 DRAM
- AXP15060 PMIC
- 40 pin GPIO header
- 1x USB 3.0 host port
- 3x USB 2.0 host port
- 1x M.2 M-Key (size: 2242)
- 1x MicroSD slot (optional non-removable 64GiB eMMC)
- 1x QSPI Flash
- 1x I2C EEPROM
- 1x 1Gbps Ethernet port
- SDIO-based Wi-Fi & UART-based Bluetooth
- 1x HDMI port
- 1x 2-lane DSI
- 1x 2-lane CSI

VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html

Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |  1 +
 .../jh7110-starfive-visionfive-2-lite.dts     | 20 +++++++++++++++++++
 2 files changed, 21 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 62b659f89ba7..2b1e7fcd6f84 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
new file mode 100644
index 000000000000..b96eea4fa7d5
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2-lite.dtsi"
+
+/ {
+	model = "StarFive VisionFive 2 Lite";
+	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";
+};
+
+&mmc0 {
+	bus-width = <4>;
+	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
+	disable-wp;
+	cap-sd-highspeed;
+};
-- 
2.43.2

Re: [PATCH v4 5/6] riscv: dts: starfive: Add VisionFive 2 Lite board device tree

[E Shattow]

On 11/24/25 23:56, Hal Feng wrote:
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S SoC.
> 
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
> 
> VisionFive 2 Lite schematics: https://doc-en.rvspace.org/VisionFive2Lite/PDF/VF2_LITE_V1.10_TF_20250818_SCH.pdf
> VisionFive 2 Lite Quick Start Guide: https://doc-en.rvspace.org/VisionFive2Lite/VisionFive2LiteQSG/index.html
> More documents: https://doc-en.rvspace.org/Doc_Center/visionfive_2_lite.html
> 
> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Tested-by: Matthias Brugger <mbrugger@suse.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/Makefile         |  1 +
>  .../jh7110-starfive-visionfive-2-lite.dts     | 20 +++++++++++++++++++
>  2 files changed, 21 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
> 
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 62b659f89ba7..2b1e7fcd6f84 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -13,5 +13,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-mars.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
> +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
> new file mode 100644
> index 000000000000..b96eea4fa7d5
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dts
> @@ -0,0 +1,20 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2-lite.dtsi"
> +
> +/ {
> +	model = "StarFive VisionFive 2 Lite";

> +	compatible = "starfive,visionfive-2-lite", "starfive,jh7110s";

Add "starfive,jh7110" to the compatible list as the least-compatible
(left-to-right order last item):

compatible = "starfive,visionfive-2-lite", "starfive,jh7110s",
"starfive,jh7110";

or if there is review feedback that no new compatible should be added,
then as usual for new JH-7110 boards:

compatible = "starfive,visionfive-2-lite", "starfive,jh7110";

> +};
> +
> +&mmc0 {
> +	bus-width = <4>;
> +	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_HIGH>;
> +	disable-wp;
> +	cap-sd-highspeed;
> +};

-E

[PATCH v4 6/6] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree

[Hal Feng]

VisionFive 2 Lite eMMC board uses a non-removable onboard 64GiB eMMC
instead of the MicroSD slot.

Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Tested-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/Makefile         |  1 +
 ...jh7110-starfive-visionfive-2-lite-emmc.dts | 22 +++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts

diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 2b1e7fcd6f84..a640ed5dc5a1 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
+dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
 dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
new file mode 100644
index 000000000000..e27a662d4022
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2025 StarFive Technology Co., Ltd.
+ * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2-lite.dtsi"
+
+/ {
+	model = "StarFive VisionFive 2 Lite eMMC";
+	compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s";
+};
+
+&mmc0 {
+	cap-mmc-highspeed;
+	cap-mmc-hw-reset;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	vmmc-supply = <&vcc_3v3>;
+	vqmmc-supply = <&emmc_vdd>;
+};
-- 
2.43.2

Re: [PATCH v4 6/6] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree

[E Shattow]

On 11/24/25 23:56, Hal Feng wrote:
> VisionFive 2 Lite eMMC board uses a non-removable onboard 64GiB eMMC
> instead of the MicroSD slot.
> 
> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> Tested-by: Matthias Brugger <mbrugger@suse.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  arch/riscv/boot/dts/starfive/Makefile         |  1 +
>  ...jh7110-starfive-visionfive-2-lite-emmc.dts | 22 +++++++++++++++++++
>  2 files changed, 23 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
> 
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 2b1e7fcd6f84..a640ed5dc5a1 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -14,5 +14,6 @@ dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-emmc.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-milkv-marscm-lite.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-pine64-star64.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite.dtb
> +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-lite-emmc.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>  dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
> new file mode 100644
> index 000000000000..e27a662d4022
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite-emmc.dts
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2025 StarFive Technology Co., Ltd.
> + * Copyright (C) 2025 Hal Feng <hal.feng@starfivetech.com>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2-lite.dtsi"
> +
> +/ {
> +	model = "StarFive VisionFive 2 Lite eMMC";

> +	compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s";

Add "starfive,jh7110" to the compatible list as the least-compatible
(left-to-right order last item):

compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110s",
"starfive,jh7110";

or if there is review feedback that no new compatible should be added,
then as usual for new JH-7110 boards:

compatible = "starfive,visionfive-2-lite-emmc", "starfive,jh7110";

> +};
> +
> +&mmc0 {
> +	cap-mmc-highspeed;
> +	cap-mmc-hw-reset;
> +	mmc-ddr-1_8v;
> +	mmc-hs200-1_8v;
> +	vmmc-supply = <&vcc_3v3>;
> +	vqmmc-supply = <&emmc_vdd>;
> +};

-E

Re: (subset) [PATCH v4 0/6] Add support for StarFive VisionFive 2 Lite board

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Tue, 25 Nov 2025 15:55:58 +0800, Hal Feng wrote:
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
> 
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
> 
> [...]

Applied to riscv-dt-for-next, thanks! No patch 1 of course, since that's
for PCI land.

[2/6] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board
      https://git.kernel.org/conor/c/7a1e15b248d6
[3/6] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts
      https://git.kernel.org/conor/c/84853940a733
[4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
      https://git.kernel.org/conor/c/2ad6d71a0de8
[5/6] riscv: dts: starfive: Add VisionFive 2 Lite board device tree
      https://git.kernel.org/conor/c/900b32fd601b
[6/6] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
      https://git.kernel.org/conor/c/ae264ae12442

Thanks,
Conor.

Re: [PATCH v4 0/6] Add support for StarFive VisionFive 2 Lite board

[patchwork-bot+linux-riscv]

Hello:

This series was applied to riscv/linux.git (fixes)
by Conor Dooley <conor.dooley@microchip.com>:

On Tue, 25 Nov 2025 15:55:58 +0800 you wrote:
> VisionFive 2 Lite is a mini SBC based on the StarFive JH7110S industrial
> SoC which can run at -40~85 degrees centigrade and up to 1.25GHz.
> 
> Board features:
> - JH7110S SoC
> - 4/8 GiB LPDDR4 DRAM
> - AXP15060 PMIC
> - 40 pin GPIO header
> - 1x USB 3.0 host port
> - 3x USB 2.0 host port
> - 1x M.2 M-Key (size: 2242)
> - 1x MicroSD slot (optional non-removable 64GiB eMMC)
> - 1x QSPI Flash
> - 1x I2C EEPROM
> - 1x 1Gbps Ethernet port
> - SDIO-based Wi-Fi & UART-based Bluetooth
> - 1x HDMI port
> - 1x 2-lane DSI
> - 1x 2-lane CSI
> 
> [...]

Here is the summary with links:
  - [v4,1/6] PCI: starfive: Use regulator APIs instead of GPIO APIs to enable the 3V3 power supply of PCIe slots
    (no matching commit)
  - [v4,2/6] dt-bindings: riscv: Add StarFive JH7110S SoC and VisionFive 2 Lite board
    https://git.kernel.org/riscv/c/7a1e15b248d6
  - [v4,3/6] riscv: dts: starfive: jh7110-common: Move out some nodes to the board dts
    https://git.kernel.org/riscv/c/84853940a733
  - [v4,4/6] riscv: dts: starfive: Add common board dtsi for VisionFive 2 Lite variants
    https://git.kernel.org/riscv/c/2ad6d71a0de8
  - [v4,5/6] riscv: dts: starfive: Add VisionFive 2 Lite board device tree
    https://git.kernel.org/riscv/c/900b32fd601b
  - [v4,6/6] riscv: dts: starfive: Add VisionFive 2 Lite eMMC board device tree
    https://git.kernel.org/riscv/c/ae264ae12442

You are awesome, thank you!
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