[PATCH v7 3/3] PCI: dwc: Add no_pme_handshake flag and skip PME_Turn_Off broadcast

[zhangsenchuan@eswincomputing.com]

From: Senchuan Zhang <zhangsenchuan@eswincomputing.com>

The ESWIN EIC7700 SoC lacks hardware support for the L2/L3 low-power
link states. It cannot enter the L2/L3 ready state through the
PME_Turn_Off/PME_To_Ack handshake protocol. To address this, add a
no_pme_handshake flag skip PME_Turn_Off broadcast and link state check
code, other driver can reuse this flag if meet the similar situation.

Signed-off-by: Yu Ning <ningyu@eswincomputing.com>
Signed-off-by: Yanghui Ou <ouyanghui@eswincomputing.com>
Signed-off-by: Senchuan Zhang <zhangsenchuan@eswincomputing.com>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 4 ++++
 drivers/pci/controller/dwc/pcie-designware.h      | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 372207c33a85..8302bc7a6cbf 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1168,6 +1168,9 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 	if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1)
 		return 0;

+	if (pci->no_pme_handshake)
+		goto stop_link;
+
 	if (pci->pp.ops->pme_turn_off) {
 		pci->pp.ops->pme_turn_off(&pci->pp);
 	} else {
@@ -1194,6 +1197,7 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 	 */
 	udelay(1);

+stop_link:
 	dw_pcie_stop_link(pci);
 	if (pci->pp.ops->deinit)
 		pci->pp.ops->deinit(&pci->pp);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 31685951a080..e8057db303d0 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -549,6 +549,7 @@ struct dw_pcie {
 	 * use_parent_dt_ranges to true to avoid this warning.
 	 */
 	bool			use_parent_dt_ranges;
+	bool			no_pme_handshake;
 };

 #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
--
2.25.1