From: Rob Herring <robh@kernel.org>
To: Jie Gan <jie.gan@oss.qualcomm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Mao Jinlong <jinlong.mao@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, Krzysztof Kozlowski <krzk@kernel.org>
Subject: Re: [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU
Date: Thu, 11 Dec 2025 07:37:23 -0600 [thread overview]
Message-ID: <20251211133723.GA859302-robh@kernel.org> (raw)
In-Reply-To: <20251211-enable-byte-cntr-for-ctcu-v8-5-3e12ff313191@oss.qualcomm.com>
On Thu, Dec 11, 2025 at 02:10:44PM +0800, Jie Gan wrote:
> Add an interrupt property to CTCU device. The interrupt will be triggered
> when the data size in the ETR buffer exceeds the threshold of the
> BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register
> of CTCU device will enable the interrupt.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> ---
> .../devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> index c969c16c21ef..90f88cc6cd3e 100644
> --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
> @@ -39,6 +39,16 @@ properties:
> items:
> - const: apb
>
> + interrupts:
> + items:
> + - description: Byte cntr interrupt for the first etr device
> + - description: Byte cntr interrupt for the second etr device
> +
> + interrupt-names:
> + items:
> + - const: etrirq0
> + - const: etrirq1
Names are kind of pointless when it is just foo<index>.
> +
> label:
> description:
> Description of a coresight device.
> @@ -60,6 +70,8 @@ additionalProperties: false
>
> examples:
> - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> ctcu@1001000 {
> compatible = "qcom,sa8775p-ctcu";
> reg = <0x1001000 0x1000>;
> @@ -67,6 +79,11 @@ examples:
> clocks = <&aoss_qmp>;
> clock-names = "apb";
>
> + interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "etrirq0",
> + "etrirq1;
> +
> in-ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2025-12-11 13:37 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-11 6:10 [PATCH v8 0/8] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-12-11 6:10 ` [PATCH v8 1/8] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-12-11 6:10 ` [PATCH v8 2/8] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-12-13 12:38 ` kernel test robot
2025-12-11 6:10 ` [PATCH v8 3/8] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2025-12-11 6:10 ` [PATCH v8 4/8] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2025-12-11 6:10 ` [PATCH v8 5/8] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-12-11 7:27 ` Rob Herring (Arm)
2025-12-11 7:35 ` Jie Gan
2025-12-11 13:37 ` Rob Herring [this message]
2025-12-12 1:12 ` Jie Gan
2025-12-11 6:10 ` [PATCH v8 6/8] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-12-11 6:10 ` [PATCH v8 7/8] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-12-11 6:10 ` [PATCH v8 8/8] arm64: dts: qcom: lemans: Add interrupts to CTCU device Jie Gan
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