From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57759314A74 for ; Sun, 14 Dec 2025 21:53:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765749185; cv=none; b=gRdKuO3/jmQXhB4gAXM+HZda+AgS5UMdeCbNkI7r/O0yyg12VIZfurR2B1rjdgBOk5vZBfWPo3azu0vbM7sA3D4QF9iiCh8sexNoCYnxcgGsFWqIeLY7sFZUhzV/EDLowCU5GM07mRkw5E1lEyatUn6fyT1UfMh0zDzpcIA8/54= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765749185; c=relaxed/simple; bh=7ljJ05ztTohJDBRhGnpzl50vRdnwmAmrwNkbp/q570E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RfEs1jwO4UHl4v/WG5JGvFgw7puTs+7P8wBRBYSWjluYYDyZzpUJJTWXdNyyVLOiPFGUrNEySwZECUMKSWkFh/4DvOzcyLupYZvuvkAFEScoVn9edTwvEbSHjl/O7K379pCfQOTJcrpn9PFBl9eWXdFWn8mJxhLrWBjQi81Vp5Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e5ZUdZbd; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e5ZUdZbd" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4779a637712so18789475e9.1 for ; Sun, 14 Dec 2025 13:53:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1765749182; x=1766353982; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d98j53CwylYGkDXzrv9xLEHUO5ol14s3GpQ93nPd4ok=; b=e5ZUdZbdVMHiWbilGX0mi/pjjtnZJ3d1Qib7wY4ydqHjxfAtN6zQW+F38aHPbY9uyg 1zuftU27lZ6C5UQJR5yglcTdnCHtVibTqBU0N24ATE/KXyU5JanfSccPVY1jW3rtlVg4 fDmXZ211F95chyRlSGs32EX6D1DRFL6LgAfz5cIhXV6BRs4bmBms2Z2VG29VEa27YCAB VucXT8EFZ8Fbg52DwZRGECKoSeC7pv9YY4uiJXQ0Ux93dsoLaxSdcd3G/ExgYTsTZ6nZ FoyeNqYOHpUYUlJEyDeppziM1PbH0SFXq8BNM57avI64YciXWw/UBnx6hRBO60lnPDi2 Z8PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1765749182; x=1766353982; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=d98j53CwylYGkDXzrv9xLEHUO5ol14s3GpQ93nPd4ok=; b=V5RbrAqXJhv8tagweETYcmU7KpoyIvat0KAiWtANhPWgT+QMnkEfA/9I7ovwcMIP+A BpEJnhHQrDnOpDTZfoAH0osJn66TPnwBvSQub3gWsXRuaORSrNblpHfwHlm8yGNyFec3 v7ysurslx4R8UfZdom6fCEDNVX94rt+9XuhVjQdI2P6ebkqwrV2SvsIT6i6fVsXxv5mH jboyvb4OABotxFW/LCitFsPQrrKPfaBpG8XgaaU8iq15MUvnPyOqALLzMrcUm+yept0o HoXovjrZ7CQpaHQ8DWUrN6sXAFDDxA8E+cWRTIIIqBah2XdICiqaakxOWIrWLFWpv3Ei Z+uw== X-Gm-Message-State: AOJu0YyO6QTWXdur73hd8kVnokGG3vRsSA8ao+VapEWTFUQ9pS6aGFiu gXKHsNdZIS7cKWXqnkc385GByZuHNA3nDqmObwyEVhw4zzlXYMMtVAGp4ZXOcT+P X-Gm-Gg: AY/fxX7FGBaDMHKyxoVUkDb80QMdzaJq0RkeTNQ49rqxnPgLB99LWzEKdb7SrRjrdXE O6WbXwhmVzqJ2pGMP4R5mmCx4h2nHSpRyzkTSNGTqlz60CitQB1MazFHnVW+1HkDcb1iniLaauX pAdUGRsVZRMpB8uxorrEilwHR/ls0KT37y1cLUhG+ucgqtQp6wyxzDMXU7XhuPsozOPbrpsGm7l V/vePRNOeho6115PzWL1lszJh+Niphqxw84DD0RmXpp5Gia3wzRzKhFARRrDP03msdB4cpL19O/ nCut+6bItrfZj9W520pN8MNkvnIR0X0oTy6V1LDwCNUco4kYd/0Vb41zMbL89Gr36DKlRG1yMpp j7rqvBRyD91jHnq4ejSY+Wc0qKe92934VqvYK8VrQu3ZaO7pbZM1hlO5ZPpEevB0Tj0QuU9zJVZ Kd36Iu5si+ipx9K6YiYJpaoHKYYcTwyJe5wJLvcXs9cyDiXcF81Xk4vuVABQMzX1CNcc4Mt0ic3 4qu/doVC4j8ZnY= X-Google-Smtp-Source: AGHT+IF84y4pyjyyMtX/3o85XLxndY0sG21i7o5eJ/lJM3XFxdHdZGn96Mk3h3sCkTBWYc9DRKeJPw== X-Received: by 2002:a05:6000:402c:b0:42b:4803:75e8 with SMTP id ffacd0b85a97d-42fb490d6f1mr8699960f8f.43.1765749181465; Sun, 14 Dec 2025 13:53:01 -0800 (PST) Received: from Lord-Beerus.station (net-5-94-28-5.cust.vodafonedsl.it. [5.94.28.5]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-430f6a42c8csm7625568f8f.16.2025.12.14.13.53.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 14 Dec 2025 13:53:00 -0800 (PST) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 1/6] arm64: dts: imx8mp-var-som: Move USDHC2 support to Symphony carrier Date: Sun, 14 Dec 2025 22:52:48 +0100 Message-ID: <20251214215256.5812-2-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251214215256.5812-1-stefano.r@variscite.com> References: <20251214215256.5812-1-stefano.r@variscite.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The VAR-SOM-MX8MP module does not include a microSD slot connected to USDHC2. The USDHC2 interface is routed only on the Symphony carrier board, and it may optionally be used or omitted depending on the customer's carrier design. Move the USDHC2 node, its regulators, pinctrl groups and related GPIOs from the SOM device tree to the Symphony carrier DTS, keeping the SOM description limited to hardware populated on the module. Signed-off-by: Stefano Radaelli --- .../dts/freescale/imx8mp-var-som-symphony.dts | 77 +++++++++++++++++++ .../boot/dts/freescale/imx8mp-var-som.dtsi | 75 ------------------ 2 files changed, 77 insertions(+), 75 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts index 36d3eb865202..ea3c193bb684 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som-symphony.dts @@ -8,4 +8,81 @@ / { model = "Variscite VAR-SOM-MX8M-PLUS on Symphony-Board"; compatible = "variscite,var-som-mx8mp-symphony", "variscite,var-som-mx8mp", "fsl,imx8mp"; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "VSD_VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0 1800000 0x1>; + vin-supply = <&ldo5>; + }; +}; + +/* SD-card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi index 29f080904482..949d9878f395 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-var-som.dtsi @@ -35,27 +35,6 @@ memory@40000000 { <0x1 0x00000000 0 0xc0000000>; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "VSD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us = <100>; - off-on-delay-us = <12000>; - }; - - reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { - compatible = "regulator-gpio"; - regulator-name = "VSD_VSEL"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - states = <3300000 0x0 1800000 0x1>; - vin-supply = <&ldo5>; - }; - reg_phy_supply: regulator-phy-supply { compatible = "regulator-fixed"; regulator-name = "phy-supply"; @@ -271,19 +250,6 @@ &uart2 { status = "okay"; }; -/* SD-card */ -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; - vmmc-supply = <®_usdhc2_vmmc>; - vqmmc-supply = <®_usdhc2_vqmmc>; - bus-width = <4>; - status = "okay"; -}; - /* eMMC */ &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -358,47 +324,6 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40 >; }; - pinctrl_usdhc2_gpio: usdhc2-gpiogrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c4 - MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 - MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0xc0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 - MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 - MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 - MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 - MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 - MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 - >; - }; - pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 -- 2.47.3