From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9FA2972612; Wed, 17 Dec 2025 17:20:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765992051; cv=none; b=f9yz5PihaqpECRKi7tynwumG0bVFKSXuH1spfxwwCC59yXE4ym7sTS+nwHSZmg6F8s1WyqgRmU9MeIT8w3hCkik5Mwv+GzVt4ezRR9ab+F3zS7Rm7iWyV2NHVhTXlMp0KpBwThJrDndgdBgOT/Y6Un2yNxLl+dKKdnyq1SCjF7g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765992051; c=relaxed/simple; bh=Y9YEMqCOaRn9nWISRWIOagoTl21UEQ/DY+m2rBZ6YSk=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GUTCeibU3YVZEo+2/2CARhNeBybD8vLMixid2ovHB8ibJA8EGHJR5tU7X1FFQd4hvsalWPF5WBSM8MzdqLb4PpntWGbnn6p9ZasKF3xLwJwBmqxsyZu0iPretrdacMSlWllbz3slRYHcsumyHtNk5BHpGtqVPMg77RFPOFxddyg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=epK3AyeX; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="epK3AyeX" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1765992045; bh=Y9YEMqCOaRn9nWISRWIOagoTl21UEQ/DY+m2rBZ6YSk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=epK3AyeXUp2FZABNF07bFT7e0KVu4mytFWGi74liuJj6pEM7CDfl6PUxpMrnOZ9u6 AcN2YFicfI9kWfplIYbc2wDrzsMcX9XxAhMOlc+w7D8dNz8fhd7GmorSzsPCK52Pp+ Fis8zi+LW9j6qj/lQYZ8lJGVFXK2fCWd6zqxNyUCmO0JXHmBfdqsRI6ALj6N0s4jJM lujKnpd7ojXxxE8q45cadWjnpWk92Bw5hUn3Iaqz13e2oEjIUT7R0iFDCMuaaMkuVA ONrOae+/kZatf1hCJD9JV+YFAL1nbV5G/J1y2bkSdKZFxswpEAoEClyoQPKt2wAwRY 2/HXroMnpXX2g== Received: from fedora (unknown [IPv6:2a01:e0a:2c:6930:d919:a6e:5ea1:8a9f]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 4C7FA17E127F; Wed, 17 Dec 2025 18:20:44 +0100 (CET) Date: Wed, 17 Dec 2025 18:20:38 +0100 From: Boris Brezillon To: Nicolas Frattaroli Cc: Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson , Chen-Yu Tsai , Chia-I Wu , kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org Subject: Re: [PATCH 3/4] drm/panthor: Implement reading shader_present from nvmem Message-ID: <20251217182038.6779a191@fedora> In-Reply-To: <20251217-mt8196-shader-present-v1-3-f6f8f3aa1e93@collabora.com> References: <20251217-mt8196-shader-present-v1-0-f6f8f3aa1e93@collabora.com> <20251217-mt8196-shader-present-v1-3-f6f8f3aa1e93@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 17 Dec 2025 18:03:29 +0100 Nicolas Frattaroli wrote: > On some platforms, notably MediaTek MT8196, the shader_present bitmask > in the Mali GPU register for it has cores enabled that may be faulty. > The true shader_present bitmask is found in an efuse instead. > > Implement reading shader_present from an nvmem cell if one is present, > falling back to the Mali register if it's absent. The error codes are > trickled up through to the probe function so that probe deferral works. > > Signed-off-by: Nicolas Frattaroli Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/panthor/panthor_hw.c | 63 ++++++++++++++++++++++++++++++++---- > 1 file changed, 57 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/panthor/panthor_hw.c b/drivers/gpu/drm/panthor/panthor_hw.c > index 87ebb7ae42c4..eb44c8b108aa 100644 > --- a/drivers/gpu/drm/panthor/panthor_hw.c > +++ b/drivers/gpu/drm/panthor/panthor_hw.c > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: GPL-2.0 or MIT > /* Copyright 2025 ARM Limited. All rights reserved. */ > > +#include > #include > > #include "panthor_device.h" > @@ -109,7 +110,52 @@ static char *get_gpu_model_name(struct panthor_device *ptdev) > return "(Unknown Mali GPU)"; > } > > -static void panthor_gpu_info_init(struct panthor_device *ptdev) > +static int overload_shader_present(struct panthor_device *ptdev) > +{ > + struct device *dev = ptdev->base.dev; > + struct nvmem_cell *cell = nvmem_cell_get(dev, "shader-present"); > + ssize_t len; > + void *buf; > + int ret; > + > + if (IS_ERR(cell)) { > + /* On platforms without this cell, use the Mali register */ > + if (PTR_ERR(cell) == -ENOENT) > + return 0; > + > + return dev_err_probe(dev, PTR_ERR(cell), > + "Failed to get shader-present nvmem cell\n"); > + } > + > + buf = nvmem_cell_read(cell, &len); > + if (IS_ERR(buf)) { > + ret = dev_err_probe(dev, PTR_ERR(buf), > + "Failed to read shader-present nvmem cell\n"); > + goto err_put_cell; > + } > + > + if (!len || len > 8) { > + ret = dev_err_probe(dev, -EINVAL, "shader-present cell can't be length %ld\n", > + len); > + goto err_free; > + } > + > + memcpy(&ptdev->gpu_info.shader_present, buf, len); > + > + kfree(buf); > + nvmem_cell_put(cell); > + > + return 0; > + > +err_free: > + kfree(buf); > +err_put_cell: > + nvmem_cell_put(cell); > + > + return ret; > +} > + > +static int panthor_gpu_info_init(struct panthor_device *ptdev) > { > unsigned int i; > > @@ -143,13 +189,18 @@ static void panthor_gpu_info_init(struct panthor_device *ptdev) > ptdev->gpu_info.tiler_present = gpu_read64(ptdev, GPU_TILER_PRESENT); > ptdev->gpu_info.l2_present = gpu_read64(ptdev, GPU_L2_PRESENT); > } > + > + return overload_shader_present(ptdev); > } > > -static void panthor_hw_info_init(struct panthor_device *ptdev) > +static int panthor_hw_info_init(struct panthor_device *ptdev) > { > u32 major, minor, status; > + int ret; > > - panthor_gpu_info_init(ptdev); > + ret = panthor_gpu_info_init(ptdev); > + if (ret) > + return ret; > > major = GPU_VER_MAJOR(ptdev->gpu_info.gpu_id); > minor = GPU_VER_MINOR(ptdev->gpu_info.gpu_id); > @@ -172,6 +223,8 @@ static void panthor_hw_info_init(struct panthor_device *ptdev) > "shader_present=0x%0llx l2_present=0x%0llx tiler_present=0x%0llx", > ptdev->gpu_info.shader_present, ptdev->gpu_info.l2_present, > ptdev->gpu_info.tiler_present); > + > + return 0; > } > > static int panthor_hw_bind_device(struct panthor_device *ptdev) > @@ -218,7 +271,5 @@ int panthor_hw_init(struct panthor_device *ptdev) > if (ret) > return ret; > > - panthor_hw_info_init(ptdev); > - > - return 0; > + return panthor_hw_info_init(ptdev); > } >