[PATCH v2 06/12] coresight-replicator: Update management interface for CPU-bound devices

Yuanfang Zhang
2025-12-18T08:10:51Z

Standard system replicators allow direct register access from any CPU.
However, replicators associated with specific CPU clusters share the
cluster's power domain and require access via a CPU within that domain.

Replace the standard `coresight_simple_reg*` accessors with custom
handlers (`coresight_replicator_reg*`) to support these devices:
- For cluster-bound replicators (indicated by `supported_cpus`), use
`smp_call_function_single()` to read registers on an associated CPU.
- For standard replicators, retain the direct access behavior.

This ensures correct operation for per-cluster replicators while
maintaining compatibility for existing system-level devices.

Signed-off-by: Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
---
drivers/hwtracing/coresight/coresight-replicator.c | 61 +++++++++++++++++++++-
1 file changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index f8d13894098f1e414fb0da8d6eeb1da4f0d55a8c..a9f22d0e15de21aa06c8d1e193e5db06091efd75 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -58,6 +58,7 @@ struct replicator_drvdata {
struct replicator_smp_arg {
struct replicator_drvdata *drvdata;
int outport;
+ u32 offset;
int rc;
};

@@ -286,9 +287,65 @@ static const struct coresight_ops replicator_cs_ops = {
.link_ops = &replicator_link_ops,
};

+static void replicator_read_register_smp_call(void *info)
+{
+ struct replicator_smp_arg *arg = info;
+
+ arg->rc = readl_relaxed(arg->drvdata->base + arg->offset);
+}
+
+static ssize_t coresight_replicator_reg32_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct replicator_drvdata *drvdata = dev_get_drvdata(dev->parent);
+ struct cs_off_attribute *cs_attr = container_of(attr, struct cs_off_attribute, attr);
+ unsigned long flags;
+ struct replicator_smp_arg arg = { 0 };
+ u32 val;
+ int ret, cpu;
+
+ pm_runtime_get_sync(dev->parent);
+
+ if (!drvdata->supported_cpus) {
+ raw_spin_lock_irqsave(&drvdata->spinlock, flags);
+ val = readl_relaxed(drvdata->base + cs_attr->off);
+ raw_spin_unlock_irqrestore(&drvdata->spinlock, flags);
+
+ } else {
+ arg.drvdata = drvdata;
+ arg.offset = cs_attr->off;
+ for_each_cpu(cpu, drvdata->supported_cpus) {
+ ret = smp_call_function_single(cpu,
+ replicator_read_register_smp_call,
+ &arg, 1);
+ if (!ret)
+ break;
+ }
+ if (!ret) {
+ val = arg.rc;
+ } else {
+ pm_runtime_put_sync(dev->parent);
+ return ret;
+ }
+ }
+
+ pm_runtime_put_sync(dev->parent);
+
+ return sysfs_emit(buf, "0x%x\n", val);
+}
+
+#define coresight_replicator_reg32(name, offset) \
+ (&((struct cs_off_attribute[]) { \
+ { \
+ __ATTR(name, 0444, coresight_replicator_reg32_show, NULL), \
+ offset \
+ } \
+ })[0].attr.attr)
+
static struct attribute *replicator_mgmt_attrs[] = {
- coresight_simple_reg32(idfilter0, REPLICATOR_IDFILTER0),
- coresight_simple_reg32(idfilter1, REPLICATOR_IDFILTER1),
+ coresight_replicator_reg32(idfilter0, REPLICATOR_IDFILTER0),
+ coresight_replicator_reg32(idfilter1, REPLICATOR_IDFILTER1),
NULL,
};

--
2.34.1