[PATCH 0/4] arm64: allwinner: a523: Support SPI controllers

[PATCH 0/4] arm64: allwinner: a523: Support SPI controllers

[Chen-Yu Tsai]

Hi folks,

This series adds support for the SPI controllers found in the Allwinner
A523 SoC family. The SPI controller is almost the same as the ones in
previous generations, except that it moved the "RX buffer count"
register field to a separate register, and that register now reports
the total count for RX buffer and FIFO.

In practice the driver has never cared about the buffer count, but if
any implementation were to use it, this counts as a non-backward
compatible change.

Also, one of the SPI controllers supports DBI mode, acting as a display
interface. There is no infrastructure for DBI interface controllers in
the kernel, so only a separate compatible is added for it.

Patch 1 adds compatible strings for the new variants.

Patch 2 adds driver support for the new SPI controller variant.

Patch 3 adds device nodes for the SPI controllers to the dtsi file,
along with pinmux settings for spi0 on the PC pins, a common usage for
SPI-NOR flashes to boot from.

Patch 4 enables the SPI-NOR flash found on the Radxa Cubie A5E.


Please take a look and try it out.


Thanks
ChenYu


Chen-Yu Tsai (4):
  spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers
  spi: sun6i: Support A523's SPI controllers
  arm64: dts: allwinner: sun55i: Add SPI controllers
  arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash

 .../bindings/spi/allwinner,sun6i-a31-spi.yaml |  4 +
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 +++++++++++++++++++
 .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 15 +++
 drivers/spi/spi-sun6i.c                       | 11 ++-
 4 files changed, 120 insertions(+), 4 deletions(-)

-- 
2.47.3

[PATCH 1/4] spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers

[Chen-Yu Tsai]

The A523 has four SPI controllers. One of them supports MIPI DBI mode
in addition to standard SPI.

Compared to older generations, this newer controller now has a combined
counter for the RX FIFO ad buffer levels. In older generations, the
RX buffer level was a separate bitfield in the FIFO status register.

In practice this difference is negligible. The buffer is mostly
invisible to the implementation. If programmed I/O transfers are limited
to the FIFO size, then the contents of the buffer seem to always be
flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied
to the FIFO levels. In all other aspects, the controller is the same as
the one in the R329.

Add new compatible strings for the new controllers.

Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
---
 .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml      | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
index 3b47b68b92cb..1b91d1566c95 100644
--- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
@@ -17,6 +17,7 @@ properties:
   compatible:
     oneOf:
       - const: allwinner,sun50i-r329-spi
+      - const: allwinner,sun55i-a523-spi
       - const: allwinner,sun6i-a31-spi
       - const: allwinner,sun8i-h3-spi
       - items:
@@ -35,6 +36,9 @@ properties:
           - const: allwinner,sun20i-d1-spi-dbi
           - const: allwinner,sun50i-r329-spi-dbi
           - const: allwinner,sun50i-r329-spi
+      - items:
+          - const: allwinner,sun55i-a523-spi-dbi
+          - const: allwinner,sun55i-a523-spi
 
   reg:
     maxItems: 1
-- 
2.47.3

[PATCH 2/4] spi: sun6i: Support A523's SPI controllers

[Chen-Yu Tsai]

The A523 has four SPI controllers. One of them supports MIPI DBI mode
in addition to standard SPI.

Compared to older generations, this newer controller now has a combined
counter for the RX FIFO ad buffer levels. In older generations, the
RX buffer level was a separate bitfield in the FIFO status register.

In practice this difference is negligible. The buffer is mostly
invisible to the implementation. If programmed I/O transfers are limited
to the FIFO size, then the contents of the buffer seem to always be
flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied
to the FIFO levels. In all other aspects, the controller is the same as
the one in the R329.

Support the standard SPI mode controllers using the settings for R329.
DBI is left out as there currently is no infrastructure for enabling a
DBI host controller, as was the case for the R329.

Also fold the entry for the R329 to make the style consistent.

Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
---
 drivers/spi/spi-sun6i.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index 871dfd3e77be..d1de6c99e762 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -795,10 +795,13 @@ static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
 static const struct of_device_id sun6i_spi_match[] = {
 	{ .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
 	{ .compatible = "allwinner,sun8i-h3-spi",  .data = &sun8i_h3_spi_cfg },
-	{
-		.compatible = "allwinner,sun50i-r329-spi",
-		.data = &sun50i_r329_spi_cfg
-	},
+	{ .compatible = "allwinner,sun50i-r329-spi", .data = &sun50i_r329_spi_cfg },
+	/*
+	 * A523's SPI controller has a combined RX buffer + FIFO counter
+	 * at offset 0x400, instead of split buffer count in FIFO status
+	 * register. But in practice we only care about the FIFO level.
+	 */
+	{ .compatible = "allwinner,sun55i-a523-spi", .data = &sun50i_r329_spi_cfg },
 	{}
 };
 MODULE_DEVICE_TABLE(of, sun6i_spi_match);
-- 
2.47.3

[PATCH 3/4] arm64: dts: allwinner: sun55i: Add SPI controllers

[Chen-Yu Tsai]

The A523 family SoCs have four SPI controllers. One of them also
supports DBI mode.

Add device nodes for all of them. Also add pinmux nodes for spi0 on the
PC pins, which is commonly used for SPI-NOR boot flash.

Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
---
 .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 +++++++++++++++++++
 1 file changed, 94 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
index 42dab01e3f56..9335977751e2 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi
@@ -214,6 +214,43 @@ spdif_out_pi_pin: spdif-pi-pin {
 				allwinner,pinmux = <2>;
 			};
 
+			/omit-if-no-ref/
+			spi0_pc_pins: spi0-pc-pins {
+				pins = "PC2", "PC4", "PC12";
+				function = "spi0";
+				allwinner,pinmux = <4>;
+			};
+
+			/omit-if-no-ref/
+			spi0_cs0_pc_pin: spi0-cs0-pc-pin {
+				pins = "PC3";
+				function = "spi0";
+				allwinner,pinmux = <4>;
+			};
+
+			/omit-if-no-ref/
+			spi0_cs1_pc_pin: spi0-cs1-pc-pin {
+				pins = "PC7";
+				function = "spi0";
+				allwinner,pinmux = <4>;
+			};
+
+			/omit-if-no-ref/
+			spi0_hold_pc_pin: spi0-hold-pc-pin {
+				/* conflicts with eMMC D7 */
+				pins = "PC16";
+				function = "spi0";
+				allwinner,pinmux = <4>;
+			};
+
+			/omit-if-no-ref/
+			spi0_wp_pc_pin: spi0-wp-pc-pin {
+				/* conflicts with eMMC D2 */
+				pins = "PC15";
+				function = "spi0";
+				allwinner,pinmux = <4>;
+			};
+
 			uart0_pb_pins: uart0-pb-pins {
 				pins = "PB9", "PB10";
 				allwinner,pinmux = <2>;
@@ -563,6 +600,49 @@ mmc2: mmc@4022000 {
 			#size-cells = <0>;
 		};
 
+		spi0: spi@4025000 {
+			compatible = "allwinner,sun55i-a523-spi";
+			reg = <0x04025000 0x1000>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma 22>, <&dma 22>;
+			dma-names = "rx", "tx";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@4026000 {
+			compatible = "allwinner,sun55i-a523-spi-dbi",
+				     "allwinner,sun55i-a523-spi";
+			reg = <0x04026000 0x1000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma 23>, <&dma 23>;
+			dma-names = "rx", "tx";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi2: spi@4027000 {
+			compatible = "allwinner,sun55i-a523-spi";
+			reg = <0x04027000 0x1000>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma 24>, <&dma 24>;
+			dma-names = "rx", "tx";
+			resets = <&ccu RST_BUS_SPI2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		usb_otg: usb@4100000 {
 			compatible = "allwinner,sun55i-a523-musb",
 				     "allwinner,sun8i-a33-musb";
@@ -815,6 +895,20 @@ rtc: rtc@7090000 {
 			#clock-cells = <1>;
 		};
 
+		r_spi0: spi@7092000 {
+			compatible = "allwinner,sun55i-a523-spi";
+			reg = <0x07092000 0x1000>;
+			interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&r_ccu CLK_BUS_R_SPI>, <&r_ccu CLK_R_SPI>;
+			clock-names = "ahb", "mod";
+			dmas = <&dma 53>, <&dma 53>;
+			dma-names = "rx", "tx";
+			resets = <&r_ccu RST_BUS_R_SPI>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		mcu_ccu: clock-controller@7102000 {
 			compatible = "allwinner,sun55i-a523-mcu-ccu";
 			reg = <0x7102000 0x200>;
-- 
2.47.3

[PATCH 4/4] arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash

[Chen-Yu Tsai]

The Orangepi 4A has a SPI-NOR flash connected to spi0 on the PC pins.
The HOLD and WP pins are not connected, and are instead pulled up by the
supply rail.

Enable spi0 and add a device node for the SPI-NOR flash.

Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
---
 .../dts/allwinner/sun55i-t527-orangepi-4a.dts     | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
index 9e6b21cf293e..055be86e5fae 100644
--- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
+++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts
@@ -400,6 +400,21 @@ &rtc {
 	assigned-clock-rates = <32768>;
 };
 
+&spi0  {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>;
+	status = "okay";
+
+	flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		vcc-supply = <&reg_cldo1>;
+	};
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pb_pins>;
-- 
2.47.3

Re: [PATCH 1/4] spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers

[Krzysztof Kozlowski]

On Sun, Dec 21, 2025 at 07:05:08PM +0800, Chen-Yu Tsai wrote:
> The A523 has four SPI controllers. One of them supports MIPI DBI mode
> in addition to standard SPI.
> 
> Compared to older generations, this newer controller now has a combined
> counter for the RX FIFO ad buffer levels. In older generations, the
> RX buffer level was a separate bitfield in the FIFO status register.
> 
> In practice this difference is negligible. The buffer is mostly
> invisible to the implementation. If programmed I/O transfers are limited
> to the FIFO size, then the contents of the buffer seem to always be
> flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied
> to the FIFO levels. In all other aspects, the controller is the same as
> the one in the R329.
> 
> Add new compatible strings for the new controllers.
> 
> Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
> ---
>  .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml      | 4 ++++
>  1 file changed, 4 insertions(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

Re: [PATCH 2/4] spi: sun6i: Support A523's SPI controllers

[Jernej Škrabec]

Dne nedelja, 21. december 2025 ob 12:05:09 Srednjeevropski standardni čas je Chen-Yu Tsai napisal(a):
> The A523 has four SPI controllers. One of them supports MIPI DBI mode
> in addition to standard SPI.
> 
> Compared to older generations, this newer controller now has a combined
> counter for the RX FIFO ad buffer levels. In older generations, the
> RX buffer level was a separate bitfield in the FIFO status register.
> 
> In practice this difference is negligible. The buffer is mostly
> invisible to the implementation. If programmed I/O transfers are limited
> to the FIFO size, then the contents of the buffer seem to always be
> flushed over to the FIFO. For DMA, the DRQ trigger levels are only tied
> to the FIFO levels. In all other aspects, the controller is the same as
> the one in the R329.
> 
> Support the standard SPI mode controllers using the settings for R329.
> DBI is left out as there currently is no infrastructure for enabling a
> DBI host controller, as was the case for the R329.
> 
> Also fold the entry for the R329 to make the style consistent.
> 
> Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH 3/4] arm64: dts: allwinner: sun55i: Add SPI controllers

[Jernej Škrabec]

Dne nedelja, 21. december 2025 ob 12:05:10 Srednjeevropski standardni čas je Chen-Yu Tsai napisal(a):
> The A523 family SoCs have four SPI controllers. One of them also
> supports DBI mode.
> 
> Add device nodes for all of them. Also add pinmux nodes for spi0 on the
> PC pins, which is commonly used for SPI-NOR boot flash.
> 
> Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH 4/4] arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash

[Jernej Škrabec]

Dne nedelja, 21. december 2025 ob 12:05:11 Srednjeevropski standardni čas je Chen-Yu Tsai napisal(a):
> The Orangepi 4A has a SPI-NOR flash connected to spi0 on the PC pins.
> The HOLD and WP pins are not connected, and are instead pulled up by the
> supply rail.
> 
> Enable spi0 and add a device node for the SPI-NOR flash.
> 
> Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH 0/4] arm64: allwinner: a523: Support SPI controllers

[Chen-Yu Tsai]

On Sun, Dec 21, 2025 at 7:05 PM Chen-Yu Tsai <wens@kernel.org> wrote:
>
> Hi folks,
>
> This series adds support for the SPI controllers found in the Allwinner
> A523 SoC family. The SPI controller is almost the same as the ones in
> previous generations, except that it moved the "RX buffer count"
> register field to a separate register, and that register now reports
> the total count for RX buffer and FIFO.
>
> In practice the driver has never cared about the buffer count, but if
> any implementation were to use it, this counts as a non-backward
> compatible change.
>
> Also, one of the SPI controllers supports DBI mode, acting as a display
> interface. There is no infrastructure for DBI interface controllers in
> the kernel, so only a separate compatible is added for it.
>
> Patch 1 adds compatible strings for the new variants.
>
> Patch 2 adds driver support for the new SPI controller variant.
>
> Patch 3 adds device nodes for the SPI controllers to the dtsi file,
> along with pinmux settings for spi0 on the PC pins, a common usage for
> SPI-NOR flashes to boot from.
>
> Patch 4 enables the SPI-NOR flash found on the Radxa Cubie A5E.

As pointed out to me on IRC, this change targets the Orangepi 4A, not
the Radxa Cubie A5E. The latter has circuits for SPI-NOR, but the whole
block is left unpopulated.

ChenYu

>
> Please take a look and try it out.
>
>
> Thanks
> ChenYu
>
>
> Chen-Yu Tsai (4):
>   spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers
>   spi: sun6i: Support A523's SPI controllers
>   arm64: dts: allwinner: sun55i: Add SPI controllers
>   arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash
>
>  .../bindings/spi/allwinner,sun6i-a31-spi.yaml |  4 +
>  .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 94 +++++++++++++++++++
>  .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 15 +++
>  drivers/spi/spi-sun6i.c                       | 11 ++-
>  4 files changed, 120 insertions(+), 4 deletions(-)
>
> --
> 2.47.3
>

Re: (subset) [PATCH 0/4] arm64: allwinner: a523: Support SPI controllers

[Mark Brown]

On Sun, 21 Dec 2025 19:05:07 +0800, Chen-Yu Tsai wrote:
> This series adds support for the SPI controllers found in the Allwinner
> A523 SoC family. The SPI controller is almost the same as the ones in
> previous generations, except that it moved the "RX buffer count"
> register field to a separate register, and that register now reports
> the total count for RX buffer and FIFO.
> 
> In practice the driver has never cared about the buffer count, but if
> any implementation were to use it, this counts as a non-backward
> compatible change.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/4] spi: dt-bindings: sun6i: Add compatibles for A523's SPI controllers
      commit: e0c8755d44eb85afd40100586076c3dc4b62ee3b
[2/4] spi: sun6i: Support A523's SPI controllers
      commit: c81f30bde5b0449d9d82d31a66f0ffd608e610b5

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

Re: (subset) [PATCH 0/4] arm64: allwinner: a523: Support SPI controllers

[Chen-Yu Tsai]

On Sun, 21 Dec 2025 19:05:07 +0800, Chen-Yu Tsai wrote:
> This series adds support for the SPI controllers found in the Allwinner
> A523 SoC family. The SPI controller is almost the same as the ones in
> previous generations, except that it moved the "RX buffer count"
> register field to a separate register, and that register now reports
> the total count for RX buffer and FIFO.
> 
> In practice the driver has never cared about the buffer count, but if
> any implementation were to use it, this counts as a non-backward
> compatible change.
> 
> [...]

Applied to sunxi/dt-for-6.20 in local tree, thanks!

[3/4] arm64: dts: allwinner: sun55i: Add SPI controllers
      commit: 1bec3bd1f839f269dfdec3c635dd2afe15e30995
[4/4] arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash
      commit: bd14ba160bbe863e7b7bc489fd947ae1cdc03047

Best regards,
-- 
Chen-Yu Tsai <wens@kernel.org>