[PATCH RFC] dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt

[Guodong Xu <guodong@riscstar.com>]

The descriptions for h, svinval, svnapot, and svpbmt extensions currently
reference the "20191213 version of the privileged ISA specification".
While an Unprivileged ISA document exists with that date, there is no
corresponding ratified Privileged ISA specification.

These extensions were ratified in the RISC-V Instruction Set Manual,
Volume II: Privileged Architecture, Version 20211203. Update the
descriptions to reference the correct specification version.

RISC-V International hosts a website [1] for ratified specifications.
Following the "Ratified ISA Specifications", historical versions of
Volume II Privileged ISA can be found.

Link: https://riscv.org/specifications/ratified/ [1]
Signed-off-by: Guodong Xu <guodong@riscstar.com>
---
I'm not sure the 20191213 version has been removed or there are other
reasons. But since RISC-V International is the official source for such
documents, I think the version history in their website should be
respected.

I checked two sources about the history verisons of ISA Volume II Privileged:
Link: https://riscv.atlassian.net/wiki/spaces/HOME/pages/805568665/The+RISC-V+Instruction+Set+Manual+Volume+II+Privileged+ISA#History [1]
Link: https://github.com/riscv/riscv-isa-manual/releases [2]

There is no 20191213 version of ratified privileged architecture in
both.

Actually, in version 20211203 of the Volume II of prvileged architecture, it
listed the following extensions:
 - Svnapot Extension 1.0 Ratified
 - Svpbmt Extension 1.0 Ratified
 - Svinval Extension 1.0 Ratified
 - Hypervisor ISA 1.0 Ratified

That's the first time the above extensions appear in ISA Volume II
Privileged Specmification.

The version before 20211203 is v1.11 (Version 20190608-Priv-MSU-Ratified),
which contains only a draft version of Hypervisor extension, and no
mentioning of Svnapot, Svpbmt and Svinval.
---
 .../devicetree/bindings/riscv/extensions.yaml         | 19 +++++++++++--------
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index 565cb2cbb49b552959392810a9b731b43346a594..6a4697b36b8d540ac14bcad6373ffcf3db13d3c0 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -117,8 +117,9 @@ properties:
 
         - const: h
           description:
-            The standard H extension for hypervisors as ratified in the 20191213
-            version of the privileged ISA specification.
+            The standard H extension for hypervisors as ratified in the RISC-V
+            Instruction Set Manual, Volume II Privileged Architecture,
+            Document Version 20211203.
 
         # multi-letter extensions, sorted alphanumerically
         - const: smaia
@@ -202,20 +203,22 @@ properties:
         - const: svinval
           description:
             The standard Svinval supervisor-level extension for fine-grained
-            address-translation cache invalidation as ratified in the 20191213
-            version of the privileged ISA specification.
+            address-translation cache invalidation as ratified in the RISC-V
+            Instruction Set Manual, Volume II Privileged Architecture,
+            Document Version 20211203.
 
         - const: svnapot
           description:
             The standard Svnapot supervisor-level extensions for napot
-            translation contiguity as ratified in the 20191213 version of the
-            privileged ISA specification.
+            translation contiguity as ratified in the RISC-V Instruction Set
+            Manual, Volume II Privileged Architecture, Document Version
+            20211203.
 
         - const: svpbmt
           description:
             The standard Svpbmt supervisor-level extensions for page-based
-            memory types as ratified in the 20191213 version of the privileged
-            ISA specification.
+            memory types as ratified in the RISC-V Instruction Set Manual,
+            Volume II Privileged Architecture, Document Version 20211203.
 
         - const: svrsw60t59b
           description:

---
base-commit: 9448598b22c50c8a5bb77a9103e2d49f134c9578
change-id: 20251223-h-description-2b9adfb2fe8f

Best regards,
-- 
Guodong Xu <guodong@riscstar.com>