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Wed, 24 Dec 2025 22:24:53 -0800 (PST) From: Guodong Xu Date: Thu, 25 Dec 2025 14:24:20 +0800 Subject: [PATCH v2] dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251225-h-description-v2-1-b0c66080c704@riscstar.com> X-B4-Tracking: v=1; b=H4sIAJPYTGkC/3WNPQ+CMBCG/wq52Rp6xIQ6aVgcHdwMQ1uucoNA7 gjREP67Dbvj+/W8KygJk8K5WEFoYeVxyAIPBcTeDy8y3GUNWOLJIlamNx1pFJ7m3DQYnO9SwER 1gryZhBJ/dt4T7tdHc4M22z3rPMp3f1nsHv4BLtZY4+pA3lWhdNZdhDXq7OUYxze027b9AFpCD ye0AAAA X-Change-ID: 20251223-h-description-2b9adfb2fe8f To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: Paul Walmsley , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , Guodong Xu X-Mailer: b4 0.14.2 The descriptions for h, svinval, svnapot, and svpbmt extensions currently reference the "20191213 version of the privileged ISA specification". While an Unprivileged ISA document exists with that date, there is no corresponding ratified Privileged ISA specification. These extensions were ratified in the RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 20211203. Update the descriptions to reference the correct specification version. RISC-V International hosts a website [1] for ratified specifications. Following the "Ratified ISA Specifications", historical versions of Volume II Privileged ISA can be found. Link: https://riscv.org/specifications/ratified/ [1] Fixes: aeb71e42caae ("dt-bindings: riscv: deprecate riscv,isa") Acked-by: Conor Dooley Signed-off-by: Guodong Xu --- Changes in v2: - Added Fixes tag. - Added Acked-by from Conor. - Link to v1: https://lore.kernel.org/r/20251223-h-description-v1-1-98bea93b0919@riscstar.com --- .../devicetree/bindings/riscv/extensions.yaml | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 565cb2cbb49b552959392810a9b731b43346a594..6a4697b36b8d540ac14bcad6373ffcf3db13d3c0 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -117,8 +117,9 @@ properties: - const: h description: - The standard H extension for hypervisors as ratified in the 20191213 - version of the privileged ISA specification. + The standard H extension for hypervisors as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. # multi-letter extensions, sorted alphanumerically - const: smaia @@ -202,20 +203,22 @@ properties: - const: svinval description: The standard Svinval supervisor-level extension for fine-grained - address-translation cache invalidation as ratified in the 20191213 - version of the privileged ISA specification. + address-translation cache invalidation as ratified in the RISC-V + Instruction Set Manual, Volume II Privileged Architecture, + Document Version 20211203. - const: svnapot description: The standard Svnapot supervisor-level extensions for napot - translation contiguity as ratified in the 20191213 version of the - privileged ISA specification. + translation contiguity as ratified in the RISC-V Instruction Set + Manual, Volume II Privileged Architecture, Document Version + 20211203. - const: svpbmt description: The standard Svpbmt supervisor-level extensions for page-based - memory types as ratified in the 20191213 version of the privileged - ISA specification. + memory types as ratified in the RISC-V Instruction Set Manual, + Volume II Privileged Architecture, Document Version 20211203. - const: svrsw60t59b description: --- base-commit: 9448598b22c50c8a5bb77a9103e2d49f134c9578 change-id: 20251223-h-description-2b9adfb2fe8f Best regards, -- Guodong Xu