From: Nishanth Menon <nm@ti.com>
To: Michael Walle <mwalle@kernel.org>
Cc: Frank Binns <frank.binns@imgtec.com>,
Matt Coster <matt.coster@imgtec.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Andrew Davis <afd@ti.com>,
Santosh Shilimkar <ssantosh@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>, Randolph Sapp <rs@ti.com>,
<linux-clk@vger.kernel.org>, <dri-devel@lists.freedesktop.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 2/4] clk: keystone: don't cache clock rate
Date: Tue, 30 Dec 2025 14:12:33 -0600 [thread overview]
Message-ID: <20251230201233.n36d5fiensqyb6fc@splice> (raw)
In-Reply-To: <20251223124729.2482877-3-mwalle@kernel.org>
On 13:47-20251223, Michael Walle wrote:
> The TISCI firmware will return 0 if the clock or consumer is not
> enabled although there is a stored value in the firmware. IOW a call to
> set rate will work but at get rate will always return 0 if the clock is
> disabled.
> The clk framework will try to cache the clock rate when it's requested
> by a consumer. If the clock or consumer is not enabled at that point,
> the cached value is 0, which is wrong. Thus, disable the cache
> altogether.
>
> Signed-off-by: Michael Walle <mwalle@kernel.org>
> Reviewed-by: Kevin Hilman <khilman@baylibre.com>
> Reviewed-by: Randolph Sapp <rs@ti.com>
> ---
> drivers/clk/keystone/sci-clk.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> index 9d5071223f4c..0a1565fdbb3b 100644
> --- a/drivers/clk/keystone/sci-clk.c
> +++ b/drivers/clk/keystone/sci-clk.c
> @@ -333,6 +333,14 @@ static int _sci_clk_build(struct sci_clk_provider *provider,
>
> init.ops = &sci_clk_ops;
> init.num_parents = sci_clk->num_parents;
> +
> + /*
> + * A clock rate query to the SCI firmware will return 0 if either the
> + * clock itself is disabled or the attached device/consumer is disabled.
> + * This makes it inherently unsuitable for the caching of the clk
> + * framework.
> + */
> + init.flags = CLK_GET_RATE_NOCACHE;
> sci_clk->hw.init = &init;
>
> ret = devm_clk_hw_register(provider->dev, &sci_clk->hw);
> --
> 2.47.3
>
Reviewed-by: Nishanth Menon <nm@ti.com>
I wish there was a better scheme, but inherently, just like SCMI and
other systems where power management co-processor controls clocks, there
is no real feasible caching scheme I can think of. I wonder if Stephen
or others have a thought on this?
That said, I wonder if we need fixes tag to this? I am sure there are
other clocks susceptible to this as well. I wonder if
commit 3c13933c6033 ("clk: keystone: sci-clk: add support for
dynamically probing clocks") is the appropriate tag?
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
https://ti.com/opensource
next prev parent reply other threads:[~2025-12-30 20:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-23 12:47 [PATCH v2 0/4] drm/imagination: add AM62P/AM67A/J722S support Michael Walle
2025-12-23 12:47 ` [PATCH v2 1/4] dt-bindings: gpu: img: Add AM62P SoC specific compatible Michael Walle
2025-12-23 12:47 ` [PATCH v2 2/4] clk: keystone: don't cache clock rate Michael Walle
2025-12-30 20:12 ` Nishanth Menon [this message]
2026-01-02 7:55 ` Michael Walle
2025-12-23 12:47 ` [PATCH v2 3/4] arm64: dts: ti: add GPU node Michael Walle
2025-12-23 12:47 ` [PATCH v2 4/4] arm64: dts: ti: sa67: set the GPU clock to 800MHz Michael Walle
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