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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-47be273e4d5sm696441795e9.6.2025.12.31.02.56.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Dec 2025 02:56:53 -0800 (PST) Date: Wed, 31 Dec 2025 10:56:51 +0000 From: David Laight To: Junhui Liu Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Troy Mitchell , Brian Masney Subject: Re: [PATCH v4 1/6] clk: correct clk_div_mask() return value for width == 32 Message-ID: <20251231105651.430f75f8@pumpkin> In-Reply-To: <20251231-dr1v90-cru-v4-1-1db8c877eb91@pigmoral.tech> References: <20251231-dr1v90-cru-v4-0-1db8c877eb91@pigmoral.tech> <20251231-dr1v90-cru-v4-1-1db8c877eb91@pigmoral.tech> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 31 Dec 2025 14:40:05 +0800 Junhui Liu wrote: > The macro clk_div_mask() currently wraps to zero when width is 32 due to > 1 << 32 being undefined behavior. This leads to incorrect mask generation > and prevents correct retrieval of register field values for 32-bit-wide > dividers. > > Although it is unlikely to exhaust all U32_MAX div, some clock IPs may rely > on a 32-bit val entry in their div_table to match a div, so providing a > full 32-bit mask is necessary. > > Fix this by casting 1 to long, ensuring proper behavior for valid widths up > to 32. > > Reviewed-by: Troy Mitchell > Reviewed-by: Brian Masney > Signed-off-by: Junhui Liu > --- > include/linux/clk-provider.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h > index 630705a47129..a651ccaf1b44 100644 > --- a/include/linux/clk-provider.h > +++ b/include/linux/clk-provider.h > @@ -720,7 +720,7 @@ struct clk_divider { > spinlock_t *lock; > }; > > -#define clk_div_mask(width) ((1 << (width)) - 1) > +#define clk_div_mask(width) ((1L << (width)) - 1) That makes no difference on 32bit architectures. I also suspect you need to ensure the value is 'unsigned int'. If you can guarantee that width isn't zero (probably true), then: #define clk_div_mask(width) ((2u << (width) - 1) - 1) should have the desired value for widths 1..32. It probably adds an extra instruction. (OTOH so does passing width as 'u8'.) David > #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) > > #define CLK_DIVIDER_ONE_BASED BIT(0) >