* [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
@ 2026-01-02 14:00 Dinh Nguyen
2026-01-02 14:00 ` [PATCH 2/2] ARM: dts: socfpga: arria10: remove underscore in node names Dinh Nguyen
2026-01-02 14:51 ` [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Rob Herring
0 siblings, 2 replies; 3+ messages in thread
From: Dinh Nguyen @ 2026-01-02 14:00 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt; +Cc: dinguyen, devicetree
The node names in the these file should be using a hyphen, not an
underscore as warned by 'dtc W=2'.
sed command used : sed -E ':a; s/(:.*)_/\1-/; ta'
Used dtx_diff to check before/after dtbs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 106 +++++++++----------
1 file changed, 53 insertions(+), 53 deletions(-)
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
index 5dc8d33e8ad7..d439fc3e17a7 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
@@ -132,17 +132,17 @@ osc2: osc2 {
compatible = "fixed-clock";
};
- f2s_periph_ref_clk: f2s_periph_ref_clk {
+ f2s_periph_ref_clk: f2s-periph-ref-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
- f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+ f2s_sdram_ref_clk: f2s-sdram-ref-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
- main_pll: main_pll@40 {
+ main_pll: main-pll@40 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -166,7 +166,7 @@ mainclk: mainclk@4c {
reg = <0x4C>;
};
- dbg_base_clk: dbg_base_clk@50 {
+ dbg_base_clk: dbg-base-clk@50 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>, <&osc1>;
@@ -174,21 +174,21 @@ dbg_base_clk: dbg_base_clk@50 {
reg = <0x50>;
};
- main_qspi_clk: main_qspi_clk@54 {
+ main_qspi_clk: main-qspi-clk@54 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x54>;
};
- main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
+ main_nand_sdmmc_clk: main-nand-sdmmc-clk@58 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x58>;
};
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
+ cfg_h2f_usr0_clk: cfg-h2f-usr0-clk@5c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -196,7 +196,7 @@ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
};
};
- periph_pll: periph_pll@80 {
+ periph_pll: periph-pll@80 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -204,42 +204,42 @@ periph_pll: periph_pll@80 {
clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
reg = <0x80>;
- emac0_clk: emac0_clk@88 {
+ emac0_clk: emac0-clk@88 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x88>;
};
- emac1_clk: emac1_clk@8c {
+ emac1_clk: emac1-clk@8c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x8C>;
};
- per_qspi_clk: per_qsi_clk@90 {
+ per_qspi_clk: per-qsi-clk@90 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x90>;
};
- per_nand_mmc_clk: per_nand_mmc_clk@94 {
+ per_nand_mmc_clk: per-nand-mmc-clk@94 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x94>;
};
- per_base_clk: per_base_clk@98 {
+ per_base_clk: per-base-clk@98 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x98>;
};
- h2f_usr1_clk: h2f_usr1_clk@9c {
+ h2f_usr1_clk: h2f-usr1-clk@9c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
@@ -247,7 +247,7 @@ h2f_usr1_clk: h2f_usr1_clk@9c {
};
};
- sdram_pll: sdram_pll@c0 {
+ sdram_pll: sdram-pll@c0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -255,28 +255,28 @@ sdram_pll: sdram_pll@c0 {
clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
reg = <0xC0>;
- ddr_dqs_clk: ddr_dqs_clk@c8 {
+ ddr_dqs_clk: ddr-dqs-clk@c8 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xC8>;
};
- ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
+ ddr_2x_dqs_clk: ddr-2x-dqs-clk@cc {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xCC>;
};
- ddr_dq_clk: ddr_dq_clk@d0 {
+ ddr_dq_clk: ddr-dq-clk@d0 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
reg = <0xD0>;
};
- h2f_usr2_clk: h2f_usr2_clk@d4 {
+ h2f_usr2_clk: h2f-usr2-clk@d4 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
@@ -284,35 +284,35 @@ h2f_usr2_clk: h2f_usr2_clk@d4 {
};
};
- mpu_periph_clk: mpu_periph_clk {
+ mpu_periph_clk: mpu-periph-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <4>;
};
- mpu_l2_ram_clk: mpu_l2_ram_clk {
+ mpu_l2_ram_clk: mpu-l2-ram-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <2>;
};
- l4_main_clk: l4_main_clk {
+ l4_main_clk: l4-main-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>;
clk-gate = <0x60 0>;
};
- l3_main_clk: l3_main_clk {
+ l3_main_clk: l3-main-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&mainclk>;
fixed-divider = <1>;
};
- l3_mp_clk: l3_mp_clk {
+ l3_mp_clk: l3-mp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>;
@@ -320,14 +320,14 @@ l3_mp_clk: l3_mp_clk {
clk-gate = <0x60 1>;
};
- l3_sp_clk: l3_sp_clk {
+ l3_sp_clk: l3-sp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&l3_mp_clk>;
div-reg = <0x64 2 2>;
};
- l4_mp_clk: l4_mp_clk {
+ l4_mp_clk: l4-mp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>, <&per_base_clk>;
@@ -335,7 +335,7 @@ l4_mp_clk: l4_mp_clk {
clk-gate = <0x60 2>;
};
- l4_sp_clk: l4_sp_clk {
+ l4_sp_clk: l4-sp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>, <&per_base_clk>;
@@ -343,7 +343,7 @@ l4_sp_clk: l4_sp_clk {
clk-gate = <0x60 3>;
};
- dbg_at_clk: dbg_at_clk {
+ dbg_at_clk: dbg-at-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
@@ -351,7 +351,7 @@ dbg_at_clk: dbg_at_clk {
clk-gate = <0x60 4>;
};
- dbg_clk: dbg_clk {
+ dbg_clk: dbg-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_at_clk>;
@@ -359,7 +359,7 @@ dbg_clk: dbg_clk {
clk-gate = <0x60 5>;
};
- dbg_trace_clk: dbg_trace_clk {
+ dbg_trace_clk: dbg-trace-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
@@ -367,42 +367,42 @@ dbg_trace_clk: dbg_trace_clk {
clk-gate = <0x60 6>;
};
- dbg_timer_clk: dbg_timer_clk {
+ dbg_timer_clk: dbg-timer-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
clk-gate = <0x60 7>;
};
- cfg_clk: cfg_clk {
+ cfg_clk: cfg-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&cfg_h2f_usr0_clk>;
clk-gate = <0x60 8>;
};
- h2f_user0_clk: h2f_user0_clk {
+ h2f_user0_clk: h2f-user0-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&cfg_h2f_usr0_clk>;
clk-gate = <0x60 9>;
};
- emac_0_clk: emac_0_clk {
+ emac_0_clk: emac-0-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&emac0_clk>;
clk-gate = <0xa0 0>;
};
- emac_1_clk: emac_1_clk {
+ emac_1_clk: emac-1-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&emac1_clk>;
clk-gate = <0xa0 1>;
};
- usb_mp_clk: usb_mp_clk {
+ usb_mp_clk: usb-mp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -410,7 +410,7 @@ usb_mp_clk: usb_mp_clk {
div-reg = <0xa4 0 3>;
};
- spi_m_clk: spi_m_clk {
+ spi_m_clk: spi-m-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -418,7 +418,7 @@ spi_m_clk: spi_m_clk {
div-reg = <0xa4 3 3>;
};
- can0_clk: can0_clk {
+ can0_clk: can0-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -426,7 +426,7 @@ can0_clk: can0_clk {
div-reg = <0xa4 6 3>;
};
- can1_clk: can1_clk {
+ can1_clk: can1-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -434,7 +434,7 @@ can1_clk: can1_clk {
div-reg = <0xa4 9 3>;
};
- gpio_db_clk: gpio_db_clk {
+ gpio_db_clk: gpio-db-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -442,21 +442,21 @@ gpio_db_clk: gpio_db_clk {
div-reg = <0xa8 0 24>;
};
- h2f_user1_clk: h2f_user1_clk {
+ h2f_user1_clk: h2f-user1-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&h2f_usr1_clk>;
clk-gate = <0xa0 7>;
};
- sdmmc_clk: sdmmc_clk {
+ sdmmc_clk: sdmmc-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
clk-gate = <0xa0 8>;
};
- sdmmc_clk_divided: sdmmc_clk_divided {
+ sdmmc_clk_divided: sdmmc-clk-divided {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&sdmmc_clk>;
@@ -464,21 +464,21 @@ sdmmc_clk_divided: sdmmc_clk_divided {
fixed-divider = <4>;
};
- nand_x_clk: nand_x_clk {
+ nand_x_clk: nand-x-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
clk-gate = <0xa0 9>;
};
- nand_ecc_clk: nand_ecc_clk {
+ nand_ecc_clk: nand-ecc-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&nand_x_clk>;
clk-gate = <0xa0 9>;
};
- nand_clk: nand_clk {
+ nand_clk: nand-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&nand_x_clk>;
@@ -486,35 +486,35 @@ nand_clk: nand_clk {
fixed-divider = <4>;
};
- qspi_clk: qspi_clk {
+ qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
clk-gate = <0xa0 11>;
};
- ddr_dqs_clk_gate: ddr_dqs_clk_gate {
+ ddr_dqs_clk_gate: ddr-dqs-clk-gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dqs_clk>;
clk-gate = <0xd8 0>;
};
- ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
+ ddr_2x_dqs_clk_gate: ddr-2x-dqs-clk-gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_2x_dqs_clk>;
clk-gate = <0xd8 1>;
};
- ddr_dq_clk_gate: ddr_dq_clk_gate {
+ ddr_dq_clk_gate: ddr-dq-clk-gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dq_clk>;
clk-gate = <0xd8 2>;
};
- h2f_user2_clk: h2f_user2_clk {
+ h2f_user2_clk: h2f-user2-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&h2f_usr2_clk>;
@@ -524,7 +524,7 @@ h2f_user2_clk: h2f_user2_clk {
};
};
- fpga_bridge0: fpga_bridge@ff400000 {
+ fpga_bridge0: fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
@@ -532,7 +532,7 @@ fpga_bridge0: fpga_bridge@ff400000 {
status = "disabled";
};
- fpga_bridge1: fpga_bridge@ff500000 {
+ fpga_bridge1: fpga-bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
--
2.42.0.411.g813d9a9188
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] ARM: dts: socfpga: arria10: remove underscore in node names
2026-01-02 14:00 [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Dinh Nguyen
@ 2026-01-02 14:00 ` Dinh Nguyen
2026-01-02 14:51 ` [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Dinh Nguyen @ 2026-01-02 14:00 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt; +Cc: dinguyen, devicetree
The node names should be using a hyphen not an underscore(dtc with W=2
warns about them).
sec command used : sed -E ':a; s/(:.*)_/\1-/; ta'
Also used dtx_diff to check before/after dtbs.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
.../dts/intel/socfpga/socfpga_arria10.dtsi | 86 +++++++++----------
1 file changed, 43 insertions(+), 43 deletions(-)
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
index a53a94678df2..1b9d17673bd5 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi
@@ -97,17 +97,17 @@ clocks {
#address-cells = <1>;
#size-cells = <0>;
- cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
- cb_intosc_ls_clk: cb_intosc_ls_clk {
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
- f2s_free_clk: f2s_free_clk {
+ f2s_free_clk: f2s-free-clk {
#clock-cells = <0>;
compatible = "fixed-clock";
};
@@ -117,7 +117,7 @@ osc1: osc1 {
compatible = "fixed-clock";
};
- main_pll: main_pll@40 {
+ main_pll: main-pll@40 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -126,49 +126,49 @@ main_pll: main_pll@40 {
<&f2s_free_clk>;
reg = <0x40>;
- main_mpu_base_clk: main_mpu_base_clk {
+ main_mpu_base_clk: main-mpu-base-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x140 0 11>;
};
- main_noc_base_clk: main_noc_base_clk {
+ main_noc_base_clk: main-noc-base-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
div-reg = <0x144 0 11>;
};
- main_emaca_clk: main_emaca_clk@68 {
+ main_emaca_clk: main-emaca-clk@68 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x68>;
};
- main_emacb_clk: main_emacb_clk@6c {
+ main_emacb_clk: main-emacb-clk@6c {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x6C>;
};
- main_emac_ptp_clk: main_emac_ptp_clk@70 {
+ main_emac_ptp_clk: main-emac-ptp-clk@70 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x70>;
};
- main_gpio_db_clk: main_gpio_db_clk@74 {
+ main_gpio_db_clk: main-gpio-db-clk@74 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x74>;
};
- main_sdmmc_clk: main_sdmmc_clk@78 {
+ main_sdmmc_clk: main-sdmmc-clk@78 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk"
;
@@ -176,28 +176,28 @@ main_sdmmc_clk: main_sdmmc_clk@78 {
reg = <0x78>;
};
- main_s2f_usr0_clk: main_s2f_usr0_clk@7c {
+ main_s2f_usr0_clk: main-s2f-usr0-clk@7c {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x7C>;
};
- main_s2f_usr1_clk: main_s2f_usr1_clk@80 {
+ main_s2f_usr1_clk: main-s2f-usr1-clk@80 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x80>;
};
- main_hmc_pll_ref_clk: main_hmc_pll_ref_clk@84 {
+ main_hmc_pll_ref_clk: main-hmc-pll-ref-clk@84 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
reg = <0x84>;
};
- main_periph_ref_clk: main_periph_ref_clk@9c {
+ main_periph_ref_clk: main-periph-ref-clk@9c {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_pll>;
@@ -205,7 +205,7 @@ main_periph_ref_clk: main_periph_ref_clk@9c {
};
};
- periph_pll: periph_pll@c0 {
+ periph_pll: periph-pll@c0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -214,70 +214,70 @@ periph_pll: periph_pll@c0 {
<&f2s_free_clk>, <&main_periph_ref_clk>;
reg = <0xC0>;
- peri_mpu_base_clk: peri_mpu_base_clk {
+ peri_mpu_base_clk: peri-mpu-base-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x140 16 11>;
};
- peri_noc_base_clk: peri_noc_base_clk {
+ peri_noc_base_clk: peri-noc-base-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
div-reg = <0x144 16 11>;
};
- peri_emaca_clk: peri_emaca_clk@e8 {
+ peri_emaca_clk: peri-emaca-clk@e8 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xE8>;
};
- peri_emacb_clk: peri_emacb_clk@ec {
+ peri_emacb_clk: peri-emacb-clk@ec {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xEC>;
};
- peri_emac_ptp_clk: peri_emac_ptp_clk@f0 {
+ peri_emac_ptp_clk: peri-emac-ptp-clk@f0 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF0>;
};
- peri_gpio_db_clk: peri_gpio_db_clk@f4 {
+ peri_gpio_db_clk: peri-gpio-db-clk@f4 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF4>;
};
- peri_sdmmc_clk: peri_sdmmc_clk@f8 {
+ peri_sdmmc_clk: peri-sdmmc-clk@f8 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xF8>;
};
- peri_s2f_usr0_clk: peri_s2f_usr0_clk@fc {
+ peri_s2f_usr0_clk: peri-s2f-usr0-clk@fc {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0xFC>;
};
- peri_s2f_usr1_clk: peri_s2f_usr1_clk@100 {
+ peri_s2f_usr1_clk: peri-s2f-usr1-clk@100 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
reg = <0x100>;
};
- peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
+ peri_hmc_pll_ref_clk: peri-hmc-pll-ref-clk@104 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&periph_pll>;
@@ -285,7 +285,7 @@ peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk@104 {
};
};
- mpu_free_clk: mpu_free_clk@60 {
+ mpu_free_clk: mpu-free-clk@60 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
@@ -294,7 +294,7 @@ mpu_free_clk: mpu_free_clk@60 {
reg = <0x60>;
};
- noc_free_clk: noc_free_clk@64 {
+ noc_free_clk: noc-free-clk@64 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
@@ -303,7 +303,7 @@ noc_free_clk: noc_free_clk@64 {
reg = <0x64>;
};
- s2f_user1_free_clk: s2f_user1_free_clk@104 {
+ s2f_user1_free_clk: s2f-user1-free-clk@104 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
@@ -312,7 +312,7 @@ s2f_user1_free_clk: s2f_user1_free_clk@104 {
reg = <0x104>;
};
- sdmmc_free_clk: sdmmc_free_clk@f8 {
+ sdmmc_free_clk: sdmmc-free-clk@f8 {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
@@ -322,14 +322,14 @@ sdmmc_free_clk: sdmmc_free_clk@f8 {
reg = <0xF8>;
};
- l4_sys_free_clk: l4_sys_free_clk {
+ l4_sys_free_clk: l4-sys-free-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-perip-clk";
clocks = <&noc_free_clk>;
fixed-divider = <4>;
};
- l4_main_clk: l4_main_clk {
+ l4_main_clk: l4-main-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
@@ -337,7 +337,7 @@ l4_main_clk: l4_main_clk {
clk-gate = <0x48 1>;
};
- l4_mp_clk: l4_mp_clk {
+ l4_mp_clk: l4-mp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
@@ -345,7 +345,7 @@ l4_mp_clk: l4_mp_clk {
clk-gate = <0x48 2>;
};
- l4_sp_clk: l4_sp_clk {
+ l4_sp_clk: l4-sp-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&noc_free_clk>;
@@ -353,7 +353,7 @@ l4_sp_clk: l4_sp_clk {
clk-gate = <0x48 3>;
};
- mpu_periph_clk: mpu_periph_clk {
+ mpu_periph_clk: mpu-periph-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&mpu_free_clk>;
@@ -361,35 +361,35 @@ mpu_periph_clk: mpu_periph_clk {
clk-gate = <0x48 0>;
};
- sdmmc_clk: sdmmc_clk {
+ sdmmc_clk: sdmmc-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&sdmmc_free_clk>;
clk-gate = <0xC8 5>;
};
- qspi_clk: qspi_clk {
+ qspi_clk: qspi-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_main_clk>;
clk-gate = <0xC8 11>;
};
- nand_x_clk: nand_x_clk {
+ nand_x_clk: nand-x-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 10>;
};
- nand_ecc_clk: nand_ecc_clk {
+ nand_ecc_clk: nand-ecc-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&nand_x_clk>;
clk-gate = <0xC8 10>;
};
- nand_clk: nand_clk {
+ nand_clk: nand-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&nand_x_clk>;
@@ -397,21 +397,21 @@ nand_clk: nand_clk {
clk-gate = <0xC8 10>;
};
- spi_m_clk: spi_m_clk {
+ spi_m_clk: spi-m-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_main_clk>;
clk-gate = <0xC8 9>;
};
- usb_clk: usb_clk {
+ usb_clk: usb-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&l4_mp_clk>;
clk-gate = <0xC8 8>;
};
- s2f_usr1_clk: s2f_usr1_clk {
+ s2f_usr1_clk: s2f-usr1-clk {
#clock-cells = <0>;
compatible = "altr,socfpga-a10-gate-clk";
clocks = <&peri_s2f_usr1_clk>;
--
2.42.0.411.g813d9a9188
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
2026-01-02 14:00 [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Dinh Nguyen
2026-01-02 14:00 ` [PATCH 2/2] ARM: dts: socfpga: arria10: remove underscore in node names Dinh Nguyen
@ 2026-01-02 14:51 ` Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Rob Herring @ 2026-01-02 14:51 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: krzk+dt, conor+dt, devicetree
On Fri, Jan 2, 2026 at 8:01 AM Dinh Nguyen <dinguyen@kernel.org> wrote:
>
> The node names in the these file should be using a hyphen, not an
> underscore as warned by 'dtc W=2'.
>
> sed command used : sed -E ':a; s/(:.*)_/\1-/; ta'
>
> Used dtx_diff to check before/after dtbs.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 106 +++++++++----------
> 1 file changed, 53 insertions(+), 53 deletions(-)
>
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
> index 5dc8d33e8ad7..d439fc3e17a7 100644
> --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
> @@ -132,17 +132,17 @@ osc2: osc2 {
> compatible = "fixed-clock";
> };
>
> - f2s_periph_ref_clk: f2s_periph_ref_clk {
> + f2s_periph_ref_clk: f2s-periph-ref-clk {
The preferred name is "clock-<freq-in-hz>" if you know the frequency.
> #clock-cells = <0>;
> compatible = "fixed-clock";
> };
>
> - f2s_sdram_ref_clk: f2s_sdram_ref_clk {
> + f2s_sdram_ref_clk: f2s-sdram-ref-clk {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> };
>
> - main_pll: main_pll@40 {
> + main_pll: main-pll@40 {
clock-controller@40
Similar on the others with unit-addresses.
> #address-cells = <1>;
> #size-cells = <0>;
> #clock-cells = <0>;
> @@ -166,7 +166,7 @@ mainclk: mainclk@4c {
It looks like it is not just underscores.
> reg = <0x4C>;
> };
>
> - dbg_base_clk: dbg_base_clk@50 {
> + dbg_base_clk: dbg-base-clk@50 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&main_pll>, <&osc1>;
> @@ -174,21 +174,21 @@ dbg_base_clk: dbg_base_clk@50 {
> reg = <0x50>;
> };
>
> - main_qspi_clk: main_qspi_clk@54 {
> + main_qspi_clk: main-qspi-clk@54 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&main_pll>;
> reg = <0x54>;
> };
>
> - main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
> + main_nand_sdmmc_clk: main-nand-sdmmc-clk@58 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&main_pll>;
> reg = <0x58>;
> };
>
> - cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
> + cfg_h2f_usr0_clk: cfg-h2f-usr0-clk@5c {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&main_pll>;
> @@ -196,7 +196,7 @@ cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
> };
> };
>
> - periph_pll: periph_pll@80 {
> + periph_pll: periph-pll@80 {
> #address-cells = <1>;
> #size-cells = <0>;
> #clock-cells = <0>;
> @@ -204,42 +204,42 @@ periph_pll: periph_pll@80 {
> clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
> reg = <0x80>;
>
> - emac0_clk: emac0_clk@88 {
> + emac0_clk: emac0-clk@88 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&periph_pll>;
> reg = <0x88>;
> };
>
> - emac1_clk: emac1_clk@8c {
> + emac1_clk: emac1-clk@8c {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&periph_pll>;
> reg = <0x8C>;
> };
>
> - per_qspi_clk: per_qsi_clk@90 {
> + per_qspi_clk: per-qsi-clk@90 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&periph_pll>;
> reg = <0x90>;
> };
>
> - per_nand_mmc_clk: per_nand_mmc_clk@94 {
> + per_nand_mmc_clk: per-nand-mmc-clk@94 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&periph_pll>;
> reg = <0x94>;
> };
>
> - per_base_clk: per_base_clk@98 {
> + per_base_clk: per-base-clk@98 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&periph_pll>;
> reg = <0x98>;
> };
>
> - h2f_usr1_clk: h2f_usr1_clk@9c {
> + h2f_usr1_clk: h2f-usr1-clk@9c {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&periph_pll>;
> @@ -247,7 +247,7 @@ h2f_usr1_clk: h2f_usr1_clk@9c {
> };
> };
>
> - sdram_pll: sdram_pll@c0 {
> + sdram_pll: sdram-pll@c0 {
> #address-cells = <1>;
> #size-cells = <0>;
> #clock-cells = <0>;
> @@ -255,28 +255,28 @@ sdram_pll: sdram_pll@c0 {
> clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
> reg = <0xC0>;
>
> - ddr_dqs_clk: ddr_dqs_clk@c8 {
> + ddr_dqs_clk: ddr-dqs-clk@c8 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&sdram_pll>;
> reg = <0xC8>;
> };
>
> - ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
> + ddr_2x_dqs_clk: ddr-2x-dqs-clk@cc {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&sdram_pll>;
> reg = <0xCC>;
> };
>
> - ddr_dq_clk: ddr_dq_clk@d0 {
> + ddr_dq_clk: ddr-dq-clk@d0 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&sdram_pll>;
> reg = <0xD0>;
> };
>
> - h2f_usr2_clk: h2f_usr2_clk@d4 {
> + h2f_usr2_clk: h2f-usr2-clk@d4 {
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&sdram_pll>;
> @@ -284,35 +284,35 @@ h2f_usr2_clk: h2f_usr2_clk@d4 {
> };
> };
>
> - mpu_periph_clk: mpu_periph_clk {
> + mpu_periph_clk: mpu-periph-clk {
I don't really have a better suggestion on all of these...
> #clock-cells = <0>;
> compatible = "altr,socfpga-perip-clk";
> clocks = <&mpuclk>;
> fixed-divider = <4>;
> };
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2026-01-02 14:51 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2026-01-02 14:00 [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Dinh Nguyen
2026-01-02 14:00 ` [PATCH 2/2] ARM: dts: socfpga: arria10: remove underscore in node names Dinh Nguyen
2026-01-02 14:51 ` [PATCH 1/2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Rob Herring
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