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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Si87D+/o; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Si87D+/o" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 73A02C19422; Mon, 5 Jan 2026 15:46:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1767628017; bh=6g43xgupT7X9snTe66W9SSmrOVZbRjTg76SexCt4z9c=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Si87D+/ouqiUp/V/VfYSNsvLz+wcGQXYrs1TH00tsHqVG41Nh0GT6/LQ3O2ztTuBt i8MTyZcXjm49WCnxVXo6bBF3LB6QsN5aNgUHtoAwUTaDJGwUtzWBKMhdvRbxyphTk4 6BIAPBrXP4Nar22gXW4uNsnvhvyqnq84iD0AAKtCNbd50Y4rCkV5ogB2/z9W97SaQe 2bQud1buFeK5ek2nKMpY0P8eNWsq1jKXNHMe9WikiDRqkFM/dDvpWeQu90O7q6h760 3BjyyRtQc8O5ohyTiC2IgHoMRUExf/DznPKiB/qtiCFd+u2ftX/em7Dye1zSfY2rmZ GYNZf+LFvw0Kw== Date: Mon, 5 Jan 2026 09:46:56 -0600 From: Rob Herring To: Icenowy Zheng Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski , Han Gao , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Subject: Re: [PATCH v4 2/9] dt-bindings: display: add verisilicon,dc Message-ID: <20260105154656.GA2585570-robh@kernel.org> References: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> <20251224161205.1132149-3-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251224161205.1132149-3-zhengxingda@iscas.ac.cn> On Thu, Dec 25, 2025 at 12:11:58AM +0800, Icenowy Zheng wrote: > From: Icenowy Zheng > > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. > > Add a device tree binding for it. > > Depends on the specific DC model, it can have either one or two display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI controllers). > > Signed-off-by: Icenowy Zheng > Signed-off-by: Icenowy Zheng > --- > Changes in v4: > - Added a comment for "verisilicon,dc" that says the ID/revision is > discoverable via registers. > - Removed clock minItems constraint w/o specific compatible strings. > > Changes in v3: > - Added SoC-specific compatible string, and arm the binding with clock / > port checking for the specific SoC (with a 2-output DC). > > Changes in v2: > - Fixed misspelt "versilicon" in title. > - Moved minItems in clock properties to be earlier than items. > - Re-aligned multi-line clocks and resets in example. > > .../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++ > 1 file changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > new file mode 100644 > index 0000000000000..fe64cc1466690 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > @@ -0,0 +1,144 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Verisilicon DC-series display controllers > + > +maintainers: > + - Icenowy Zheng > + > +properties: > + $nodename: > + pattern: "^display@[0-9a-f]+$" > + > + compatible: > + items: > + - enum: > + - thead,th1520-dc8200 > + - const: verisilicon,dc # DC IPs have discoverable ID/revision registers > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: DC Core clock > + - description: DMA AXI bus clock > + - description: Configuration AHB bus clock > + - description: Pixel clock of output 0 > + - description: Pixel clock of output 1 > + > + clock-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + - const: pix0 > + - const: pix1 > + > + resets: > + items: > + - description: DC Core reset > + - description: DMA AXI bus reset > + - description: Configuration AHB bus reset > + > + reset-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: The first output channel , endpoint 0 should be No space before comma. Or perhaps should be a period instead. > + used for DPI format output and endpoint 1 should be used > + for DP format output. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: The second output channel if the DC variant > + supports. Follow the same endpoint addressing rule with > + the first port. > + > + required: > + - port@0 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: thead,th1520-dc8200 > + then: > + properties: > + clocks: > + minItems: 5 That's already implicitly the min. Perhaps you wanted 'minItems: 4' on the clocks and clock-names definitions for versions with only 1 output? > + ports: > + required: > + - port@0 > + - port@1 It is valid to omit these if the output is present, but unused. > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + display@ffef600000 { > + compatible = "thead,th1520-dc8200", "verisilicon,dc"; > + reg = <0xff 0xef600000 0x0 0x100000>; > + interrupts = <93 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk_vo CLK_DPU_CCLK>, > + <&clk_vo CLK_DPU_ACLK>, > + <&clk_vo CLK_DPU_HCLK>, > + <&clk_vo CLK_DPU_PIXELCLK0>, > + <&clk_vo CLK_DPU_PIXELCLK1>; > + clock-names = "core", "axi", "ahb", "pix0", "pix1"; > + resets = <&rst TH1520_RESET_ID_DPU_CORE>, > + <&rst TH1520_RESET_ID_DPU_AXI>, > + <&rst TH1520_RESET_ID_DPU_AHB>; > + reset-names = "core", "axi", "ahb"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + }; > + > + port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + dpu_out_dp1: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&hdmi_in>; > + }; > + }; > + }; > + }; > + }; > -- > 2.52.0 >