* [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
@ 2026-01-12 4:41 Dinh Nguyen
2026-01-12 7:34 ` Krzysztof Kozlowski
2026-01-12 16:42 ` Rob Herring
0 siblings, 2 replies; 5+ messages in thread
From: Dinh Nguyen @ 2026-01-12 4:41 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt; +Cc: dinguyen, devicetree
The node names in a DTS file should be using a hyphen, not an underscore
as warned by 'dtc W=2'.
For clock nodes, use clock-controller@address and clock-<name>. While at
it, fix DTS coding style to use lowercase hex for values and unit
addresses for these clock nodes.
There are no functional change in this patch.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: used clock-controller@address and clock-name
reworded commit message
---
arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 128 +++++++++----------
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
index 35be14150f41..28494aeb71b2 100644
--- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
+++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
@@ -131,17 +131,17 @@ osc2: osc2 {
compatible = "fixed-clock";
};
- f2s_periph_ref_clk: f2s_periph_ref_clk {
+ f2s_periph_ref_clk: clock-f2s-periph-ref {
#clock-cells = <0>;
compatible = "fixed-clock";
};
- f2s_sdram_ref_clk: f2s_sdram_ref_clk {
+ f2s_sdram_ref_clk: clock-f2s-sdram-ref {
#clock-cells = <0>;
compatible = "fixed-clock";
};
- main_pll: main_pll@40 {
+ main_pll: clock-controller@40 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -149,7 +149,7 @@ main_pll: main_pll@40 {
clocks = <&osc1>;
reg = <0x40>;
- mpuclk: mpuclk@48 {
+ mpuclk: clock-controller@48 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
@@ -157,15 +157,15 @@ mpuclk: mpuclk@48 {
reg = <0x48>;
};
- mainclk: mainclk@4c {
+ mainclk: clock-controller@4c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
div-reg = <0xe4 0 9>;
- reg = <0x4C>;
+ reg = <0x4c>;
};
- dbg_base_clk: dbg_base_clk@50 {
+ dbg_base_clk: clock-controller@50 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>, <&osc1>;
@@ -173,29 +173,29 @@ dbg_base_clk: dbg_base_clk@50 {
reg = <0x50>;
};
- main_qspi_clk: main_qspi_clk@54 {
+ main_qspi_clk: clock-controller@54 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x54>;
};
- main_nand_sdmmc_clk: main_nand_sdmmc_clk@58 {
+ main_nand_sdmmc_clk: clock-controller@58 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
reg = <0x58>;
};
- cfg_h2f_usr0_clk: cfg_h2f_usr0_clk@5c {
+ cfg_h2f_usr0_clk: clock-controller@5c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&main_pll>;
- reg = <0x5C>;
+ reg = <0x5c>;
};
};
- periph_pll: periph_pll@80 {
+ periph_pll: clock-controller@80 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -203,50 +203,50 @@ periph_pll: periph_pll@80 {
clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
reg = <0x80>;
- emac0_clk: emac0_clk@88 {
+ emac0_clk: clock-controller@88 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x88>;
};
- emac1_clk: emac1_clk@8c {
+ emac1_clk: clock-controller@8c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
- reg = <0x8C>;
+ reg = <0x8c>;
};
- per_qspi_clk: per_qsi_clk@90 {
+ per_qspi_clk: clock-controller@90 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x90>;
};
- per_nand_mmc_clk: per_nand_mmc_clk@94 {
+ per_nand_mmc_clk: clock-controller@94 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x94>;
};
- per_base_clk: per_base_clk@98 {
+ per_base_clk: clock-controller@98 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
reg = <0x98>;
};
- h2f_usr1_clk: h2f_usr1_clk@9c {
+ h2f_usr1_clk: clock-controller@9c {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&periph_pll>;
- reg = <0x9C>;
+ reg = <0x9c>;
};
};
- sdram_pll: sdram_pll@c0 {
+ sdram_pll: clock-controller@c0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
@@ -254,64 +254,64 @@ sdram_pll: sdram_pll@c0 {
clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
reg = <0xC0>;
- ddr_dqs_clk: ddr_dqs_clk@c8 {
+ ddr_dqs_clk: clock-controller@c8 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
- reg = <0xC8>;
+ reg = <0xc8>;
};
- ddr_2x_dqs_clk: ddr_2x_dqs_clk@cc {
+ ddr_2x_dqs_clk: clock-controller@cc {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
- reg = <0xCC>;
+ reg = <0xcc>;
};
- ddr_dq_clk: ddr_dq_clk@d0 {
+ ddr_dq_clk: clock-controller@d0 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
- reg = <0xD0>;
+ reg = <0xd0>;
};
- h2f_usr2_clk: h2f_usr2_clk@d4 {
+ h2f_usr2_clk: clock-controller@d4 {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&sdram_pll>;
- reg = <0xD4>;
+ reg = <0xd4>;
};
};
- mpu_periph_clk: mpu_periph_clk {
+ mpu_periph_clk: clock-mpu-periph {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <4>;
};
- mpu_l2_ram_clk: mpu_l2_ram_clk {
+ mpu_l2_ram_clk: clock-mpu-l2-ram {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&mpuclk>;
fixed-divider = <2>;
};
- l4_main_clk: l4_main_clk {
+ l4_main_clk: clock-l4-main {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>;
clk-gate = <0x60 0>;
};
- l3_main_clk: l3_main_clk {
+ l3_main_clk: clock-l3-main {
#clock-cells = <0>;
compatible = "altr,socfpga-perip-clk";
clocks = <&mainclk>;
fixed-divider = <1>;
};
- l3_mp_clk: l3_mp_clk {
+ l3_mp_clk: clock-l3-mp {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>;
@@ -319,14 +319,14 @@ l3_mp_clk: l3_mp_clk {
clk-gate = <0x60 1>;
};
- l3_sp_clk: l3_sp_clk {
+ l3_sp_clk: clock-l3-sp {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&l3_mp_clk>;
div-reg = <0x64 2 2>;
};
- l4_mp_clk: l4_mp_clk {
+ l4_mp_clk: clock-l4-mp {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>, <&per_base_clk>;
@@ -334,7 +334,7 @@ l4_mp_clk: l4_mp_clk {
clk-gate = <0x60 2>;
};
- l4_sp_clk: l4_sp_clk {
+ l4_sp_clk: clock-l4-sp {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&mainclk>, <&per_base_clk>;
@@ -342,7 +342,7 @@ l4_sp_clk: l4_sp_clk {
clk-gate = <0x60 3>;
};
- dbg_at_clk: dbg_at_clk {
+ dbg_at_clk: clock-dbg-at {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
@@ -350,7 +350,7 @@ dbg_at_clk: dbg_at_clk {
clk-gate = <0x60 4>;
};
- dbg_clk: dbg_clk {
+ dbg_clk: clock-dbg {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_at_clk>;
@@ -358,50 +358,50 @@ dbg_clk: dbg_clk {
clk-gate = <0x60 5>;
};
- dbg_trace_clk: dbg_trace_clk {
+ dbg_trace_clk: clock-dbg-trace {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
- div-reg = <0x6C 0 3>;
+ div-reg = <0x6c 0 3>;
clk-gate = <0x60 6>;
};
- dbg_timer_clk: dbg_timer_clk {
+ dbg_timer_clk: clock-dbg-timer {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&dbg_base_clk>;
clk-gate = <0x60 7>;
};
- cfg_clk: cfg_clk {
+ cfg_clk: clock-cfg {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&cfg_h2f_usr0_clk>;
clk-gate = <0x60 8>;
};
- h2f_user0_clk: h2f_user0_clk {
+ h2f_user0_clk: clock-h2f-user0 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&cfg_h2f_usr0_clk>;
clk-gate = <0x60 9>;
};
- emac_0_clk: emac_0_clk {
+ emac_0_clk: clock-emac-0 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&emac0_clk>;
clk-gate = <0xa0 0>;
};
- emac_1_clk: emac_1_clk {
+ emac_1_clk: clock-emac-1 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&emac1_clk>;
clk-gate = <0xa0 1>;
};
- usb_mp_clk: usb_mp_clk {
+ usb_mp_clk: clock-usb-mp {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -409,7 +409,7 @@ usb_mp_clk: usb_mp_clk {
div-reg = <0xa4 0 3>;
};
- spi_m_clk: spi_m_clk {
+ spi_m_clk: clock-spi-m {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -417,7 +417,7 @@ spi_m_clk: spi_m_clk {
div-reg = <0xa4 3 3>;
};
- can0_clk: can0_clk {
+ can0_clk: clock-can0 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -425,7 +425,7 @@ can0_clk: can0_clk {
div-reg = <0xa4 6 3>;
};
- can1_clk: can1_clk {
+ can1_clk: clock-can1 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -433,7 +433,7 @@ can1_clk: can1_clk {
div-reg = <0xa4 9 3>;
};
- gpio_db_clk: gpio_db_clk {
+ gpio_db_clk: clock-gpio-db {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&per_base_clk>;
@@ -441,21 +441,21 @@ gpio_db_clk: gpio_db_clk {
div-reg = <0xa8 0 24>;
};
- h2f_user1_clk: h2f_user1_clk {
+ h2f_user1_clk: clock-h2f-user1 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&h2f_usr1_clk>;
clk-gate = <0xa0 7>;
};
- sdmmc_clk: sdmmc_clk {
+ sdmmc_clk: clock-sdmmc {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
clk-gate = <0xa0 8>;
};
- sdmmc_clk_divided: sdmmc_clk_divided {
+ sdmmc_clk_divided: clock-sdmmc-divided {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&sdmmc_clk>;
@@ -463,21 +463,21 @@ sdmmc_clk_divided: sdmmc_clk_divided {
fixed-divider = <4>;
};
- nand_x_clk: nand_x_clk {
+ nand_x_clk: clock-nand-x {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
clk-gate = <0xa0 9>;
};
- nand_ecc_clk: nand_ecc_clk {
+ nand_ecc_clk: clock-nand-ecc {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&nand_x_clk>;
clk-gate = <0xa0 9>;
};
- nand_clk: nand_clk {
+ nand_clk: clock-nand {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&nand_x_clk>;
@@ -485,35 +485,35 @@ nand_clk: nand_clk {
fixed-divider = <4>;
};
- qspi_clk: qspi_clk {
+ qspi_clk: clock-qspi {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
clk-gate = <0xa0 11>;
};
- ddr_dqs_clk_gate: ddr_dqs_clk_gate {
+ ddr_dqs_clk_gate: clock-ddr-dqs-gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dqs_clk>;
clk-gate = <0xd8 0>;
};
- ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
+ ddr_2x_dqs_clk_gate: clock-ddr-2x-dqs-gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_2x_dqs_clk>;
clk-gate = <0xd8 1>;
};
- ddr_dq_clk_gate: ddr_dq_clk_gate {
+ ddr_dq_clk_gate: clock-ddr-dq-gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dq_clk>;
clk-gate = <0xd8 2>;
};
- h2f_user2_clk: h2f_user2_clk {
+ h2f_user2_clk: clock-h2f-user2 {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&h2f_usr2_clk>;
@@ -523,7 +523,7 @@ h2f_user2_clk: h2f_user2_clk {
};
};
- fpga_bridge0: fpga_bridge@ff400000 {
+ fpga_bridge0: fpga-bridge@ff400000 {
compatible = "altr,socfpga-lwhps2fpga-bridge";
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
@@ -531,7 +531,7 @@ fpga_bridge0: fpga_bridge@ff400000 {
status = "disabled";
};
- fpga_bridge1: fpga_bridge@ff500000 {
+ fpga_bridge1: fpga-bridge@ff500000 {
compatible = "altr,socfpga-hps2fpga-bridge";
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
--
2.42.0.411.g813d9a9188
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
2026-01-12 4:41 [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Dinh Nguyen
@ 2026-01-12 7:34 ` Krzysztof Kozlowski
2026-01-12 15:29 ` Dinh Nguyen
2026-01-12 16:42 ` Rob Herring
1 sibling, 1 reply; 5+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-12 7:34 UTC (permalink / raw)
To: Dinh Nguyen, robh, krzk+dt, conor+dt; +Cc: devicetree
On 12/01/2026 05:41, Dinh Nguyen wrote:
> The node names in a DTS file should be using a hyphen, not an underscore
> as warned by 'dtc W=2'.
>
> For clock nodes, use clock-controller@address and clock-<name>. While at
> it, fix DTS coding style to use lowercase hex for values and unit
> addresses for these clock nodes.
>
> There are no functional change in this patch.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v2: used clock-controller@address and clock-name
> reworded commit message
> ---
> arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 128 +++++++++----------
> 1 file changed, 64 insertions(+), 64 deletions(-)
>
> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
> index 35be14150f41..28494aeb71b2 100644
> --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
> @@ -131,17 +131,17 @@ osc2: osc2 {
> compatible = "fixed-clock";
> };
>
> - f2s_periph_ref_clk: f2s_periph_ref_clk {
> + f2s_periph_ref_clk: clock-f2s-periph-ref {
> #clock-cells = <0>;
> compatible = "fixed-clock";
I am pretty sure this is functional change, because you just changed the
name of the clock. At least that is the impression of above diff.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
2026-01-12 7:34 ` Krzysztof Kozlowski
@ 2026-01-12 15:29 ` Dinh Nguyen
2026-01-12 15:50 ` Krzysztof Kozlowski
0 siblings, 1 reply; 5+ messages in thread
From: Dinh Nguyen @ 2026-01-12 15:29 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh, krzk+dt, conor+dt; +Cc: devicetree
On 1/12/26 01:34, Krzysztof Kozlowski wrote:
> On 12/01/2026 05:41, Dinh Nguyen wrote:
>> The node names in a DTS file should be using a hyphen, not an underscore
>> as warned by 'dtc W=2'.
>>
>> For clock nodes, use clock-controller@address and clock-<name>. While at
>> it, fix DTS coding style to use lowercase hex for values and unit
>> addresses for these clock nodes.
>>
>> There are no functional change in this patch.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> v2: used clock-controller@address and clock-name
>> reworded commit message
>> ---
>> arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 128 +++++++++----------
>> 1 file changed, 64 insertions(+), 64 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
>> index 35be14150f41..28494aeb71b2 100644
>> --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
>> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
>> @@ -131,17 +131,17 @@ osc2: osc2 {
>> compatible = "fixed-clock";
>> };
>>
>> - f2s_periph_ref_clk: f2s_periph_ref_clk {
>> + f2s_periph_ref_clk: clock-f2s-periph-ref {
>> #clock-cells = <0>;
>> compatible = "fixed-clock";
>
> I am pretty sure this is functional change, because you just changed the
> name of the clock. At least that is the impression of above diff.
>
Thanks for the review. I'll check it with dtx_diff and fdtdump. I just
don't see the the clock names getting used anywhere.
Dinh
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
2026-01-12 15:29 ` Dinh Nguyen
@ 2026-01-12 15:50 ` Krzysztof Kozlowski
0 siblings, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-12 15:50 UTC (permalink / raw)
To: Dinh Nguyen, robh, krzk+dt, conor+dt; +Cc: devicetree
On 12/01/2026 16:29, Dinh Nguyen wrote:
>
>
> On 1/12/26 01:34, Krzysztof Kozlowski wrote:
>> On 12/01/2026 05:41, Dinh Nguyen wrote:
>>> The node names in a DTS file should be using a hyphen, not an underscore
>>> as warned by 'dtc W=2'.
>>>
>>> For clock nodes, use clock-controller@address and clock-<name>. While at
>>> it, fix DTS coding style to use lowercase hex for values and unit
>>> addresses for these clock nodes.
>>>
>>> There are no functional change in this patch.
>>>
>>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>>> ---
>>> v2: used clock-controller@address and clock-name
>>> reworded commit message
>>> ---
>>> arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 128 +++++++++----------
>>> 1 file changed, 64 insertions(+), 64 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
>>> index 35be14150f41..28494aeb71b2 100644
>>> --- a/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
>>> +++ b/arch/arm/boot/dts/intel/socfpga/socfpga.dtsi
>>> @@ -131,17 +131,17 @@ osc2: osc2 {
>>> compatible = "fixed-clock";
>>> };
>>>
>>> - f2s_periph_ref_clk: f2s_periph_ref_clk {
>>> + f2s_periph_ref_clk: clock-f2s-periph-ref {
>>> #clock-cells = <0>;
>>> compatible = "fixed-clock";
>>
>> I am pretty sure this is functional change, because you just changed the
>> name of the clock. At least that is the impression of above diff.
>>
>
> Thanks for the review. I'll check it with dtx_diff and fdtdump. I just
Clock name won't be in DT.
> don't see the the clock names getting used anywhere.
I don't know if your drivers use clock names, but many platforms
especially legacy ones do. Whether this change has actual impact is a
bit different question, I just pointed out that there is an functional
change.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi
2026-01-12 4:41 [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Dinh Nguyen
2026-01-12 7:34 ` Krzysztof Kozlowski
@ 2026-01-12 16:42 ` Rob Herring
1 sibling, 0 replies; 5+ messages in thread
From: Rob Herring @ 2026-01-12 16:42 UTC (permalink / raw)
To: Dinh Nguyen; +Cc: devicetree, conor+dt, krzk+dt
On Sun, 11 Jan 2026 22:41:53 -0600, Dinh Nguyen wrote:
> The node names in a DTS file should be using a hyphen, not an underscore
> as warned by 'dtc W=2'.
>
> For clock nodes, use clock-controller@address and clock-<name>. While at
> it, fix DTS coding style to use lowercase hex for values and unit
> addresses for these clock nodes.
>
> There are no functional change in this patch.
>
> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
> ---
> v2: used clock-controller@address and clock-name
> reworded commit message
> ---
> arch/arm/boot/dts/intel/socfpga/socfpga.dtsi | 128 +++++++++----------
> 1 file changed, 64 insertions(+), 64 deletions(-)
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: tags/next-20260109 (exact match)
Base: tags/next-20260109 (use --merge-base to override)
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm/boot/dts/intel/' for 20260112044153.1887253-1-dinguyen@kernel.org:
arch/arm/boot/dts/intel/socfpga/socfpga_vt.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_vt.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_vt.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_vt.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_sdmmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_qspi.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10nano.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_qspi.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mcvevk.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_vining_fpga.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_sdmmc.dtb: sysmgr@ffd08000 (altr,sys-mgr): compatible: 'oneOf' conditional failed, one must be fixed:
['altr,sys-mgr', 'syscon'] is too long
'altr,sys-mgr-s10' was expected
'altr,sys-mgr' was expected
from schema $id: http://devicetree.org/schemas/soc/altera/altr,sys-mgr.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe3_emmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_emmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_arria5_socdk.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_qspi.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_chameleon96.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_qspi.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sodia.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_qspi.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socrates.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_socdk.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe3_sdmmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_pe1_sdmmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_pe1_qspi.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_emmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa1_st1_sdmmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_mercury_sa2_st1_sdmmc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dtb: clkmgr@ffd04000 (altr,clk-mgr): clocks: 'clock-can0', 'clock-can1', 'clock-cfg', 'clock-controller@40', 'clock-controller@80', 'clock-controller@c0', 'clock-dbg', 'clock-dbg-at', 'clock-dbg-timer', 'clock-dbg-trace', 'clock-ddr-2x-dqs-gate', 'clock-ddr-dq-gate', 'clock-ddr-dqs-gate', 'clock-emac-0', 'clock-emac-1', 'clock-f2s-periph-ref', 'clock-f2s-sdram-ref', 'clock-gpio-db', 'clock-h2f-user0', 'clock-h2f-user1', 'clock-h2f-user2', 'clock-l3-main', 'clock-l3-mp', 'clock-l3-sp', 'clock-l4-main', 'clock-l4-mp', 'clock-l4-sp', 'clock-mpu-l2-ram', 'clock-mpu-periph', 'clock-nand', 'clock-nand-ecc', 'clock-nand-x', 'clock-qspi', 'clock-sdmmc', 'clock-sdmmc-divided', 'clock-spi-m', 'clock-usb-mp' do not match any of the regexes: '^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$', '^osc[0-9]$', '^pinctrl-[0-9]+$'
from schema $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dtb: clocks: clock-gpio-db: {'#clock-cells': 0, 'compatible': ['altr,socfpga-gate-clk'], 'clocks': [[20]], 'clk-gate': [160, 6], 'div-reg': [168, 0, 24]} is not of type 'array'
from schema $id: http://devicetree.org/schemas/property-units.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dtb: clock-f2s-periph-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de0_nano_soc.dtb: clock-f2s-sdram-ref (fixed-clock): 'clock-frequency' is a required property
from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-01-12 16:42 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2026-01-12 4:41 [PATCHv2] ARM: dts: socfpga: remove underscore node names for base socfpga dtsi Dinh Nguyen
2026-01-12 7:34 ` Krzysztof Kozlowski
2026-01-12 15:29 ` Dinh Nguyen
2026-01-12 15:50 ` Krzysztof Kozlowski
2026-01-12 16:42 ` Rob Herring
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