* [PATCH 2/3] gpio: tegra186: Add support for Tegra264
2026-01-14 10:38 [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support Prathamesh Shete
@ 2026-01-14 10:38 ` Prathamesh Shete
2026-01-14 10:38 ` [PATCH 3/3] arm64: tegra: Add Tegra264 GPIO controllers Prathamesh Shete
2026-01-15 13:29 ` [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support Krzysztof Kozlowski
2 siblings, 0 replies; 6+ messages in thread
From: Prathamesh Shete @ 2026-01-14 10:38 UTC (permalink / raw)
To: linusw, brgl, krzk+dt, conor+dt, thierry.reding, jonathanh, robh,
linux-gpio, devicetree, linux-tegra, linux-kernel
Cc: pshete
Extend the existing Tegra186 GPIO controller driver with support for the
GPIO controller found on Tegra264.
Use the "nvidia,pmc" phandle from the GPIO device tree node to
ensure the GPIO driver associates with the intended PMC device.
Relying only on compatible-based lookup can select an unexpected
PMC node, so fall back to compatible-based lookup when the phandle
is not present.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
drivers/gpio/gpio-tegra186.c | 90 +++++++++++++++++++++++++++++++++++-
1 file changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c
index b1498b59a921..b05cfa881f6f 100644
--- a/drivers/gpio/gpio-tegra186.c
+++ b/drivers/gpio/gpio-tegra186.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2016-2025 NVIDIA Corporation
+ * Copyright (c) 2016-2026 NVIDIA Corporation
*
* Author: Thierry Reding <treding@nvidia.com>
* Dipen Patel <dpatel@nvidia.com>
@@ -21,6 +21,7 @@
#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/gpio/tegra241-gpio.h>
#include <dt-bindings/gpio/tegra256-gpio.h>
+#include <dt-bindings/gpio/tegra264-gpio.h>
/* security registers */
#define TEGRA186_GPIO_CTL_SCR 0x0c
@@ -1001,7 +1002,9 @@ static int tegra186_gpio_probe(struct platform_device *pdev)
if (gpio->soc->num_irqs_per_bank > 1)
tegra186_gpio_init_route_mapping(gpio);
- np = of_find_matching_node(NULL, tegra186_pmc_of_match);
+ np = of_parse_phandle(pdev->dev.of_node, "nvidia,pmc", 0);
+ if (!np)
+ np = of_find_matching_node(NULL, tegra186_pmc_of_match);
if (np) {
if (of_device_is_available(np)) {
irq->parent_domain = irq_find_host(np);
@@ -1277,6 +1280,80 @@ static const struct tegra_gpio_soc tegra241_aon_soc = {
.has_vm_support = false,
};
+#define TEGRA264_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
+ TEGRA_GPIO_PORT(TEGRA264_MAIN, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra264_main_ports[] = {
+ TEGRA264_MAIN_GPIO_PORT(F, 3, 0, 8),
+ TEGRA264_MAIN_GPIO_PORT(G, 3, 1, 5),
+ TEGRA264_MAIN_GPIO_PORT(H, 1, 0, 8),
+ TEGRA264_MAIN_GPIO_PORT(J, 1, 1, 8),
+ TEGRA264_MAIN_GPIO_PORT(K, 1, 2, 8),
+ TEGRA264_MAIN_GPIO_PORT(L, 1, 3, 8),
+ TEGRA264_MAIN_GPIO_PORT(M, 1, 4, 6),
+ TEGRA264_MAIN_GPIO_PORT(P, 2, 0, 8),
+ TEGRA264_MAIN_GPIO_PORT(Q, 2, 1, 8),
+ TEGRA264_MAIN_GPIO_PORT(R, 2, 2, 8),
+ TEGRA264_MAIN_GPIO_PORT(S, 2, 3, 2),
+ TEGRA264_MAIN_GPIO_PORT(T, 0, 0, 7),
+ TEGRA264_MAIN_GPIO_PORT(U, 0, 1, 8),
+ TEGRA264_MAIN_GPIO_PORT(V, 0, 2, 8),
+ TEGRA264_MAIN_GPIO_PORT(W, 0, 3, 8),
+ TEGRA264_MAIN_GPIO_PORT(X, 0, 7, 6),
+ TEGRA264_MAIN_GPIO_PORT(Y, 0, 5, 8),
+ TEGRA264_MAIN_GPIO_PORT(Z, 0, 6, 8),
+ TEGRA264_MAIN_GPIO_PORT(AL, 0, 4, 3),
+};
+
+static const struct tegra_gpio_soc tegra264_main_soc = {
+ .num_ports = ARRAY_SIZE(tegra264_main_ports),
+ .ports = tegra264_main_ports,
+ .name = "tegra264-gpio",
+ .instance = 0,
+ .num_irqs_per_bank = 8,
+ .has_vm_support = true,
+};
+
+#define TEGRA264_AON_GPIO_PORT(_name, _bank, _port, _pins) \
+ TEGRA_GPIO_PORT(TEGRA264_AON, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra264_aon_ports[] = {
+ TEGRA264_AON_GPIO_PORT(AA, 0, 0, 8),
+ TEGRA264_AON_GPIO_PORT(BB, 0, 1, 2),
+ TEGRA264_AON_GPIO_PORT(CC, 0, 2, 8),
+ TEGRA264_AON_GPIO_PORT(DD, 0, 3, 8),
+ TEGRA264_AON_GPIO_PORT(EE, 0, 4, 4)
+};
+
+static const struct tegra_gpio_soc tegra264_aon_soc = {
+ .num_ports = ARRAY_SIZE(tegra264_aon_ports),
+ .ports = tegra264_aon_ports,
+ .name = "tegra264-gpio-aon",
+ .instance = 1,
+ .num_irqs_per_bank = 8,
+ .has_vm_support = true,
+};
+
+#define TEGRA264_UPHY_GPIO_PORT(_name, _bank, _port, _pins) \
+ TEGRA_GPIO_PORT(TEGRA264_UPHY, _name, _bank, _port, _pins)
+
+static const struct tegra_gpio_port tegra264_uphy_ports[] = {
+ TEGRA264_UPHY_GPIO_PORT(A, 0, 0, 6),
+ TEGRA264_UPHY_GPIO_PORT(B, 0, 1, 8),
+ TEGRA264_UPHY_GPIO_PORT(C, 0, 2, 3),
+ TEGRA264_UPHY_GPIO_PORT(D, 1, 0, 8),
+ TEGRA264_UPHY_GPIO_PORT(E, 1, 1, 4),
+};
+
+static const struct tegra_gpio_soc tegra264_uphy_soc = {
+ .num_ports = ARRAY_SIZE(tegra264_uphy_ports),
+ .ports = tegra264_uphy_ports,
+ .name = "tegra264-gpio-uphy",
+ .instance = 2,
+ .num_irqs_per_bank = 8,
+ .has_vm_support = true,
+};
+
#define TEGRA256_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \
TEGRA_GPIO_PORT(TEGRA256_MAIN, _name, _bank, _port, _pins)
@@ -1368,6 +1445,15 @@ static const struct of_device_id tegra186_gpio_of_match[] = {
}, {
.compatible = "nvidia,tegra256-gpio",
.data = &tegra256_main_soc
+ }, {
+ .compatible = "nvidia,tegra264-gpio",
+ .data = &tegra264_main_soc
+ }, {
+ .compatible = "nvidia,tegra264-gpio-aon",
+ .data = &tegra264_aon_soc
+ }, {
+ .compatible = "nvidia,tegra264-gpio-uphy",
+ .data = &tegra264_uphy_soc
}, {
/* sentinel */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] arm64: tegra: Add Tegra264 GPIO controllers
2026-01-14 10:38 [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support Prathamesh Shete
2026-01-14 10:38 ` [PATCH 2/3] gpio: tegra186: Add support for Tegra264 Prathamesh Shete
@ 2026-01-14 10:38 ` Prathamesh Shete
2026-01-15 13:29 ` [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support Krzysztof Kozlowski
2 siblings, 0 replies; 6+ messages in thread
From: Prathamesh Shete @ 2026-01-14 10:38 UTC (permalink / raw)
To: linusw, brgl, krzk+dt, conor+dt, thierry.reding, jonathanh, robh,
linux-gpio, devicetree, linux-tegra, linux-kernel
Cc: pshete
Add device tree nodes for MAIN, AON and UPHY GPIO controller instances.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra264.dtsi | 88 ++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
index f137565da804..8cdf1c61458a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
@@ -3277,6 +3277,50 @@ rtc: rtc@c2c0000 {
status = "disabled";
};
+ gpio_main: gpio@c300000 {
+ compatible = "nvidia,tegra264-gpio";
+ reg = <0x00 0x0c300000 0x0 0x4000>,
+ <0x00 0x0c310000 0x0 0x4000>;
+ reg-names = "security", "gpio";
+ nvidia,pmc = <&pmc>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
serial@c4e0000 {
compatible = "nvidia,tegra264-utc";
reg = <0x0 0x0c4e0000 0x0 0x8000>,
@@ -3347,6 +3391,22 @@ pmc: pmc@c800000 {
#interrupt-cells = <2>;
interrupt-controller;
};
+
+ gpio_aon: gpio@cf00000 {
+ compatible = "nvidia,tegra264-gpio-aon";
+ reg = <0x0 0x0cf00000 0x0 0x10000>,
+ <0x0 0x0cf10000 0x0 0x1000>;
+ reg-names = "security", "gpio";
+ nvidia,pmc = <&pmc>;
+ interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
/* TOP_MMIO */
@@ -3726,6 +3786,34 @@ bus@a800000000 {
ranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */
<0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */
+
+ gpio_uphy: gpio@8300000 {
+ compatible = "nvidia,tegra264-gpio-uphy";
+ reg = <0x00 0x08300000 0x0 0x2000>,
+ <0x00 0x08310000 0x0 0x2000>;
+ reg-names = "security", "gpio";
+ nvidia,pmc = <&pmc>;
+ interrupts = <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
cpus {
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support
2026-01-14 10:38 [PATCH 1/3] dt-bindings: gpio: Add Tegra264 support Prathamesh Shete
2026-01-14 10:38 ` [PATCH 2/3] gpio: tegra186: Add support for Tegra264 Prathamesh Shete
2026-01-14 10:38 ` [PATCH 3/3] arm64: tegra: Add Tegra264 GPIO controllers Prathamesh Shete
@ 2026-01-15 13:29 ` Krzysztof Kozlowski
2026-01-19 22:12 ` Jon Hunter
2 siblings, 1 reply; 6+ messages in thread
From: Krzysztof Kozlowski @ 2026-01-15 13:29 UTC (permalink / raw)
To: Prathamesh Shete
Cc: linusw, brgl, krzk+dt, conor+dt, thierry.reding, jonathanh, robh,
linux-gpio, devicetree, linux-tegra, linux-kernel
On Wed, Jan 14, 2026 at 10:38:44AM +0000, Prathamesh Shete wrote:
> Extend the existing Tegra186 GPIO controller device tree bindings with
> support for the GPIO controller found on Tegra264. The number of pins
> is slightly different, but the programming model remains the same.
>
> Add a new header, include/dt-bindings/gpio/tegra264-gpio.h,
> that defines port IDs as well as the TEGRA264_MAIN_GPIO() helper,
> both of which are used in conjunction to create a unique specifier
> for each pin.
>
> Document nvidia,pmc property referencing the PMC node providing the
> parent interrupt domain. GPIO driver uses this to select the correct
Why do you need to reference parent interrupt not via interrupts but
custom phandle?
> PMC,falling back to compatible-based lookup only if the phandle is
> absent.
>
> Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
> ---
> .../bindings/gpio/nvidia,tegra186-gpio.yaml | 10 +++
> include/dt-bindings/gpio/tegra264-gpio.h | 61 +++++++++++++++++++
> 2 files changed, 71 insertions(+)
> create mode 100644 include/dt-bindings/gpio/tegra264-gpio.h
>
> diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
> index 2bd620a1099b..93150504c03c 100644
> --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
> @@ -86,6 +86,9 @@ properties:
> - nvidia,tegra234-gpio
> - nvidia,tegra234-gpio-aon
> - nvidia,tegra256-gpio
> + - nvidia,tegra264-gpio
> + - nvidia,tegra264-gpio-uphy
> + - nvidia,tegra264-gpio-aon
>
> reg-names:
> items:
> @@ -110,6 +113,10 @@ properties:
> ports, in the order the HW manual describes them. The number of entries
> required varies depending on compatible value.
>
> + nvidia,pmc:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: Phandle to the PMC node providing the parent interrupt domain.
You should require it for the new devices/compatibles.
> +
> gpio-controller: true
>
> gpio-ranges:
> @@ -157,6 +164,8 @@ allOf:
> - nvidia,tegra194-gpio
> - nvidia,tegra234-gpio
> - nvidia,tegra256-gpio
> + - nvidia,tegra264-gpio
> + - nvidia,tegra264-gpio-uphy
> then:
> properties:
> interrupts:
> @@ -171,6 +180,7 @@ allOf:
> - nvidia,tegra186-gpio-aon
> - nvidia,tegra194-gpio-aon
> - nvidia,tegra234-gpio-aon
> + - nvidia,tegra264-gpio-aon
> then:
> properties:
> interrupts:
> diff --git a/include/dt-bindings/gpio/tegra264-gpio.h b/include/dt-bindings/gpio/tegra264-gpio.h
> new file mode 100644
> index 000000000000..d7baceace474
> --- /dev/null
> +++ b/include/dt-bindings/gpio/tegra264-gpio.h
Use filenames matching compatible or bindings file.
nvidia,tegra264-gpio.h
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread